[thirdparty/u-boot.git] / board / xilinx / versal / board.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2014 - 2018 Xilinx, Inc.
 * Michal Simek <michal.simek@amd.com>
 */

#include <command.h>
#include <common.h>
#include <cpu_func.h>
#include <env.h>
#include <fdtdec.h>
#include <init.h>
#include <env_internal.h>
#include <log.h>
#include <malloc.h>
#include <time.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <versalpl.h>
#include "../common/board.h"

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_FPGA_VERSALPL)
static xilinx_desc versalpl = {
	xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op, NULL,
	FPGA_LEGACY
};
#endif

int board_init(void)
{
	printf("EL Level:\tEL%d\n", current_el());

#if defined(CONFIG_FPGA_VERSALPL)
	fpga_init();
	fpga_add(fpga_xilinx, &versalpl);
#endif

	if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
		xilinx_read_eeprom();

	return 0;
}

int board_early_init_r(void)
{
	u32 val;

	if (current_el() != 3)
		return 0;

	debug("iou_switch ctrl div0 %x\n",
	      readl(&crlapb_base->iou_switch_ctrl));

	writel(IOU_SWITCH_CTRL_CLKACT_BIT |
	       (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
	       &crlapb_base->iou_switch_ctrl);

	/* Global timer init - Program time stamp reference clk */
	val = readl(&crlapb_base->timestamp_ref_ctrl);
	val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
	writel(val, &crlapb_base->timestamp_ref_ctrl);

	debug("ref ctrl 0x%x\n",
	      readl(&crlapb_base->timestamp_ref_ctrl));

	/* Clear reset of timestamp reg */
	writel(0, &crlapb_base->rst_timestamp);

	/*
	 * Program freq register in System counter and
	 * enable system counter.
	 */
	writel(CONFIG_COUNTER_FREQUENCY,
	       &iou_scntr_secure->base_frequency_id_register);

	debug("counter val 0x%x\n",
	      readl(&iou_scntr_secure->base_frequency_id_register));

	writel(IOU_SCNTRS_CONTROL_EN,
	       &iou_scntr_secure->counter_control_register);

	debug("scntrs control 0x%x\n",
	      readl(&iou_scntr_secure->counter_control_register));
	debug("timer 0x%llx\n", get_ticks());
	debug("timer 0x%llx\n", get_ticks());

	return 0;
}

unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
			 char *const argv[])
{
	int ret = 0;

	if (current_el() > 1) {
		smp_kick_all_cpus();
		dcache_disable();
		armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
				    ES_TO_AARCH64);
	} else {
		printf("FAIL: current EL is not above EL1\n");
		ret = EINVAL;
	}
	return ret;
}

static u8 versal_get_bootmode(void)
{
	u8 bootmode;
	u32 reg = 0;

	reg = readl(&crp_base->boot_mode_usr);

	if (reg >> BOOT_MODE_ALT_SHIFT)
		reg >>= BOOT_MODE_ALT_SHIFT;

	bootmode = reg & BOOT_MODES_MASK;

	return bootmode;
}

static int boot_targets_setup(void)
{
	u8 bootmode;
	struct udevice *dev;
	int bootseq = -1;
	int bootseq_len = 0;
	int env_targets_len = 0;
	const char *mode = NULL;
	char *new_targets;
	char *env_targets;

	bootmode = versal_get_bootmode();

	puts("Bootmode: ");
	switch (bootmode) {
	case USB_MODE:
		puts("USB_MODE\n");
		mode = "usb_dfu0 usb_dfu1";
		break;
	case JTAG_MODE:
		puts("JTAG_MODE\n");
		mode = "jtag pxe dhcp";
		break;
	case QSPI_MODE_24BIT:
		puts("QSPI_MODE_24\n");
		mode = "xspi0";
		break;
	case QSPI_MODE_32BIT:
		puts("QSPI_MODE_32\n");
		mode = "xspi0";
		break;
	case OSPI_MODE:
		puts("OSPI_MODE\n");
		mode = "xspi0";
		break;
	case EMMC_MODE:
		puts("EMMC_MODE\n");
		if (uclass_get_device_by_name(UCLASS_MMC,
					      "mmc@f1050000", &dev) &&
		    uclass_get_device_by_name(UCLASS_MMC,
					      "sdhci@f1050000", &dev)) {
			debug("SD1 driver for SD1 device is not present\n");
			break;
		}
		debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
		mode = "mmc";
		bootseq = dev_seq(dev);
		break;
	case SELECTMAP_MODE:
		puts("SELECTMAP_MODE\n");
		break;
	case SD_MODE:
		puts("SD_MODE\n");
		if (uclass_get_device_by_name(UCLASS_MMC,
					      "mmc@f1040000", &dev) &&
		    uclass_get_device_by_name(UCLASS_MMC,
					      "sdhci@f1040000", &dev)) {
			debug("SD0 driver for SD0 device is not present\n");
			break;
		}
		debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));

		mode = "mmc";
		bootseq = dev_seq(dev);
		break;
	case SD1_LSHFT_MODE:
		puts("LVL_SHFT_");
		/* fall through */
	case SD_MODE1:
		puts("SD_MODE1\n");
		if (uclass_get_device_by_name(UCLASS_MMC,
					      "mmc@f1050000", &dev) &&
		    uclass_get_device_by_name(UCLASS_MMC,
					      "sdhci@f1050000", &dev)) {
			debug("SD1 driver for SD1 device is not present\n");
			break;
		}
		debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));

		mode = "mmc";
		bootseq = dev_seq(dev);
		break;
	default:
		printf("Invalid Boot Mode:0x%x\n", bootmode);
		break;
	}

	if (mode) {
		if (bootseq >= 0) {
			bootseq_len = snprintf(NULL, 0, "%i", bootseq);
			debug("Bootseq len: %x\n", bootseq_len);
		}

		/*
		 * One terminating char + one byte for space between mode
		 * and default boot_targets
		 */
		env_targets = env_get("boot_targets");
		if (env_targets)
			env_targets_len = strlen(env_targets);

		new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
				     bootseq_len);
		if (!new_targets)
			return -ENOMEM;

		if (bootseq >= 0)
			sprintf(new_targets, "%s%x %s", mode, bootseq,
				env_targets ? env_targets : "");
		else
			sprintf(new_targets, "%s %s", mode,
				env_targets ? env_targets : "");

		env_set("boot_targets", new_targets);
	}

	return 0;
}

int board_late_init(void)
{
	int ret;

	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
		debug("Saved variables - Skipping\n");
		return 0;
	}

	if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
		return 0;

	if (IS_ENABLED(CONFIG_DISTRO_DEFAULTS)) {
		ret = boot_targets_setup();
		if (ret)
			return ret;
	}

	return board_late_init_xilinx();
}

int dram_init_banksize(void)
{
	int ret;

	ret = fdtdec_setup_memory_banksize();
	if (ret)
		return ret;

	mem_map_fill();

	return 0;
}

int dram_init(void)
{
	if (fdtdec_setup_mem_size_base_lowest() != 0)
		return -EINVAL;

	return 0;
}

void reset_cpu(void)
{
}

#if defined(CONFIG_ENV_IS_NOWHERE)
enum env_location env_get_location(enum env_operation op, int prio)
{
	u32 bootmode = versal_get_bootmode();

	if (prio)
		return ENVL_UNKNOWN;

	switch (bootmode) {
	case EMMC_MODE:
	case SD_MODE:
	case SD1_LSHFT_MODE:
	case SD_MODE1:
		if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
			return ENVL_FAT;
		if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
			return ENVL_EXT4;
		return ENVL_NOWHERE;
	case OSPI_MODE:
	case QSPI_MODE_24BIT:
	case QSPI_MODE_32BIT:
		if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
			return ENVL_SPI_FLASH;
		return ENVL_NOWHERE;
	case JTAG_MODE:
	case SELECTMAP_MODE:
	default:
		return ENVL_NOWHERE;
	}
}
#endif
Commit	Line	Data
ec48b6c9 MS	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* (C) Copyright 2014 - 2018 Xilinx, Inc.
174d7284	4	* Michal Simek <michal.simek@amd.com>
ec48b6c9 MS	5	*/
ec48b6c9 MS	6
1d15612b	7	#include <command.h>
d678a59d	8	#include <common.h>
9a3b4ceb	9	#include <cpu_func.h>
09140113	10	#include <env.h>
ec48b6c9	11	#include <fdtdec.h>
5255932f	12	#include <init.h>
4fb83c9c	13	#include <env_internal.h>
f7ae49fc	14	#include <log.h>
ec48b6c9	15	#include <malloc.h>
1045315d	16	#include <time.h>
90526e9f	17	#include <asm/cache.h>
401d1c4f	18	#include <asm/global_data.h>
ec48b6c9 MS	19	#include <asm/io.h>
ec48b6c9 MS	20	#include <asm/arch/hardware.h>
aef149e9	21	#include <asm/arch/sys_proto.h>
bfd092f9 SDPP	22	#include <dm/device.h>
bfd092f9 SDPP	23	#include <dm/uclass.h>
26e054c9	24	#include <versalpl.h>
80fdef12	25	#include "../common/board.h"
ec48b6c9 MS	26
	27	DECLARE_GLOBAL_DATA_PTR;
	28
26e054c9	29	#if defined(CONFIG_FPGA_VERSALPL)
d7fcbfc1 OS	30	static xilinx_desc versalpl = {
	31	xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op, NULL,
	32	FPGA_LEGACY
	33	};
26e054c9 SDPP	34	#endif
26e054c9 SDPP	35
ec48b6c9 MS	36	int board_init(void)
	37	{
	38	printf("EL Level:\tEL%d\n", current_el());
	39
26e054c9 SDPP	40	#if defined(CONFIG_FPGA_VERSALPL)
	41	fpga_init();
	42	fpga_add(fpga_xilinx, &versalpl);
	43	#endif
	44
d61728c8 MS	45	if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
	46	xilinx_read_eeprom();
	47
ec48b6c9 MS	48	return 0;
	49	}
	50
	51	int board_early_init_r(void)
	52	{
fb771793 MS	53	u32 val;
	54
	55	if (current_el() != 3)
	56	return 0;
	57
47a766f9 MS	58	debug("iou_switch ctrl div0 %x\n",
	59	readl(&crlapb_base->iou_switch_ctrl));
	60
fb771793	61	writel(IOU_SWITCH_CTRL_CLKACT_BIT \|
47a766f9	62	(CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
fb771793 MS	63	&crlapb_base->iou_switch_ctrl);
	64
	65	/* Global timer init - Program time stamp reference clk */
	66	val = readl(&crlapb_base->timestamp_ref_ctrl);
	67	val \|= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
	68	writel(val, &crlapb_base->timestamp_ref_ctrl);
	69
	70	debug("ref ctrl 0x%x\n",
	71	readl(&crlapb_base->timestamp_ref_ctrl));
	72
	73	/* Clear reset of timestamp reg */
	74	writel(0, &crlapb_base->rst_timestamp);
	75
	76	/*
	77	* Program freq register in System counter and
	78	* enable system counter.
	79	*/
d8c033a9	80	writel(CONFIG_COUNTER_FREQUENCY,
fb771793 MS	81	&iou_scntr_secure->base_frequency_id_register);
	82
	83	debug("counter val 0x%x\n",
	84	readl(&iou_scntr_secure->base_frequency_id_register));
	85
	86	writel(IOU_SCNTRS_CONTROL_EN,
	87	&iou_scntr_secure->counter_control_register);
	88
	89	debug("scntrs control 0x%x\n",
	90	readl(&iou_scntr_secure->counter_control_register));
	91	debug("timer 0x%llx\n", get_ticks());
	92	debug("timer 0x%llx\n", get_ticks());
ec48b6c9 MS	93
	94	return 0;
	95	}
	96
2eeceb48 ARS	97	unsigned long do_go_exec(ulong (entry)(int, char const []), int argc,
	98	char *const argv[])
	99	{
	100	int ret = 0;
	101
	102	if (current_el() > 1) {
	103	smp_kick_all_cpus();
	104	dcache_disable();
	105	armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
	106	ES_TO_AARCH64);
	107	} else {
	108	printf("FAIL: current EL is not above EL1\n");
	109	ret = EINVAL;
	110	}
	111	return ret;
	112	}
	113
51f6c52e	114	static u8 versal_get_bootmode(void)
bfd092f9	115	{
51f6c52e	116	u8 bootmode;
bfd092f9	117	u32 reg = 0;
51f6c52e MS	118
	119	reg = readl(&crp_base->boot_mode_usr);
	120
	121	if (reg >> BOOT_MODE_ALT_SHIFT)
	122	reg >>= BOOT_MODE_ALT_SHIFT;
	123
	124	bootmode = reg & BOOT_MODES_MASK;
	125
	126	return bootmode;
	127	}
	128
6ec17a2c	129	static int boot_targets_setup(void)
51f6c52e	130	{
bfd092f9 SDPP	131	u8 bootmode;
	132	struct udevice *dev;
	133	int bootseq = -1;
	134	int bootseq_len = 0;
	135	int env_targets_len = 0;
b687f5d2	136	const char *mode = NULL;
bfd092f9 SDPP	137	char *new_targets;
	138	char *env_targets;
	139
51f6c52e	140	bootmode = versal_get_bootmode();
bfd092f9 SDPP	141
	142	puts("Bootmode: ");
	143	switch (bootmode) {
f0c16cd6 KR	144	case USB_MODE:
f0c16cd6 KR	145	puts("USB_MODE\n");
82cb49dc	146	mode = "usb_dfu0 usb_dfu1";
f0c16cd6	147	break;
bfd092f9 SDPP	148	case JTAG_MODE:
bfd092f9 SDPP	149	puts("JTAG_MODE\n");
3d865acb	150	mode = "jtag pxe dhcp";
bfd092f9 SDPP	151	break;
	152	case QSPI_MODE_24BIT:
	153	puts("QSPI_MODE_24\n");
	154	mode = "xspi0";
	155	break;
	156	case QSPI_MODE_32BIT:
	157	puts("QSPI_MODE_32\n");
	158	mode = "xspi0";
	159	break;
	160	case OSPI_MODE:
	161	puts("OSPI_MODE\n");
	162	mode = "xspi0";
	163	break;
	164	case EMMC_MODE:
	165	puts("EMMC_MODE\n");
7c5b7bb1	166	if (uclass_get_device_by_name(UCLASS_MMC,
5f4e1ff7 KR	167	"mmc@f1050000", &dev) &&
5f4e1ff7 KR	168	uclass_get_device_by_name(UCLASS_MMC,
7c5b7bb1	169	"sdhci@f1050000", &dev)) {
b687f5d2 VYA	170	debug("SD1 driver for SD1 device is not present\n");
b687f5d2 VYA	171	break;
7c5b7bb1	172	}
8b85dfc6	173	debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
7c5b7bb1	174	mode = "mmc";
8b85dfc6	175	bootseq = dev_seq(dev);
bfd092f9	176	break;
facfa565 PL	177	case SELECTMAP_MODE:
	178	puts("SELECTMAP_MODE\n");
	179	break;
bfd092f9 SDPP	180	case SD_MODE:
	181	puts("SD_MODE\n");
	182	if (uclass_get_device_by_name(UCLASS_MMC,
5f4e1ff7 KR	183	"mmc@f1040000", &dev) &&
5f4e1ff7 KR	184	uclass_get_device_by_name(UCLASS_MMC,
bfd092f9	185	"sdhci@f1040000", &dev)) {
b687f5d2 VYA	186	debug("SD0 driver for SD0 device is not present\n");
b687f5d2 VYA	187	break;
bfd092f9	188	}
8b85dfc6	189	debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
bfd092f9 SDPP	190
bfd092f9 SDPP	191	mode = "mmc";
8b85dfc6	192	bootseq = dev_seq(dev);
bfd092f9 SDPP	193	break;
	194	case SD1_LSHFT_MODE:
	195	puts("LVL_SHFT_");
	196	/* fall through */
	197	case SD_MODE1:
	198	puts("SD_MODE1\n");
	199	if (uclass_get_device_by_name(UCLASS_MMC,
5f4e1ff7 KR	200	"mmc@f1050000", &dev) &&
5f4e1ff7 KR	201	uclass_get_device_by_name(UCLASS_MMC,
bfd092f9	202	"sdhci@f1050000", &dev)) {
b687f5d2 VYA	203	debug("SD1 driver for SD1 device is not present\n");
b687f5d2 VYA	204	break;
bfd092f9	205	}
8b85dfc6	206	debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
bfd092f9 SDPP	207
bfd092f9 SDPP	208	mode = "mmc";
8b85dfc6	209	bootseq = dev_seq(dev);
bfd092f9 SDPP	210	break;
bfd092f9 SDPP	211	default:
bfd092f9 SDPP	212	printf("Invalid Boot Mode:0x%x\n", bootmode);
	213	break;
	214	}
	215
b687f5d2 VYA	216	if (mode) {
	217	if (bootseq >= 0) {
	218	bootseq_len = snprintf(NULL, 0, "%i", bootseq);
	219	debug("Bootseq len: %x\n", bootseq_len);
	220	}
bfd092f9	221
b687f5d2 VYA	222	/*
	223	* One terminating char + one byte for space between mode
	224	* and default boot_targets
	225	*/
	226	env_targets = env_get("boot_targets");
	227	if (env_targets)
	228	env_targets_len = strlen(env_targets);
	229
	230	new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
	231	bootseq_len);
	232	if (!new_targets)
	233	return -ENOMEM;
	234
	235	if (bootseq >= 0)
	236	sprintf(new_targets, "%s%x %s", mode, bootseq,
	237	env_targets ? env_targets : "");
	238	else
	239	sprintf(new_targets, "%s %s", mode,
	240	env_targets ? env_targets : "");
	241
	242	env_set("boot_targets", new_targets);
	243	}
bfd092f9	244
6ec17a2c MS	245	return 0;
	246	}
	247
	248	int board_late_init(void)
	249	{
	250	int ret;
	251
	252	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
	253	debug("Saved variables - Skipping\n");
	254	return 0;
	255	}
	256
	257	if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
	258	return 0;
	259
	260	if (IS_ENABLED(CONFIG_DISTRO_DEFAULTS)) {
	261	ret = boot_targets_setup();
	262	if (ret)
	263	return ret;
	264	}
	265
80fdef12	266	return board_late_init_xilinx();
bfd092f9 SDPP	267	}
bfd092f9 SDPP	268
ec48b6c9 MS	269	int dram_init_banksize(void)
ec48b6c9 MS	270	{
aef149e9 MS	271	int ret;
	272
	273	ret = fdtdec_setup_memory_banksize();
	274	if (ret)
	275	return ret;
	276
	277	mem_map_fill();
ec48b6c9 MS	278
	279	return 0;
	280	}
	281
	282	int dram_init(void)
	283	{
22b6bb6c	284	if (fdtdec_setup_mem_size_base_lowest() != 0)
ec48b6c9 MS	285	return -EINVAL;
	286
	287	return 0;
	288	}
	289
35b65dd8	290	void reset_cpu(void)
ec48b6c9 MS	291	{
ec48b6c9 MS	292	}
4fb83c9c	293
097ccdf9	294	#if defined(CONFIG_ENV_IS_NOWHERE)
4fb83c9c ARS	295	enum env_location env_get_location(enum env_operation op, int prio)
	296	{
	297	u32 bootmode = versal_get_bootmode();
	298
	299	if (prio)
	300	return ENVL_UNKNOWN;
	301
	302	switch (bootmode) {
	303	case EMMC_MODE:
	304	case SD_MODE:
	305	case SD1_LSHFT_MODE:
	306	case SD_MODE1:
	307	if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
	308	return ENVL_FAT;
	309	if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
	310	return ENVL_EXT4;
bf97c460	311	return ENVL_NOWHERE;
4fb83c9c ARS	312	case OSPI_MODE:
	313	case QSPI_MODE_24BIT:
	314	case QSPI_MODE_32BIT:
	315	if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
	316	return ENVL_SPI_FLASH;
bf97c460	317	return ENVL_NOWHERE;
4fb83c9c	318	case JTAG_MODE:
facfa565	319	case SELECTMAP_MODE:
4fb83c9c ARS	320	default:
	321	return ENVL_NOWHERE;
	322	}
	323	}
097ccdf9	324	#endif