[people/ms/u-boot.git] / board / xilinx / zynq / board.c

/*
 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <fdtdec.h>
#include <fpga.h>
#include <mmc.h>
#include <netdev.h>
#include <zynqpl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>

DECLARE_GLOBAL_DATA_PTR;

#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
static xilinx_desc fpga;

/* It can be done differently */
static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
#endif

int board_init(void)
{
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
	u32 idcode;

	idcode = zynq_slcr_get_idcode();

	switch (idcode) {
	case XILINX_ZYNQ_7010:
		fpga = fpga010;
		break;
	case XILINX_ZYNQ_7015:
		fpga = fpga015;
		break;
	case XILINX_ZYNQ_7020:
		fpga = fpga020;
		break;
	case XILINX_ZYNQ_7030:
		fpga = fpga030;
		break;
	case XILINX_ZYNQ_7045:
		fpga = fpga045;
		break;
	case XILINX_ZYNQ_7100:
		fpga = fpga100;
		break;
	}
#endif

#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
	fpga_init();
	fpga_add(fpga_xilinx, &fpga);
#endif

	return 0;
}

int board_late_init(void)
{
	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
	case ZYNQ_BM_NOR:
		setenv("modeboot", "norboot");
		break;
	case ZYNQ_BM_SD:
		setenv("modeboot", "sdboot");
		break;
	case ZYNQ_BM_JTAG:
		setenv("modeboot", "jtagboot");
		break;
	default:
		setenv("modeboot", "");
		break;
	}

	return 0;
}

int board_eth_init(bd_t *bis)
{
	u32 ret = 0;

#ifdef CONFIG_XILINX_AXIEMAC
	ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
						XILINX_AXIDMA_BASEADDR);
#endif
#ifdef CONFIG_XILINX_EMACLITE
	u32 txpp = 0;
	u32 rxpp = 0;
# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
	txpp = 1;
# endif
# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
	rxpp = 1;
# endif
	ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
			txpp, rxpp);
#endif

#if defined(CONFIG_ZYNQ_GEM)
# if defined(CONFIG_ZYNQ_GEM0)
	ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
						CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
# endif
# if defined(CONFIG_ZYNQ_GEM1)
	ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
						CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
# endif
#endif
	return ret;
}

#ifdef CONFIG_CMD_MMC
int board_mmc_init(bd_t *bd)
{
	int ret = 0;

#if defined(CONFIG_ZYNQ_SDHCI)
# if defined(CONFIG_ZYNQ_SDHCI0)
	ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
# endif
# if defined(CONFIG_ZYNQ_SDHCI1)
	ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
# endif
#endif
	return ret;
}
#endif

int dram_init(void)
{
#ifdef CONFIG_OF_CONTROL
	int node;
	fdt_addr_t addr;
	fdt_size_t size;
	const void *blob = gd->fdt_blob;

	node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
					     "memory", 7);
	if (node == -FDT_ERR_NOTFOUND) {
		debug("ZYNQ DRAM: Can't get memory node\n");
		return -1;
	}
	addr = fdtdec_get_addr_size(blob, node, "reg", &size);
	if (addr == FDT_ADDR_T_NONE || size == 0) {
		debug("ZYNQ DRAM: Can't get base address or size\n");
		return -1;
	}
	gd->ram_size = size;
#else
	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#endif
	zynq_ddrc_init();

	return 0;
}
Commit	Line	Data
f22651cf MS	1	/*
	2	* (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
	3	*
3765b3e7	4	* SPDX-License-Identifier: GPL-2.0+
f22651cf MS	5	*/
	6
	7	#include <common.h>
9e0e37ac	8	#include <fdtdec.h>
5b73caff MS	9	#include <fpga.h>
5b73caff MS	10	#include <mmc.h>
f22651cf	11	#include <netdev.h>
d5dae85f	12	#include <zynqpl.h>
7193653e MS	13	#include <asm/arch/hardware.h>
7193653e MS	14	#include <asm/arch/sys_proto.h>
f22651cf MS	15
	16	DECLARE_GLOBAL_DATA_PTR;
	17
0b680206 MS	18	#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) \|\| \
0b680206 MS	19	(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
5b73caff	20	static xilinx_desc fpga;
d5dae85f MS	21
d5dae85f MS	22	/* It can be done differently */
5b73caff MS	23	static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
	24	static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
	25	static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
	26	static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
	27	static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
	28	static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
d5dae85f MS	29	#endif
d5dae85f MS	30
f22651cf MS	31	int board_init(void)
f22651cf MS	32	{
0b680206 MS	33	#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) \|\| \
0b680206 MS	34	(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
d5dae85f MS	35	u32 idcode;
	36
	37	idcode = zynq_slcr_get_idcode();
	38
	39	switch (idcode) {
	40	case XILINX_ZYNQ_7010:
	41	fpga = fpga010;
	42	break;
31993d6a MS	43	case XILINX_ZYNQ_7015:
	44	fpga = fpga015;
	45	break;
d5dae85f MS	46	case XILINX_ZYNQ_7020:
	47	fpga = fpga020;
	48	break;
	49	case XILINX_ZYNQ_7030:
	50	fpga = fpga030;
	51	break;
	52	case XILINX_ZYNQ_7045:
	53	fpga = fpga045;
	54	break;
fd2b10b6 MS	55	case XILINX_ZYNQ_7100:
	56	fpga = fpga100;
	57	break;
d5dae85f MS	58	}
	59	#endif
	60
0b680206 MS	61	#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) \|\| \
0b680206 MS	62	(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
d5dae85f MS	63	fpga_init();
	64	fpga_add(fpga_xilinx, &fpga);
	65	#endif
	66
f22651cf MS	67	return 0;
	68	}
	69
b3de9249 JT	70	int board_late_init(void)
	71	{
	72	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
	73	case ZYNQ_BM_NOR:
	74	setenv("modeboot", "norboot");
	75	break;
	76	case ZYNQ_BM_SD:
	77	setenv("modeboot", "sdboot");
	78	break;
	79	case ZYNQ_BM_JTAG:
	80	setenv("modeboot", "jtagboot");
	81	break;
	82	default:
	83	setenv("modeboot", "");
	84	break;
	85	}
	86
	87	return 0;
	88	}
f22651cf	89
f22651cf MS	90	int board_eth_init(bd_t *bis)
	91	{
	92	u32 ret = 0;
	93
2d83d33a MS	94	#ifdef CONFIG_XILINX_AXIEMAC
	95	ret \|= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
	96	XILINX_AXIDMA_BASEADDR);
	97	#endif
	98	#ifdef CONFIG_XILINX_EMACLITE
	99	u32 txpp = 0;
	100	u32 rxpp = 0;
	101	# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
	102	txpp = 1;
	103	# endif
	104	# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
	105	rxpp = 1;
	106	# endif
	107	ret \|= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
	108	txpp, rxpp);
	109	#endif
	110
7193653e MS	111	#if defined(CONFIG_ZYNQ_GEM)
7193653e MS	112	# if defined(CONFIG_ZYNQ_GEM0)
117cd4cc	113	ret \|= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
01fbf310	114	CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
7193653e MS	115	# endif
7193653e MS	116	# if defined(CONFIG_ZYNQ_GEM1)
117cd4cc	117	ret \|= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
01fbf310	118	CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
7193653e	119	# endif
f22651cf	120	#endif
f22651cf MS	121	return ret;
f22651cf MS	122	}
f22651cf	123
293eb33f MS	124	#ifdef CONFIG_CMD_MMC
	125	int board_mmc_init(bd_t *bd)
	126	{
	127	int ret = 0;
	128
	129	#if defined(CONFIG_ZYNQ_SDHCI)
	130	# if defined(CONFIG_ZYNQ_SDHCI0)
	131	ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
	132	# endif
	133	# if defined(CONFIG_ZYNQ_SDHCI1)
	134	ret \|= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
	135	# endif
	136	#endif
	137	return ret;
	138	}
	139	#endif
	140
f22651cf MS	141	int dram_init(void)
f22651cf MS	142	{
9e0e37ac MS	143	#ifdef CONFIG_OF_CONTROL
	144	int node;
	145	fdt_addr_t addr;
	146	fdt_size_t size;
	147	const void *blob = gd->fdt_blob;
	148
	149	node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
	150	"memory", 7);
	151	if (node == -FDT_ERR_NOTFOUND) {
	152	debug("ZYNQ DRAM: Can't get memory node\n");
	153	return -1;
	154	}
	155	addr = fdtdec_get_addr_size(blob, node, "reg", &size);
	156	if (addr == FDT_ADDR_T_NONE \|\| size == 0) {
	157	debug("ZYNQ DRAM: Can't get base address or size\n");
	158	return -1;
	159	}
	160	gd->ram_size = size;
	161	#else
f22651cf	162	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
9e0e37ac	163	#endif
148ba55c MS	164	zynq_ddrc_init();
148ba55c MS	165
f22651cf MS	166	return 0;
f22651cf MS	167	}