]>
Commit | Line | Data |
---|---|---|
83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
f22651cf MS |
2 | /* |
3 | * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> | |
3e1b61de | 4 | * (C) Copyright 2013 - 2018 Xilinx, Inc. |
f22651cf MS |
5 | */ |
6 | ||
d678a59d | 7 | #include <common.h> |
340760ec ASS |
8 | #include <debug_uart.h> |
9 | #include <dfu.h> | |
5255932f | 10 | #include <init.h> |
62b96262 | 11 | #include <log.h> |
e6cc3b25 | 12 | #include <dm/uclass.h> |
9fb625ce | 13 | #include <env.h> |
cd08513b | 14 | #include <env_internal.h> |
9e0e37ac | 15 | #include <fdtdec.h> |
5b73caff | 16 | #include <fpga.h> |
3c7b4c35 | 17 | #include <malloc.h> |
c67fecd2 | 18 | #include <memalign.h> |
5b73caff | 19 | #include <mmc.h> |
0ecd14e6 | 20 | #include <watchdog.h> |
e6cc3b25 | 21 | #include <wdt.h> |
d5dae85f | 22 | #include <zynqpl.h> |
401d1c4f | 23 | #include <asm/global_data.h> |
7193653e MS |
24 | #include <asm/arch/hardware.h> |
25 | #include <asm/arch/sys_proto.h> | |
80fdef12 | 26 | #include "../common/board.h" |
f22651cf MS |
27 | |
28 | DECLARE_GLOBAL_DATA_PTR; | |
29 | ||
05f0f269 MS |
30 | #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DEBUG_UART_BOARD_INIT) |
31 | void board_debug_uart_init(void) | |
32 | { | |
33 | /* Add initialization sequence if UART is not configured */ | |
34 | } | |
35 | #endif | |
36 | ||
f22651cf MS |
37 | int board_init(void) |
38 | { | |
98757d87 MS |
39 | if (IS_ENABLED(CONFIG_SPL_BUILD)) |
40 | printf("Silicon version:\t%d\n", zynq_get_silicon_version()); | |
41 | ||
2fe55d18 MS |
42 | if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM)) |
43 | xilinx_read_eeprom(); | |
44 | ||
f22651cf MS |
45 | return 0; |
46 | } | |
47 | ||
b3de9249 JT |
48 | int board_late_init(void) |
49 | { | |
3c7b4c35 SDPP |
50 | int env_targets_len = 0; |
51 | const char *mode; | |
52 | char *new_targets; | |
53 | char *env_targets; | |
54 | ||
62b96262 MS |
55 | if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { |
56 | debug("Saved variables - Skipping\n"); | |
57 | return 0; | |
58 | } | |
59 | ||
b2561c5b | 60 | if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) |
62b96262 MS |
61 | return 0; |
62 | ||
b3de9249 | 63 | switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { |
085b2b82 | 64 | case ZYNQ_BM_QSPI: |
3c7b4c35 | 65 | mode = "qspi"; |
382bee57 | 66 | env_set("modeboot", "qspiboot"); |
085b2b82 MS |
67 | break; |
68 | case ZYNQ_BM_NAND: | |
3c7b4c35 | 69 | mode = "nand"; |
382bee57 | 70 | env_set("modeboot", "nandboot"); |
085b2b82 | 71 | break; |
b3de9249 | 72 | case ZYNQ_BM_NOR: |
3c7b4c35 | 73 | mode = "nor"; |
382bee57 | 74 | env_set("modeboot", "norboot"); |
b3de9249 JT |
75 | break; |
76 | case ZYNQ_BM_SD: | |
7712fb1f | 77 | mode = "mmc0"; |
382bee57 | 78 | env_set("modeboot", "sdboot"); |
b3de9249 JT |
79 | break; |
80 | case ZYNQ_BM_JTAG: | |
c352f1e1 | 81 | mode = "jtag pxe dhcp"; |
382bee57 | 82 | env_set("modeboot", "jtagboot"); |
b3de9249 JT |
83 | break; |
84 | default: | |
3c7b4c35 | 85 | mode = ""; |
382bee57 | 86 | env_set("modeboot", ""); |
b3de9249 JT |
87 | break; |
88 | } | |
89 | ||
3c7b4c35 SDPP |
90 | /* |
91 | * One terminating char + one byte for space between mode | |
92 | * and default boot_targets | |
93 | */ | |
94 | env_targets = env_get("boot_targets"); | |
95 | if (env_targets) | |
96 | env_targets_len = strlen(env_targets); | |
97 | ||
98 | new_targets = calloc(1, strlen(mode) + env_targets_len + 2); | |
99 | if (!new_targets) | |
100 | return -ENOMEM; | |
101 | ||
102 | sprintf(new_targets, "%s %s", mode, | |
103 | env_targets ? env_targets : ""); | |
104 | ||
105 | env_set("boot_targets", new_targets); | |
106 | ||
80fdef12 | 107 | return board_late_init_xilinx(); |
b3de9249 | 108 | } |
f22651cf | 109 | |
aa6e94de | 110 | #if !defined(CFG_SYS_SDRAM_BASE) && !defined(CFG_SYS_SDRAM_SIZE) |
76b00aca | 111 | int dram_init_banksize(void) |
361a8799 | 112 | { |
da3f003b | 113 | return fdtdec_setup_memory_banksize(); |
361a8799 | 114 | } |
8a5db0ab | 115 | |
361a8799 TR |
116 | int dram_init(void) |
117 | { | |
12308b12 | 118 | if (fdtdec_setup_mem_size_base() != 0) |
de9bf1b5 | 119 | return -EINVAL; |
64b67fb2 | 120 | |
361a8799 | 121 | zynq_ddrc_init(); |
64b67fb2 | 122 | |
361a8799 | 123 | return 0; |
758f29d0 | 124 | } |
758f29d0 MS |
125 | #else |
126 | int dram_init(void) | |
127 | { | |
aa6e94de TR |
128 | gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, |
129 | CFG_SYS_SDRAM_SIZE); | |
758f29d0 | 130 | |
148ba55c MS |
131 | zynq_ddrc_init(); |
132 | ||
f22651cf MS |
133 | return 0; |
134 | } | |
758f29d0 | 135 | #endif |
cd08513b ARS |
136 | |
137 | enum env_location env_get_location(enum env_operation op, int prio) | |
138 | { | |
139 | u32 bootmode = zynq_slcr_get_boot_mode() & ZYNQ_BM_MASK; | |
140 | ||
141 | if (prio) | |
142 | return ENVL_UNKNOWN; | |
143 | ||
144 | switch (bootmode) { | |
145 | case ZYNQ_BM_SD: | |
146 | if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT)) | |
147 | return ENVL_FAT; | |
148 | if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4)) | |
149 | return ENVL_EXT4; | |
50918d0d | 150 | return ENVL_NOWHERE; |
cd08513b ARS |
151 | case ZYNQ_BM_NAND: |
152 | if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND)) | |
153 | return ENVL_NAND; | |
154 | if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI)) | |
155 | return ENVL_UBI; | |
50918d0d | 156 | return ENVL_NOWHERE; |
cd08513b ARS |
157 | case ZYNQ_BM_NOR: |
158 | case ZYNQ_BM_QSPI: | |
159 | if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) | |
160 | return ENVL_SPI_FLASH; | |
50918d0d | 161 | return ENVL_NOWHERE; |
cd08513b ARS |
162 | case ZYNQ_BM_JTAG: |
163 | default: | |
164 | return ENVL_NOWHERE; | |
165 | } | |
166 | } | |
c67fecd2 MS |
167 | |
168 | #if defined(CONFIG_SET_DFU_ALT_INFO) | |
169 | ||
170 | #define DFU_ALT_BUF_LEN SZ_1K | |
171 | ||
172 | void set_dfu_alt_info(char *interface, char *devstr) | |
173 | { | |
174 | ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); | |
175 | ||
ce183fd7 | 176 | if (env_get("dfu_alt_info")) |
c67fecd2 MS |
177 | return; |
178 | ||
179 | memset(buf, 0, sizeof(buf)); | |
180 | ||
181 | switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { | |
182 | case ZYNQ_BM_SD: | |
183 | snprintf(buf, DFU_ALT_BUF_LEN, | |
88eaca26 | 184 | "mmc 0=boot.bin fat 0 1;" |
93020aa3 | 185 | "%s fat 0 1", CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); |
c67fecd2 | 186 | break; |
1cd876bd | 187 | #if defined(CONFIG_SPL_SPI_LOAD) |
c67fecd2 MS |
188 | case ZYNQ_BM_QSPI: |
189 | snprintf(buf, DFU_ALT_BUF_LEN, | |
190 | "sf 0:0=boot.bin raw 0 0x1500000;" | |
93020aa3 MS |
191 | "%s raw 0x%x 0x500000", |
192 | CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, | |
c67fecd2 MS |
193 | CONFIG_SYS_SPI_U_BOOT_OFFS); |
194 | break; | |
1cd876bd | 195 | #endif |
c67fecd2 MS |
196 | default: |
197 | return; | |
198 | } | |
199 | ||
200 | env_set("dfu_alt_info", buf); | |
201 | puts("DFU alt info setting: done\n"); | |
202 | } | |
203 | #endif |