[people/ms/u-boot.git] / board / xm250 / lowlevel_init.S

/*
 * Most of this taken from Redboot hal_platform_setup.h with cleanup
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>

DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE

/* wait for coprocessor write complete */
	.macro CPWAIT reg
	mrc	p15,0,\reg,c2,c0,0
	mov	\reg,\reg
	sub	pc,pc,#4
	.endm
/*
	.macro SET_LED val
	ldr	r6, =CRADLE_LED_CLR_REG
	ldr	r7, =0
	str	r7, [r6]
	ldr	r6, =CRADLE_LED_SET_REG
	ldr	r7, =\val
	str	r7, [r6]
	.endm
*/

.globl lowlevel_init
lowlevel_init:

	mov	r10, lr

	/* Set up GPIO pins first */

	ldr	r0,   =GPSR0
	ldr	r1,   =CONFIG_SYS_GPSR0_VAL
	str	r1,   [r0]

	ldr	r0,   =GPSR1
	ldr	r1,   =CONFIG_SYS_GPSR1_VAL
	str	r1,   [r0]

	ldr	r0,   =GPSR2
	ldr	r1,   =CONFIG_SYS_GPSR2_VAL
	str	r1,   [r0]

	ldr	r0,   =GPCR0
	ldr	r1,   =CONFIG_SYS_GPCR0_VAL
	str	r1,   [r0]

	ldr	r0,   =GPCR1
	ldr	r1,   =CONFIG_SYS_GPCR1_VAL
	str	r1,   [r0]

	ldr	r0,   =GPCR2
	ldr	r1,   =CONFIG_SYS_GPCR2_VAL
	str	r1,   [r0]

	ldr	r0,   =GRER0
	ldr	r1,   =CONFIG_SYS_GRER0_VAL
	str	r1,   [r0]

	ldr	r0,   =GRER1
	ldr	r1,   =CONFIG_SYS_GRER1_VAL
	str	r1,   [r0]

	ldr	r0,   =GRER2
	ldr	r1,   =CONFIG_SYS_GRER2_VAL
	str	r1,   [r0]

	ldr	r0,   =GFER0
	ldr	r1,   =CONFIG_SYS_GFER0_VAL
	str	r1,   [r0]

	ldr	r0,   =GFER1
	ldr	r1,   =CONFIG_SYS_GFER1_VAL
	str	r1,   [r0]

	ldr	r0,   =GFER2
	ldr	r1,   =CONFIG_SYS_GFER2_VAL
	str	r1,   [r0]

	ldr	r0,   =GPDR0
	ldr	r1,   =CONFIG_SYS_GPDR0_VAL
	str	r1,   [r0]

	ldr	r0,   =GPDR1
	ldr	r1,   =CONFIG_SYS_GPDR1_VAL
	str	r1,   [r0]

	ldr	r0,   =GPDR2
	ldr	r1,   =CONFIG_SYS_GPDR2_VAL
	str	r1,   [r0]

	ldr	r0,   =GAFR0_L
	ldr	r1,   =CONFIG_SYS_GAFR0_L_VAL
	str	r1,   [r0]

	ldr	r0,   =GAFR0_U
	ldr	r1,   =CONFIG_SYS_GAFR0_U_VAL
	str	r1,   [r0]

	ldr	r0,   =GAFR1_L
	ldr	r1,   =CONFIG_SYS_GAFR1_L_VAL
	str	r1,   [r0]

	ldr	r0,   =GAFR1_U
	ldr	r1,   =CONFIG_SYS_GAFR1_U_VAL
	str	r1,   [r0]

	ldr	r0,   =GAFR2_L
	ldr	r1,   =CONFIG_SYS_GAFR2_L_VAL
	str	r1,   [r0]

	ldr	r0,   =GAFR2_U
	ldr	r1,   =CONFIG_SYS_GAFR2_U_VAL
	str	r1,   [r0]

	/* enable GPIO pins */
	ldr	r0,   =PSSR
	ldr	r1,   =CONFIG_SYS_PSSR_VAL
	str	r1,   [r0]

	/* SET_LED 1 */

	ldr	r3, =MSC1		/* low - bank 2 Lubbock Registers / SRAM */
	ldr	r2, =CONFIG_SYS_MSC1_VAL	/* high - bank 3 Ethernet Controller */
	str	r2, [r3]		/* need to set MSC1 before trying to write to the HEX LEDs */
	ldr	r2, [r3]		/* need to read it back to make sure the value latches (see MSC section of manual) */


/*********************************************************************
 *  Initlialize Memory Controller
 *
 *  See PXA250 Operating System Developer's Guide
 *
 *  pause for 200 uSecs- allow internal clocks to settle
 *  *Note: only need this if hard reset... doing it anyway for now
 */

	@ Step 1
	@ ---- Wait 200 usec
	ldr	r3, =OSCR	@ reset the OS Timer Count to zero
	mov	r2, #0
	str	r2, [r3]
	ldr	r4, =0x300	@ really 0x2E1 is about 200usec, so 0x300 should be plenty
1:
	ldr	r2, [r3]
	cmp	r4, r2
	bgt	1b

	/* SET_LED 2 */

mem_init:
	@ get memory controller base address
	ldr	r1,  =MEMC_BASE


@****************************************************************************
@  Step 2
@

	@ Step 2a
	@ write msc0, read back to ensure data latches
	@
	ldr	r2,   =CONFIG_SYS_MSC0_VAL
	str	r2,   [r1, #MSC0_OFFSET]
	ldr	r2,   [r1, #MSC0_OFFSET]

	@ write msc1
	ldr	r2,  =CONFIG_SYS_MSC1_VAL
	str	r2,  [r1, #MSC1_OFFSET]
	ldr	r2,  [r1, #MSC1_OFFSET]

	@ write msc2
	ldr	r2,  =CONFIG_SYS_MSC2_VAL
	str	r2,  [r1, #MSC2_OFFSET]
	ldr	r2,  [r1, #MSC2_OFFSET]

	@ Step 2b
	@ write mecr
	ldr	r2,  =CONFIG_SYS_MECR_VAL
	str	r2,  [r1, #MECR_OFFSET]

	@ write mcmem0
	ldr	r2,  =CONFIG_SYS_MCMEM0_VAL
	str	r2,  [r1, #MCMEM0_OFFSET]

	@ write mcmem1
	ldr	r2,  =CONFIG_SYS_MCMEM1_VAL
	str	r2,  [r1, #MCMEM1_OFFSET]

	@ write mcatt0
	ldr	r2,  =CONFIG_SYS_MCATT0_VAL
	str	r2,  [r1, #MCATT0_OFFSET]

	@ write mcatt1
	ldr	r2,  =CONFIG_SYS_MCATT1_VAL
	str	r2,  [r1, #MCATT1_OFFSET]

	@ write mcio0
	ldr	r2,  =CONFIG_SYS_MCIO0_VAL
	str	r2,  [r1, #MCIO0_OFFSET]

	@ write mcio1
	ldr	r2,  =CONFIG_SYS_MCIO1_VAL
	str	r2,  [r1, #MCIO1_OFFSET]

	/*SET_LED 3 */

	@ Step 2c
	@ fly-by-dma is defeatured on this part
	@ write flycnfg
	@ldr	r2,  =CONFIG_SYS_FLYCNFG_VAL
	@str	r2,  [r1, #FLYCNFG_OFFSET]

/* FIXME Does this sequence really make sense */
#ifdef REDBOOT_WAY
	@ Step 2d
	@ get the mdrefr settings
	ldr	r3,  =CONFIG_SYS_MDREFR_VAL

	@ extract DRI field (we need a valid DRI field)
	@
	ldr	r2,  =0xFFF

	@ valid DRI field in r3
	@
	and	r3,  r3,  r2

	@ get the reset state of MDREFR
	@
	ldr	r4,  [r1, #MDREFR_OFFSET]

	@ clear the DRI field
	@
	bic	r4,  r4,  r2

	@ insert the valid DRI field loaded above
	@
	orr	r4,  r4,  r3

	@ write back mdrefr
	@
	str	r4,  [r1, #MDREFR_OFFSET]

	@ *Note: preserve the mdrefr value in r4 *

	/*SET_LED 4 */

@****************************************************************************
@  Step 3
@
@ NO SRAM

	mov   pc, r10


@****************************************************************************
@  Step 4
@

	@ Assumes previous mdrefr value in r4, if not then read current mdrefr

	@ clear the free-running clock bits
	@ (clear K0Free, K1Free, K2Free
	@
	bic	r4,  r4,  #(0x00800000 | 0x01000000 | 0x02000000)

	@ set K0RUN for CPLD clock
	@
	orr	r4,  r4, #0x00002000

	@ set K1RUN if bank 0 installed
	@
	orr	r4,  r4, #0x00010000

	@ write back mdrefr
	@
	str	r4,  [r1, #MDREFR_OFFSET]
	ldr	r4,  [r1, #MDREFR_OFFSET]

	@ deassert SLFRSH
	@
	bic	r4,  r4,  #0x00400000

	@ write back mdrefr
	@
	str	r4,  [r1, #MDREFR_OFFSET]

	@ assert E1PIN
	@
	orr	r4,  r4,  #0x00008000

	@ write back mdrefr
	@
	str	r4,  [r1, #MDREFR_OFFSET]
	ldr	r4,  [r1, #MDREFR_OFFSET]
	nop
	nop
#else
	@ Step 2d
	@ get the mdrefr settings
	ldr	r4,  =CONFIG_SYS_MDREFR_VAL

	@ write back mdrefr
	@
	str	r4,  [r1, #MDREFR_OFFSET]

	@  Step 4

	@ set K0RUN for FLASH clock
	@
	orr	r4,  r4, #0x00002000

	@ set K1RUN for bank DRAM 0
	@
	orr	r4,  r4, #0x00010000

	@ set K2RUN for bank PLD
	@
	orr	r4,  r4, #0x00040000

	@ write back mdrefr
	@
	str	r4,  [r1, #MDREFR_OFFSET]
	ldr	r4,  [r1, #MDREFR_OFFSET]

	@ deassert SLFRSH
	@
	bic	r4,  r4,  #0x00400000

	@ write back mdrefr
	@
	str	r4,  [r1, #MDREFR_OFFSET]

	@ assert E1PIN
	@
	orr	r4,  r4,  #0x00008000

	@ write back mdrefr
	@
	str	r4,  [r1, #MDREFR_OFFSET]
	ldr	r4,  [r1, #MDREFR_OFFSET]
	nop
	nop
#endif

	@ Step 4d
	@ fetch platform value of mdcnfg
	@
	ldr	r2,  =CONFIG_SYS_MDCNFG_VAL

	@ disable all sdram banks
	@
	bic	r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
	bic	r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)

	@ program banks 0/1 for bus width
	@
	bic	r2,  r2,  #MDCNFG_DWID0		@0=32-bit

	@ write initial value of mdcnfg, w/o enabling sdram banks
	@
	str	r2,  [r1, #MDCNFG_OFFSET]

	@ Step 4e
	@ pause for 200 uSecs
	@
	ldr	r3, =OSCR	@ reset the OS Timer Count to zero
	mov	r2, #0
	str	r2, [r3]
	ldr	r4, =0x300	@ really 0x2E1 is about 200usec, so 0x300 should be plenty
1:
	ldr	r2, [r3]
	cmp	r4, r2
	bgt	1b

	/*SET_LED 5 */

	/* Why is this here??? */
	mov	r0, #0x78		@turn everything off
	mcr	p15, 0, r0, c1, c0, 0	@(caches off, MMU off, etc.)

	@ Step 4f
	@ Access memory *not yet enabled* for CBR refresh cycles (8)
	@ - CBR is generated for all banks

	ldr	r2, =CONFIG_SYS_DRAM_BASE
	str	r2, [r2]
	str	r2, [r2]
	str	r2, [r2]
	str	r2, [r2]
	str	r2, [r2]
	str	r2, [r2]
	str	r2, [r2]
	str	r2, [r2]

	@ Step 4g
	@get memory controller base address
	@
	ldr	r1,  =MEMC_BASE

	@fetch current mdcnfg value
	@
	ldr	r3,  [r1, #MDCNFG_OFFSET]

	@enable sdram bank 0 if installed (must do for any populated bank)
	@
	orr	r3,  r3,  #MDCNFG_DE0

	@write back mdcnfg, enabling the sdram bank(s)
	@
	str	r3,  [r1, #MDCNFG_OFFSET]

	@ Step 4h
	@ write mdmrs
	@
	ldr	r2,  =CONFIG_SYS_MDMRS_VAL
	str	r2,  [r1, #MDMRS_OFFSET]

	@ Done Memory Init

	/*SET_LED 6 */

	@********************************************************************
	@ Disable (mask) all interrupts at the interrupt controller
	@

	@ clear the interrupt level register (use IRQ, not FIQ)
	@
	mov	r1, #0
	ldr	r2,  =ICLR
	str	r1,  [r2]

	@ Set interrupt mask register
	@
	ldr	r1,  =CONFIG_SYS_ICMR_VAL
	ldr	r2,  =ICMR
	str	r1,  [r2]

	@ ********************************************************************
	@ Disable the peripheral clocks, and set the core clock
	@

	@ Turn Off ALL on-chip peripheral clocks for re-configuration
	@
	ldr	r1,  =CKEN
	mov	r2,  #0
	str	r2,  [r1]

	@ set core clocks
	@
	ldr	r2,  =CONFIG_SYS_CCCR_VAL
	ldr	r1,  =CCCR
	str	r2,  [r1]

#ifdef ENABLE32KHZ
	@ enable the 32Khz oscillator for RTC and PowerManager
	@
	ldr	r1,  =OSCC
	mov	r2,  #OSCC_OON
	str	r2,  [r1]

	@ NOTE:	 spin here until OSCC.OOK get set,
	@	 meaning the PLL has settled.
	@
60:
	ldr	r2, [r1]
	ands	r2, r2, #1
	beq	60b
#endif

	@ Turn on needed clocks
	@
	ldr	r1,  =CKEN
	ldr	r2,  =CONFIG_SYS_CKEN_VAL
	str	r2,  [r1]

	/*SET_LED 7 */

/* Is this needed???? */
#define NODEBUG
#ifdef NODEBUG
	/*Disable software and data breakpoints */
	mov	r0,#0
	mcr	p15,0,r0,c14,c8,0	/* ibcr0 */
	mcr	p15,0,r0,c14,c9,0	/* ibcr1 */
	mcr	p15,0,r0,c14,c4,0	/* dbcon */

	/*Enable all debug functionality */
	mov	r0,#0x80000000
	mcr	p14,0,r0,c10,c0,0	/* dcsr */

#endif

	/*SET_LED 8 */

	mov	pc, r10

@ End lowlevel_init
Commit	Line	Data
efa329cb WD	1	/*
	2	* Most of this taken from Redboot hal_platform_setup.h with cleanup
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <config.h>
	24	#include <version.h>
	25	#include <asm/arch/pxa-regs.h>
	26
6d0f6bcf	27	DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
efa329cb WD	28
	29	/* wait for coprocessor write complete */
	30	.macro CPWAIT reg
	31	mrc p15,0,\reg,c2,c0,0
	32	mov \reg,\reg
	33	sub pc,pc,#4
	34	.endm
	35	/*
	36	.macro SET_LED val
	37	ldr r6, =CRADLE_LED_CLR_REG
	38	ldr r7, =0
	39	str r7, [r6]
	40	ldr r6, =CRADLE_LED_SET_REG
	41	ldr r7, =\val
	42	str r7, [r6]
	43	.endm
	44	*/
	45
400558b5 WD	46	.globl lowlevel_init
400558b5 WD	47	lowlevel_init:
efa329cb WD	48
	49	mov r10, lr
	50
	51	/* Set up GPIO pins first */
	52
	53	ldr r0, =GPSR0
6d0f6bcf	54	ldr r1, =CONFIG_SYS_GPSR0_VAL
efa329cb WD	55	str r1, [r0]
	56
	57	ldr r0, =GPSR1
6d0f6bcf	58	ldr r1, =CONFIG_SYS_GPSR1_VAL
efa329cb WD	59	str r1, [r0]
	60
	61	ldr r0, =GPSR2
6d0f6bcf	62	ldr r1, =CONFIG_SYS_GPSR2_VAL
efa329cb WD	63	str r1, [r0]
	64
	65	ldr r0, =GPCR0
6d0f6bcf	66	ldr r1, =CONFIG_SYS_GPCR0_VAL
efa329cb WD	67	str r1, [r0]
	68
	69	ldr r0, =GPCR1
6d0f6bcf	70	ldr r1, =CONFIG_SYS_GPCR1_VAL
efa329cb WD	71	str r1, [r0]
	72
	73	ldr r0, =GPCR2
6d0f6bcf	74	ldr r1, =CONFIG_SYS_GPCR2_VAL
efa329cb WD	75	str r1, [r0]
	76
	77	ldr r0, =GRER0
6d0f6bcf	78	ldr r1, =CONFIG_SYS_GRER0_VAL
efa329cb WD	79	str r1, [r0]
	80
	81	ldr r0, =GRER1
6d0f6bcf	82	ldr r1, =CONFIG_SYS_GRER1_VAL
efa329cb WD	83	str r1, [r0]
	84
	85	ldr r0, =GRER2
6d0f6bcf	86	ldr r1, =CONFIG_SYS_GRER2_VAL
efa329cb WD	87	str r1, [r0]
	88
	89	ldr r0, =GFER0
6d0f6bcf	90	ldr r1, =CONFIG_SYS_GFER0_VAL
efa329cb WD	91	str r1, [r0]
	92
	93	ldr r0, =GFER1
6d0f6bcf	94	ldr r1, =CONFIG_SYS_GFER1_VAL
efa329cb WD	95	str r1, [r0]
	96
	97	ldr r0, =GFER2
6d0f6bcf	98	ldr r1, =CONFIG_SYS_GFER2_VAL
efa329cb WD	99	str r1, [r0]
	100
	101	ldr r0, =GPDR0
6d0f6bcf	102	ldr r1, =CONFIG_SYS_GPDR0_VAL
efa329cb WD	103	str r1, [r0]
	104
	105	ldr r0, =GPDR1
6d0f6bcf	106	ldr r1, =CONFIG_SYS_GPDR1_VAL
efa329cb WD	107	str r1, [r0]
	108
	109	ldr r0, =GPDR2
6d0f6bcf	110	ldr r1, =CONFIG_SYS_GPDR2_VAL
efa329cb WD	111	str r1, [r0]
	112
	113	ldr r0, =GAFR0_L
6d0f6bcf	114	ldr r1, =CONFIG_SYS_GAFR0_L_VAL
efa329cb WD	115	str r1, [r0]
	116
	117	ldr r0, =GAFR0_U
6d0f6bcf	118	ldr r1, =CONFIG_SYS_GAFR0_U_VAL
efa329cb WD	119	str r1, [r0]
	120
	121	ldr r0, =GAFR1_L
6d0f6bcf	122	ldr r1, =CONFIG_SYS_GAFR1_L_VAL
efa329cb WD	123	str r1, [r0]
	124
	125	ldr r0, =GAFR1_U
6d0f6bcf	126	ldr r1, =CONFIG_SYS_GAFR1_U_VAL
efa329cb WD	127	str r1, [r0]
	128
	129	ldr r0, =GAFR2_L
6d0f6bcf	130	ldr r1, =CONFIG_SYS_GAFR2_L_VAL
efa329cb WD	131	str r1, [r0]
	132
	133	ldr r0, =GAFR2_U
6d0f6bcf	134	ldr r1, =CONFIG_SYS_GAFR2_U_VAL
efa329cb WD	135	str r1, [r0]
	136
	137	/* enable GPIO pins */
	138	ldr r0, =PSSR
6d0f6bcf	139	ldr r1, =CONFIG_SYS_PSSR_VAL
efa329cb WD	140	str r1, [r0]
	141
	142	/* SET_LED 1 */
	143
	144	ldr r3, =MSC1 /* low - bank 2 Lubbock Registers / SRAM */
6d0f6bcf	145	ldr r2, =CONFIG_SYS_MSC1_VAL /* high - bank 3 Ethernet Controller */
efa329cb WD	146	str r2, [r3] /* need to set MSC1 before trying to write to the HEX LEDs */
	147	ldr r2, [r3] /* need to read it back to make sure the value latches (see MSC section of manual) */
	148
	149
	150	/*********************************************************************
	151	* Initlialize Memory Controller
	152	*
	153	* See PXA250 Operating System Developer's Guide
	154	*
	155	* pause for 200 uSecs- allow internal clocks to settle
	156	* *Note: only need this if hard reset... doing it anyway for now
	157	*/
	158
	159	@ Step 1
	160	@ ---- Wait 200 usec
	161	ldr r3, =OSCR @ reset the OS Timer Count to zero
	162	mov r2, #0
	163	str r2, [r3]
	164	ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
	165	1:
	166	ldr r2, [r3]
	167	cmp r4, r2
	168	bgt 1b
	169
	170	/* SET_LED 2 */
	171
	172	mem_init:
	173	@ get memory controller base address
	174	ldr r1, =MEMC_BASE
	175
	176
	177	@****************************************************************************
	178	@ Step 2
	179	@
	180
	181	@ Step 2a
	182	@ write msc0, read back to ensure data latches
	183	@
6d0f6bcf	184	ldr r2, =CONFIG_SYS_MSC0_VAL
efa329cb WD	185	str r2, [r1, #MSC0_OFFSET]
	186	ldr r2, [r1, #MSC0_OFFSET]
	187
	188	@ write msc1
6d0f6bcf	189	ldr r2, =CONFIG_SYS_MSC1_VAL
efa329cb WD	190	str r2, [r1, #MSC1_OFFSET]
	191	ldr r2, [r1, #MSC1_OFFSET]
	192
	193	@ write msc2
6d0f6bcf	194	ldr r2, =CONFIG_SYS_MSC2_VAL
efa329cb WD	195	str r2, [r1, #MSC2_OFFSET]
	196	ldr r2, [r1, #MSC2_OFFSET]
	197
	198	@ Step 2b
	199	@ write mecr
6d0f6bcf	200	ldr r2, =CONFIG_SYS_MECR_VAL
efa329cb WD	201	str r2, [r1, #MECR_OFFSET]
	202
	203	@ write mcmem0
6d0f6bcf	204	ldr r2, =CONFIG_SYS_MCMEM0_VAL
efa329cb WD	205	str r2, [r1, #MCMEM0_OFFSET]
	206
	207	@ write mcmem1
6d0f6bcf	208	ldr r2, =CONFIG_SYS_MCMEM1_VAL
efa329cb WD	209	str r2, [r1, #MCMEM1_OFFSET]
	210
	211	@ write mcatt0
6d0f6bcf	212	ldr r2, =CONFIG_SYS_MCATT0_VAL
efa329cb WD	213	str r2, [r1, #MCATT0_OFFSET]
	214
	215	@ write mcatt1
6d0f6bcf	216	ldr r2, =CONFIG_SYS_MCATT1_VAL
efa329cb WD	217	str r2, [r1, #MCATT1_OFFSET]
	218
	219	@ write mcio0
6d0f6bcf	220	ldr r2, =CONFIG_SYS_MCIO0_VAL
efa329cb WD	221	str r2, [r1, #MCIO0_OFFSET]
	222
	223	@ write mcio1
6d0f6bcf	224	ldr r2, =CONFIG_SYS_MCIO1_VAL
efa329cb WD	225	str r2, [r1, #MCIO1_OFFSET]
	226
	227	/SET_LED 3 /
	228
	229	@ Step 2c
	230	@ fly-by-dma is defeatured on this part
	231	@ write flycnfg
6d0f6bcf	232	@ldr r2, =CONFIG_SYS_FLYCNFG_VAL
efa329cb WD	233	@str r2, [r1, #FLYCNFG_OFFSET]
	234
	235	/* FIXME Does this sequence really make sense */
	236	#ifdef REDBOOT_WAY
	237	@ Step 2d
	238	@ get the mdrefr settings
6d0f6bcf	239	ldr r3, =CONFIG_SYS_MDREFR_VAL
efa329cb WD	240
	241	@ extract DRI field (we need a valid DRI field)
	242	@
	243	ldr r2, =0xFFF
	244
	245	@ valid DRI field in r3
	246	@
	247	and r3, r3, r2
	248
	249	@ get the reset state of MDREFR
	250	@
	251	ldr r4, [r1, #MDREFR_OFFSET]
	252
	253	@ clear the DRI field
	254	@
	255	bic r4, r4, r2
	256
	257	@ insert the valid DRI field loaded above
	258	@
	259	orr r4, r4, r3
	260
	261	@ write back mdrefr
	262	@
	263	str r4, [r1, #MDREFR_OFFSET]
	264
	265	@ Note: preserve the mdrefr value in r4
	266
	267	/SET_LED 4 /
	268
	269	@****************************************************************************
	270	@ Step 3
	271	@
	272	@ NO SRAM
	273
	274	mov pc, r10
	275
	276
	277	@****************************************************************************
	278	@ Step 4
	279	@
	280
	281	@ Assumes previous mdrefr value in r4, if not then read current mdrefr
	282
	283	@ clear the free-running clock bits
	284	@ (clear K0Free, K1Free, K2Free
	285	@
	286	bic r4, r4, #(0x00800000 \| 0x01000000 \| 0x02000000)
	287
	288	@ set K0RUN for CPLD clock
	289	@
	290	orr r4, r4, #0x00002000
	291
	292	@ set K1RUN if bank 0 installed
	293	@
	294	orr r4, r4, #0x00010000
	295
	296	@ write back mdrefr
	297	@
	298	str r4, [r1, #MDREFR_OFFSET]
	299	ldr r4, [r1, #MDREFR_OFFSET]
	300
	301	@ deassert SLFRSH
	302	@
	303	bic r4, r4, #0x00400000
304
305	@ write back mdrefr
306	@
307	str r4, [r1, #MDREFR_OFFSET]
308
309	@ assert E1PIN
310	@
311	orr r4, r4, #0x00008000
312
313	@ write back mdrefr
314	@
315	str r4, [r1, #MDREFR_OFFSET]
316	ldr r4, [r1, #MDREFR_OFFSET]
317	nop
318	nop
319	#else
320	@ Step 2d
321	@ get the mdrefr settings
6d0f6bcf	322	ldr r4, =CONFIG_SYS_MDREFR_VAL
efa329cb WD	323
	324	@ write back mdrefr
	325	@
	326	str r4, [r1, #MDREFR_OFFSET]
	327
	328	@ Step 4
	329
	330	@ set K0RUN for FLASH clock
	331	@
	332	orr r4, r4, #0x00002000
	333
	334	@ set K1RUN for bank DRAM 0
	335	@
	336	orr r4, r4, #0x00010000
	337
	338	@ set K2RUN for bank PLD
	339	@
	340	orr r4, r4, #0x00040000
	341
	342	@ write back mdrefr
	343	@
	344	str r4, [r1, #MDREFR_OFFSET]
	345	ldr r4, [r1, #MDREFR_OFFSET]
	346
	347	@ deassert SLFRSH
	348	@
	349	bic r4, r4, #0x00400000
	350
	351	@ write back mdrefr
	352	@
	353	str r4, [r1, #MDREFR_OFFSET]
	354
	355	@ assert E1PIN
	356	@
	357	orr r4, r4, #0x00008000
	358
	359	@ write back mdrefr
	360	@
	361	str r4, [r1, #MDREFR_OFFSET]
	362	ldr r4, [r1, #MDREFR_OFFSET]
	363	nop
	364	nop
	365	#endif
	366
	367	@ Step 4d
	368	@ fetch platform value of mdcnfg
	369	@
6d0f6bcf	370	ldr r2, =CONFIG_SYS_MDCNFG_VAL
efa329cb WD	371
	372	@ disable all sdram banks
	373	@
	374	bic r2, r2, #(MDCNFG_DE0 \| MDCNFG_DE1)
	375	bic r2, r2, #(MDCNFG_DE2 \| MDCNFG_DE3)
	376
	377	@ program banks 0/1 for bus width
	378	@
	379	bic r2, r2, #MDCNFG_DWID0 @0=32-bit
	380
	381	@ write initial value of mdcnfg, w/o enabling sdram banks
	382	@
	383	str r2, [r1, #MDCNFG_OFFSET]
	384
	385	@ Step 4e
	386	@ pause for 200 uSecs
	387	@
	388	ldr r3, =OSCR @ reset the OS Timer Count to zero
	389	mov r2, #0
	390	str r2, [r3]
	391	ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
	392	1:
	393	ldr r2, [r3]
	394	cmp r4, r2
	395	bgt 1b
	396
	397	/SET_LED 5 /
	398
	399	/* Why is this here??? */
	400	mov r0, #0x78 @turn everything off
	401	mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.)
	402
	403	@ Step 4f
	404	@ Access memory not yet enabled for CBR refresh cycles (8)
	405	@ - CBR is generated for all banks
	406
6d0f6bcf	407	ldr r2, =CONFIG_SYS_DRAM_BASE
efa329cb WD	408	str r2, [r2]
	409	str r2, [r2]
	410	str r2, [r2]
	411	str r2, [r2]
	412	str r2, [r2]
	413	str r2, [r2]
	414	str r2, [r2]
	415	str r2, [r2]
	416
	417	@ Step 4g
	418	@get memory controller base address
	419	@
	420	ldr r1, =MEMC_BASE
	421
	422	@fetch current mdcnfg value
	423	@
	424	ldr r3, [r1, #MDCNFG_OFFSET]
	425
	426	@enable sdram bank 0 if installed (must do for any populated bank)
	427	@
	428	orr r3, r3, #MDCNFG_DE0
	429
	430	@write back mdcnfg, enabling the sdram bank(s)
	431	@
	432	str r3, [r1, #MDCNFG_OFFSET]
	433
	434	@ Step 4h
	435	@ write mdmrs
	436	@
6d0f6bcf	437	ldr r2, =CONFIG_SYS_MDMRS_VAL
efa329cb WD	438	str r2, [r1, #MDMRS_OFFSET]
	439
	440	@ Done Memory Init
	441
	442	/SET_LED 6 /
	443
	444	@********************************************************************
	445	@ Disable (mask) all interrupts at the interrupt controller
	446	@
	447
	448	@ clear the interrupt level register (use IRQ, not FIQ)
	449	@
	450	mov r1, #0
	451	ldr r2, =ICLR
	452	str r1, [r2]
	453
	454	@ Set interrupt mask register
	455	@
6d0f6bcf	456	ldr r1, =CONFIG_SYS_ICMR_VAL
efa329cb WD	457	ldr r2, =ICMR
	458	str r1, [r2]
	459
	460	@ ********************************************************************
	461	@ Disable the peripheral clocks, and set the core clock
	462	@
	463
	464	@ Turn Off ALL on-chip peripheral clocks for re-configuration
	465	@
	466	ldr r1, =CKEN
	467	mov r2, #0
	468	str r2, [r1]
	469
	470	@ set core clocks
	471	@
6d0f6bcf	472	ldr r2, =CONFIG_SYS_CCCR_VAL
efa329cb WD	473	ldr r1, =CCCR
	474	str r2, [r1]
	475
	476	#ifdef ENABLE32KHZ
	477	@ enable the 32Khz oscillator for RTC and PowerManager
	478	@
	479	ldr r1, =OSCC
	480	mov r2, #OSCC_OON
	481	str r2, [r1]
	482
	483	@ NOTE: spin here until OSCC.OOK get set,
	484	@ meaning the PLL has settled.
	485	@
	486	60:
	487	ldr r2, [r1]
	488	ands r2, r2, #1
	489	beq 60b
	490	#endif
	491
	492	@ Turn on needed clocks
	493	@
	494	ldr r1, =CKEN
6d0f6bcf	495	ldr r2, =CONFIG_SYS_CKEN_VAL
efa329cb WD	496	str r2, [r1]
	497
	498	/SET_LED 7 /
	499
	500	/* Is this needed???? */
	501	#define NODEBUG
	502	#ifdef NODEBUG
	503	/Disable software and data breakpoints /
	504	mov r0,#0
	505	mcr p15,0,r0,c14,c8,0 /* ibcr0 */
	506	mcr p15,0,r0,c14,c9,0 /* ibcr1 */
	507	mcr p15,0,r0,c14,c4,0 /* dbcon */
	508
	509	/Enable all debug functionality /
	510	mov r0,#0x80000000
	511	mcr p14,0,r0,c10,c0,0 /* dcsr */
	512
	513	#endif
	514
	515	/SET_LED 8 /
	516
	517	mov pc, r10
	518
400558b5	519	@ End lowlevel_init