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CommitLineData
1938f4a5
SG
1/*
2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2002-2006
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * (C) Copyright 2002
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Marius Groeger <mgroeger@sysgo.de>
9 *
1a459660 10 * SPDX-License-Identifier: GPL-2.0+
1938f4a5
SG
11 */
12
13#include <common.h>
24b852a7 14#include <console.h>
1938f4a5 15#include <environment.h>
ab7cd627 16#include <dm.h>
1938f4a5 17#include <fdtdec.h>
f828bf25 18#include <fs.h>
e4fef6cf 19#include <i2c.h>
1938f4a5 20#include <initcall.h>
96d4b75c 21#include <init_helpers.h>
fb5cf7f1 22#include <malloc.h>
0eb25b61 23#include <mapmem.h>
a733b06b 24#include <os.h>
1938f4a5 25#include <post.h>
e47b2d67 26#include <relocate.h>
e4fef6cf 27#include <spi.h>
c5d4001a 28#include <status_led.h>
1057e6cf 29#include <timer.h>
71c52dba 30#include <trace.h>
5a541945 31#include <video.h>
e4fef6cf 32#include <watchdog.h>
b885d02e
SG
33#ifdef CONFIG_MACH_TYPE
34#include <asm/mach-types.h>
35#endif
1fbf97dc
SG
36#if defined(CONFIG_MP) && defined(CONFIG_PPC)
37#include <asm/mp.h>
38#endif
1938f4a5
SG
39#include <asm/io.h>
40#include <asm/sections.h>
ab7cd627 41#include <dm/root.h>
056285fd 42#include <linux/errno.h>
1938f4a5
SG
43
44/*
45 * Pointer to initial global data area
46 *
47 * Here we initialize it if needed.
48 */
49#ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
50#undef XTRN_DECLARE_GLOBAL_DATA_PTR
51#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
52DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR);
53#else
54DECLARE_GLOBAL_DATA_PTR;
55#endif
56
57/*
4c509343 58 * TODO(sjg@chromium.org): IMO this code should be
1938f4a5
SG
59 * refactored to a single function, something like:
60 *
61 * void led_set_state(enum led_colour_t colour, int on);
62 */
63/************************************************************************
64 * Coloured LED functionality
65 ************************************************************************
66 * May be supplied by boards if desired
67 */
c5d4001a
JH
68__weak void coloured_LED_init(void) {}
69__weak void red_led_on(void) {}
70__weak void red_led_off(void) {}
71__weak void green_led_on(void) {}
72__weak void green_led_off(void) {}
73__weak void yellow_led_on(void) {}
74__weak void yellow_led_off(void) {}
75__weak void blue_led_on(void) {}
76__weak void blue_led_off(void) {}
1938f4a5
SG
77
78/*
79 * Why is gd allocated a register? Prior to reloc it might be better to
80 * just pass it around to each function in this file?
81 *
82 * After reloc one could argue that it is hardly used and doesn't need
83 * to be in a register. Or if it is it should perhaps hold pointers to all
84 * global data for all modules, so that post-reloc we can avoid the massive
85 * literal pool we get on ARM. Or perhaps just encourage each module to use
86 * a structure...
87 */
88
d54d7eb9 89#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
e4fef6cf
SG
90static int init_func_watchdog_init(void)
91{
ea3310e8
TR
92# if defined(CONFIG_HW_WATCHDOG) && \
93 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
14a380a8 94 defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \
46d7a3b3 95 defined(CONFIG_DESIGNWARE_WATCHDOG) || \
14a380a8 96 defined(CONFIG_IMX_WATCHDOG))
d54d7eb9 97 hw_watchdog_init();
e4fef6cf 98 puts(" Watchdog enabled\n");
ba169d98 99# endif
e4fef6cf
SG
100 WATCHDOG_RESET();
101
102 return 0;
103}
104
105int init_func_watchdog_reset(void)
106{
107 WATCHDOG_RESET();
108
109 return 0;
110}
111#endif /* CONFIG_WATCHDOG */
112
dd2a6cd0 113__weak void board_add_ram_info(int use_default)
e4fef6cf
SG
114{
115 /* please define platform specific board_add_ram_info() */
116}
117
1938f4a5
SG
118static int init_baud_rate(void)
119{
bfebc8c9 120 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
1938f4a5
SG
121 return 0;
122}
123
124static int display_text_info(void)
125{
9b217498 126#if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
9fdee7d7 127 ulong bss_start, bss_end, text_base;
1938f4a5 128
632efa74
SG
129 bss_start = (ulong)&__bss_start;
130 bss_end = (ulong)&__bss_end;
b60eff31 131
d54d7eb9 132#ifdef CONFIG_SYS_TEXT_BASE
9fdee7d7 133 text_base = CONFIG_SYS_TEXT_BASE;
d54d7eb9 134#else
9fdee7d7 135 text_base = CONFIG_SYS_MONITOR_BASE;
d54d7eb9 136#endif
9fdee7d7
DS
137
138 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
139 text_base, bss_start, bss_end);
a733b06b 140#endif
1938f4a5 141
1938f4a5
SG
142 return 0;
143}
144
145static int announce_dram_init(void)
146{
147 puts("DRAM: ");
148 return 0;
149}
150
151static int show_dram_config(void)
152{
fa39ffe5 153 unsigned long long size;
1938f4a5
SG
154
155#ifdef CONFIG_NR_DRAM_BANKS
156 int i;
157
158 debug("\nRAM Configuration:\n");
159 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
160 size += gd->bd->bi_dram[i].size;
715f599f
BM
161 debug("Bank #%d: %llx ", i,
162 (unsigned long long)(gd->bd->bi_dram[i].start));
1938f4a5
SG
163#ifdef DEBUG
164 print_size(gd->bd->bi_dram[i].size, "\n");
165#endif
166 }
167 debug("\nDRAM: ");
168#else
169 size = gd->ram_size;
170#endif
171
e4fef6cf
SG
172 print_size(size, "");
173 board_add_ram_info(0);
174 putc('\n');
1938f4a5
SG
175
176 return 0;
177}
178
76b00aca 179__weak int dram_init_banksize(void)
1938f4a5
SG
180{
181#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
182 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
183 gd->bd->bi_dram[0].size = get_effective_memsize();
184#endif
76b00aca
SG
185
186 return 0;
1938f4a5
SG
187}
188
69153988 189#if defined(CONFIG_SYS_I2C)
e4fef6cf
SG
190static int init_func_i2c(void)
191{
192 puts("I2C: ");
815a76f2 193#ifdef CONFIG_SYS_I2C
194 i2c_init_all();
195#else
e4fef6cf 196 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
815a76f2 197#endif
e4fef6cf
SG
198 puts("ready\n");
199 return 0;
200}
201#endif
202
203#if defined(CONFIG_HARD_SPI)
204static int init_func_spi(void)
205{
206 puts("SPI: ");
207 spi_init();
208 puts("ready\n");
209 return 0;
210}
211#endif
212
1938f4a5
SG
213static int setup_mon_len(void)
214{
e945f6dc 215#if defined(__ARM__) || defined(__MICROBLAZE__)
b60eff31 216 gd->mon_len = (ulong)&__bss_end - (ulong)_start;
9b217498 217#elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
a733b06b 218 gd->mon_len = (ulong)&_end - (ulong)_init;
ea3310e8 219#elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
d54d7eb9 220 gd->mon_len = CONFIG_SYS_MONITOR_LEN;
e2099d78 221#elif defined(CONFIG_NDS32) || defined(CONFIG_SH)
2e88bb28 222 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
b0b35953 223#elif defined(CONFIG_SYS_MONITOR_BASE)
e4fef6cf
SG
224 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
225 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
632efa74 226#endif
1938f4a5
SG
227 return 0;
228}
229
230__weak int arch_cpu_init(void)
231{
232 return 0;
233}
234
8ebf5069
PB
235__weak int mach_cpu_init(void)
236{
237 return 0;
238}
239
1938f4a5
SG
240/* Get the top of usable RAM */
241__weak ulong board_get_usable_ram_top(ulong total_size)
242{
1e4d11a5
SW
243#ifdef CONFIG_SYS_SDRAM_BASE
244 /*
4c509343 245 * Detect whether we have so much RAM that it goes past the end of our
1e4d11a5
SW
246 * 32-bit address space. If so, clip the usable RAM so it doesn't.
247 */
248 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
249 /*
250 * Will wrap back to top of 32-bit space when reservations
251 * are made.
252 */
253 return 0;
254#endif
1938f4a5
SG
255 return gd->ram_top;
256}
257
258static int setup_dest_addr(void)
259{
260 debug("Monitor len: %08lX\n", gd->mon_len);
261 /*
262 * Ram is setup, size stored in gd !!
263 */
264 debug("Ram size: %08lX\n", (ulong)gd->ram_size);
36cc0de0 265#if defined(CONFIG_SYS_MEM_TOP_HIDE)
1938f4a5
SG
266 /*
267 * Subtract specified amount of memory to hide so that it won't
268 * get "touched" at all by U-Boot. By fixing up gd->ram_size
269 * the Linux kernel should now get passed the now "corrected"
36cc0de0
YS
270 * memory size and won't touch it either. This should work
271 * for arch/ppc and arch/powerpc. Only Linux board ports in
272 * arch/powerpc with bootwrapper support, that recalculate the
273 * memory size from the SDRAM controller setup will have to
274 * get fixed.
1938f4a5 275 */
36cc0de0
YS
276 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
277#endif
1938f4a5
SG
278#ifdef CONFIG_SYS_SDRAM_BASE
279 gd->ram_top = CONFIG_SYS_SDRAM_BASE;
280#endif
e4fef6cf 281 gd->ram_top += get_effective_memsize();
1938f4a5 282 gd->ram_top = board_get_usable_ram_top(gd->mon_len);
a0ba279a 283 gd->relocaddr = gd->ram_top;
1938f4a5 284 debug("Ram top: %08lX\n", (ulong)gd->ram_top);
ec3b4820 285#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
e4fef6cf
SG
286 /*
287 * We need to make sure the location we intend to put secondary core
288 * boot code is reserved and not used by any part of u-boot
289 */
a0ba279a
MY
290 if (gd->relocaddr > determine_mp_bootpg(NULL)) {
291 gd->relocaddr = determine_mp_bootpg(NULL);
292 debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
e4fef6cf
SG
293 }
294#endif
1938f4a5
SG
295 return 0;
296}
297
1938f4a5
SG
298#ifdef CONFIG_PRAM
299/* reserve protected RAM */
300static int reserve_pram(void)
301{
302 ulong reg;
303
bfebc8c9 304 reg = env_get_ulong("pram", 10, CONFIG_PRAM);
a0ba279a 305 gd->relocaddr -= (reg << 10); /* size is in kB */
1938f4a5 306 debug("Reserving %ldk for protected RAM at %08lx\n", reg,
a0ba279a 307 gd->relocaddr);
1938f4a5
SG
308 return 0;
309}
310#endif /* CONFIG_PRAM */
311
312/* Round memory pointer down to next 4 kB limit */
313static int reserve_round_4k(void)
314{
a0ba279a 315 gd->relocaddr &= ~(4096 - 1);
1938f4a5
SG
316 return 0;
317}
318
80d4bcd3 319#ifdef CONFIG_ARM
60873f73 320__weak int reserve_mmu(void)
1938f4a5 321{
80d4bcd3 322#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
1938f4a5 323 /* reserve TLB table */
cce6be7f 324 gd->arch.tlb_size = PGTABLE_SIZE;
a0ba279a 325 gd->relocaddr -= gd->arch.tlb_size;
1938f4a5
SG
326
327 /* round down to next 64 kB limit */
a0ba279a 328 gd->relocaddr &= ~(0x10000 - 1);
1938f4a5 329
a0ba279a 330 gd->arch.tlb_addr = gd->relocaddr;
1938f4a5
SG
331 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
332 gd->arch.tlb_addr + gd->arch.tlb_size);
50e93b95
YS
333
334#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
335 /*
336 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
337 * with location within secure ram.
338 */
339 gd->arch.tlb_allocated = gd->arch.tlb_addr;
80d4bcd3 340#endif
50e93b95
YS
341#endif
342
1938f4a5
SG
343 return 0;
344}
345#endif
346
5a541945
SG
347static int reserve_video(void)
348{
0f079eb5 349#ifdef CONFIG_DM_VIDEO
5a541945
SG
350 ulong addr;
351 int ret;
352
353 addr = gd->relocaddr;
354 ret = video_reserve(&addr);
355 if (ret)
356 return ret;
357 gd->relocaddr = addr;
0f079eb5 358#elif defined(CONFIG_LCD)
5a541945 359# ifdef CONFIG_FB_ADDR
1938f4a5 360 gd->fb_base = CONFIG_FB_ADDR;
5a541945 361# else
1938f4a5 362 /* reserve memory for LCD display (always full pages) */
a0ba279a
MY
363 gd->relocaddr = lcd_setmem(gd->relocaddr);
364 gd->fb_base = gd->relocaddr;
5a541945 365# endif /* CONFIG_FB_ADDR */
0f079eb5 366#elif defined(CONFIG_VIDEO) && \
5b8e76c3 367 (!defined(CONFIG_PPC)) && \
d54d7eb9 368 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \
ea3310e8 369 !defined(CONFIG_M68K)
e4fef6cf 370 /* reserve memory for video display (always full pages) */
a0ba279a
MY
371 gd->relocaddr = video_setmem(gd->relocaddr);
372 gd->fb_base = gd->relocaddr;
0f079eb5 373#endif
e4fef6cf
SG
374
375 return 0;
376}
e4fef6cf 377
8703ef3f
SG
378static int reserve_trace(void)
379{
380#ifdef CONFIG_TRACE
381 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
382 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
383 debug("Reserving %dk for trace data at: %08lx\n",
384 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
385#endif
386
387 return 0;
388}
389
1938f4a5
SG
390static int reserve_uboot(void)
391{
392 /*
393 * reserve memory for U-Boot code, data & bss
394 * round down to next 4 kB limit
395 */
a0ba279a
MY
396 gd->relocaddr -= gd->mon_len;
397 gd->relocaddr &= ~(4096 - 1);
703ec9dd 398#if defined(CONFIG_E500) || defined(CONFIG_MIPS)
e4fef6cf 399 /* round down to next 64 kB limit so that IVPR stays aligned */
a0ba279a 400 gd->relocaddr &= ~(65536 - 1);
e4fef6cf 401#endif
1938f4a5
SG
402
403 debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10,
a0ba279a
MY
404 gd->relocaddr);
405
406 gd->start_addr_sp = gd->relocaddr;
407
1938f4a5
SG
408 return 0;
409}
410
411/* reserve memory for malloc() area */
412static int reserve_malloc(void)
413{
a0ba279a 414 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
1938f4a5 415 debug("Reserving %dk for malloc() at: %08lx\n",
a0ba279a 416 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
1938f4a5
SG
417 return 0;
418}
419
420/* (permanently) allocate a Board Info struct */
421static int reserve_board(void)
422{
d54d7eb9
SZ
423 if (!gd->bd) {
424 gd->start_addr_sp -= sizeof(bd_t);
425 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
426 memset(gd->bd, '\0', sizeof(bd_t));
427 debug("Reserving %zu Bytes for Board Info at: %08lx\n",
428 sizeof(bd_t), gd->start_addr_sp);
429 }
1938f4a5
SG
430 return 0;
431}
432
433static int setup_machine(void)
434{
435#ifdef CONFIG_MACH_TYPE
436 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
437#endif
438 return 0;
439}
440
441static int reserve_global_data(void)
442{
a0ba279a
MY
443 gd->start_addr_sp -= sizeof(gd_t);
444 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
1938f4a5 445 debug("Reserving %zu Bytes for Global Data at: %08lx\n",
a0ba279a 446 sizeof(gd_t), gd->start_addr_sp);
1938f4a5
SG
447 return 0;
448}
449
450static int reserve_fdt(void)
451{
e9acb9ea 452#ifndef CONFIG_OF_EMBED
1938f4a5 453 /*
4c509343 454 * If the device tree is sitting immediately above our image then we
1938f4a5
SG
455 * must relocate it. If it is embedded in the data section, then it
456 * will be relocated with other data.
457 */
458 if (gd->fdt_blob) {
459 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
460
a0ba279a
MY
461 gd->start_addr_sp -= gd->fdt_size;
462 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
a733b06b 463 debug("Reserving %lu Bytes for FDT at: %08lx\n",
a0ba279a 464 gd->fdt_size, gd->start_addr_sp);
1938f4a5 465 }
e9acb9ea 466#endif
1938f4a5
SG
467
468 return 0;
469}
470
25e7dc6a
SG
471static int reserve_bootstage(void)
472{
473#ifdef CONFIG_BOOTSTAGE
474 int size = bootstage_get_size();
475
476 gd->start_addr_sp -= size;
477 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
478 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
479 gd->start_addr_sp);
480#endif
481
482 return 0;
483}
484
68145d4c 485int arch_reserve_stacks(void)
1938f4a5 486{
68145d4c
AB
487 return 0;
488}
8cae8a68 489
68145d4c
AB
490static int reserve_stacks(void)
491{
492 /* make stack pointer 16-byte aligned */
a0ba279a
MY
493 gd->start_addr_sp -= 16;
494 gd->start_addr_sp &= ~0xf;
1938f4a5
SG
495
496 /*
4c509343 497 * let the architecture-specific code tailor gd->start_addr_sp and
68145d4c 498 * gd->irq_sp
1938f4a5 499 */
68145d4c 500 return arch_reserve_stacks();
1938f4a5
SG
501}
502
503static int display_new_sp(void)
504{
a0ba279a 505 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
1938f4a5
SG
506
507 return 0;
508}
509
e2099d78
VZ
510#if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
511 defined(CONFIG_SH)
e4fef6cf
SG
512static int setup_board_part1(void)
513{
514 bd_t *bd = gd->bd;
515
516 /*
517 * Save local variables to board info struct
518 */
e4fef6cf
SG
519 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
520 bd->bi_memsize = gd->ram_size; /* size in bytes */
521
522#ifdef CONFIG_SYS_SRAM_BASE
523 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
524 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
525#endif
526
50258977 527#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
e4fef6cf
SG
528 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
529#endif
064b55cf 530#if defined(CONFIG_M68K)
e4fef6cf
SG
531 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
532#endif
533#if defined(CONFIG_MPC83xx)
534 bd->bi_immrbar = CONFIG_SYS_IMMR;
535#endif
e4fef6cf
SG
536
537 return 0;
538}
fb3db635 539#endif
e4fef6cf 540
fb3db635 541#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
e4fef6cf
SG
542static int setup_board_part2(void)
543{
544 bd_t *bd = gd->bd;
545
546 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
547 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
548#if defined(CONFIG_CPM2)
549 bd->bi_cpmfreq = gd->arch.cpm_clk;
550 bd->bi_brgfreq = gd->arch.brg_clk;
551 bd->bi_sccfreq = gd->arch.scc_clk;
552 bd->bi_vco = gd->arch.vco_out;
553#endif /* CONFIG_CPM2 */
1313db48
AW
554#if defined(CONFIG_M68K) && defined(CONFIG_PCI)
555 bd->bi_pcifreq = gd->pci_clk;
556#endif
557#if defined(CONFIG_EXTRA_CLOCK)
558 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
559 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
560 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
561#endif
e4fef6cf
SG
562
563 return 0;
564}
565#endif
566
1938f4a5
SG
567#ifdef CONFIG_POST
568static int init_post(void)
569{
570 post_bootmode_init();
571 post_run(NULL, POST_ROM | post_bootmode_get(0));
572
573 return 0;
574}
575#endif
576
1938f4a5
SG
577static int reloc_fdt(void)
578{
e9acb9ea 579#ifndef CONFIG_OF_EMBED
f05ad9ba
SG
580 if (gd->flags & GD_FLG_SKIP_RELOC)
581 return 0;
1938f4a5
SG
582 if (gd->new_fdt) {
583 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
584 gd->fdt_blob = gd->new_fdt;
585 }
e9acb9ea 586#endif
1938f4a5
SG
587
588 return 0;
589}
590
25e7dc6a
SG
591static int reloc_bootstage(void)
592{
593#ifdef CONFIG_BOOTSTAGE
594 if (gd->flags & GD_FLG_SKIP_RELOC)
595 return 0;
596 if (gd->new_bootstage) {
597 int size = bootstage_get_size();
598
599 debug("Copying bootstage from %p to %p, size %x\n",
600 gd->bootstage, gd->new_bootstage, size);
601 memcpy(gd->new_bootstage, gd->bootstage, size);
602 gd->bootstage = gd->new_bootstage;
603 }
604#endif
605
606 return 0;
607}
608
1938f4a5
SG
609static int setup_reloc(void)
610{
f05ad9ba
SG
611 if (gd->flags & GD_FLG_SKIP_RELOC) {
612 debug("Skipping relocation due to flag\n");
613 return 0;
614 }
615
d54d7eb9 616#ifdef CONFIG_SYS_TEXT_BASE
53207bfd
LW
617#ifdef ARM
618 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
619#elif defined(CONFIG_M68K)
e310b93e 620 /*
621 * On all ColdFire arch cpu, monitor code starts always
622 * just after the default vector table location, so at 0x400
623 */
624 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
53207bfd
LW
625#else
626 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
e310b93e 627#endif
d54d7eb9 628#endif
1938f4a5
SG
629 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
630
631 debug("Relocation Offset is: %08lx\n", gd->reloc_off);
a733b06b 632 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
a0ba279a
MY
633 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
634 gd->start_addr_sp);
1938f4a5
SG
635
636 return 0;
637}
638
2a792753 639#ifdef CONFIG_OF_BOARD_FIXUP
640static int fix_fdt(void)
641{
642 return board_fix_fdt((void *)gd->fdt_blob);
643}
644#endif
645
1938f4a5 646/* ARM calls relocate_code from its crt0.S */
530f27ea
SG
647#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
648 !CONFIG_IS_ENABLED(X86_64)
1938f4a5
SG
649
650static int jump_to_copy(void)
651{
f05ad9ba
SG
652 if (gd->flags & GD_FLG_SKIP_RELOC)
653 return 0;
48a33806
SG
654 /*
655 * x86 is special, but in a nice way. It uses a trampoline which
656 * enables the dcache if possible.
657 *
658 * For now, other archs use relocate_code(), which is implemented
659 * similarly for all archs. When we do generic relocation, hopefully
660 * we can make all archs enable the dcache prior to relocation.
661 */
3fb80163 662#if defined(CONFIG_X86) || defined(CONFIG_ARC)
48a33806
SG
663 /*
664 * SDRAM and console are now initialised. The final stack can now
665 * be setup in SDRAM. Code execution will continue in Flash, but
666 * with the stack in SDRAM and Global Data in temporary memory
667 * (CPU cache)
668 */
f0c7d9c7 669 arch_setup_gd(gd->new_gd);
48a33806
SG
670 board_init_f_r_trampoline(gd->start_addr_sp);
671#else
a0ba279a 672 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
48a33806 673#endif
1938f4a5
SG
674
675 return 0;
676}
677#endif
678
679/* Record the board_init_f() bootstage (after arch_cpu_init()) */
b383d6c0 680static int initf_bootstage(void)
1938f4a5 681{
baa7d345
SG
682 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
683 IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
b383d6c0
SG
684 int ret;
685
824bb1b4 686 ret = bootstage_init(!from_spl);
b383d6c0
SG
687 if (ret)
688 return ret;
824bb1b4
SG
689 if (from_spl) {
690 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
691 CONFIG_BOOTSTAGE_STASH_SIZE);
692
693 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
694 if (ret && ret != -ENOENT) {
695 debug("Failed to unstash bootstage: err=%d\n", ret);
696 return ret;
697 }
698 }
b383d6c0 699
1938f4a5
SG
700 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
701
702 return 0;
703}
704
9854a874
SG
705static int initf_console_record(void)
706{
f1896c45 707#if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
9854a874
SG
708 return console_record_init();
709#else
710 return 0;
711#endif
712}
713
ab7cd627
SG
714static int initf_dm(void)
715{
f1896c45 716#if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
ab7cd627
SG
717 int ret;
718
63c5bf48 719 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f");
ab7cd627 720 ret = dm_init_and_scan(true);
63c5bf48 721 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F);
ab7cd627
SG
722 if (ret)
723 return ret;
724#endif
1057e6cf
SG
725#ifdef CONFIG_TIMER_EARLY
726 ret = dm_timer_init();
727 if (ret)
728 return ret;
729#endif
ab7cd627
SG
730
731 return 0;
732}
733
146251f8
SG
734/* Architecture-specific memory reservation */
735__weak int reserve_arch(void)
736{
737 return 0;
738}
739
d4c671cc
SG
740__weak int arch_cpu_init_dm(void)
741{
742 return 0;
743}
744
4acff452 745static const init_fnc_t init_sequence_f[] = {
1938f4a5 746 setup_mon_len,
b45122fd 747#ifdef CONFIG_OF_CONTROL
0879361f 748 fdtdec_setup,
b45122fd 749#endif
d210718d 750#ifdef CONFIG_TRACE
71c52dba 751 trace_early_init,
d210718d 752#endif
768e0f52 753 initf_malloc,
af1bc0cf 754 log_init,
5ac44a55 755 initf_bootstage, /* uses its own timer, so does not need DM */
9854a874 756 initf_console_record,
671549e5
SG
757#if defined(CONFIG_HAVE_FSP)
758 arch_fsp_init,
e4fef6cf 759#endif
1938f4a5 760 arch_cpu_init, /* basic arch cpu dependent setup */
8ebf5069 761 mach_cpu_init, /* SoC/machine dependent CPU setup */
3ea0953d 762 initf_dm,
d4c671cc 763 arch_cpu_init_dm,
1938f4a5
SG
764#if defined(CONFIG_BOARD_EARLY_INIT_F)
765 board_early_init_f,
766#endif
727e94a4 767#if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
c252c068 768 /* get CPU and bus clocks according to the environment variable */
e4fef6cf 769 get_clocks, /* get CPU and bus clocks (etc.) */
1793e782 770#endif
0ce45287 771#if !defined(CONFIG_M68K)
1938f4a5 772 timer_init, /* initialize timer */
0ce45287 773#endif
e4fef6cf
SG
774#if defined(CONFIG_BOARD_POSTCLK_INIT)
775 board_postclk_init,
1938f4a5
SG
776#endif
777 env_init, /* initialize environment */
778 init_baud_rate, /* initialze baudrate settings */
779 serial_init, /* serial communications setup */
780 console_init_f, /* stage 1 init of console */
781 display_options, /* say that we are here */
782 display_text_info, /* show debugging info if required */
76d1d02f
SG
783#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH) || \
784 defined(CONFIG_X86)
e4fef6cf
SG
785 checkcpu,
786#endif
cc664000 787#if defined(CONFIG_DISPLAY_CPUINFO)
1938f4a5 788 print_cpuinfo, /* display cpu info (and speed) */
cc664000 789#endif
af9e6ad4
CJF
790#if defined(CONFIG_DTB_RESELECT)
791 embedded_dtb_select,
792#endif
1938f4a5 793#if defined(CONFIG_DISPLAY_BOARDINFO)
0365ffcc 794 show_board_info,
e4fef6cf
SG
795#endif
796 INIT_FUNC_WATCHDOG_INIT
797#if defined(CONFIG_MISC_INIT_F)
798 misc_init_f,
799#endif
800 INIT_FUNC_WATCHDOG_RESET
69153988 801#if defined(CONFIG_SYS_I2C)
e4fef6cf
SG
802 init_func_i2c,
803#endif
804#if defined(CONFIG_HARD_SPI)
805 init_func_spi,
1938f4a5
SG
806#endif
807 announce_dram_init,
1938f4a5 808 dram_init, /* configure available RAM banks */
e4fef6cf
SG
809#ifdef CONFIG_POST
810 post_init_f,
811#endif
812 INIT_FUNC_WATCHDOG_RESET
813#if defined(CONFIG_SYS_DRAM_TEST)
814 testdram,
815#endif /* CONFIG_SYS_DRAM_TEST */
816 INIT_FUNC_WATCHDOG_RESET
817
1938f4a5
SG
818#ifdef CONFIG_POST
819 init_post,
820#endif
e4fef6cf 821 INIT_FUNC_WATCHDOG_RESET
1938f4a5
SG
822 /*
823 * Now that we have DRAM mapped and working, we can
824 * relocate the code and continue running from DRAM.
825 *
826 * Reserve memory at end of RAM for (top down in that order):
827 * - area that won't get touched by U-Boot and Linux (optional)
828 * - kernel log buffer
829 * - protected RAM
830 * - LCD framebuffer
831 * - monitor code
832 * - board info struct
833 */
834 setup_dest_addr,
1938f4a5
SG
835#ifdef CONFIG_PRAM
836 reserve_pram,
837#endif
838 reserve_round_4k,
80d4bcd3 839#ifdef CONFIG_ARM
1938f4a5
SG
840 reserve_mmu,
841#endif
5a541945 842 reserve_video,
8703ef3f 843 reserve_trace,
1938f4a5
SG
844 reserve_uboot,
845 reserve_malloc,
846 reserve_board,
847 setup_machine,
848 reserve_global_data,
849 reserve_fdt,
25e7dc6a 850 reserve_bootstage,
146251f8 851 reserve_arch,
1938f4a5 852 reserve_stacks,
76b00aca 853 dram_init_banksize,
1938f4a5 854 show_dram_config,
e2099d78
VZ
855#if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
856 defined(CONFIG_SH)
e4fef6cf 857 setup_board_part1,
fb3db635
DS
858#endif
859#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
e4fef6cf
SG
860 INIT_FUNC_WATCHDOG_RESET
861 setup_board_part2,
862#endif
1938f4a5 863 display_new_sp,
2a792753 864#ifdef CONFIG_OF_BOARD_FIXUP
865 fix_fdt,
e4fef6cf
SG
866#endif
867 INIT_FUNC_WATCHDOG_RESET
1938f4a5 868 reloc_fdt,
25e7dc6a 869 reloc_bootstage,
1938f4a5 870 setup_reloc,
3fb80163 871#if defined(CONFIG_X86) || defined(CONFIG_ARC)
313aef37 872 copy_uboot_to_ram,
313aef37 873 do_elf_reloc_fixups,
6bda55a3 874 clear_bss,
313aef37 875#endif
de5e5cea
CZ
876#if defined(CONFIG_XTENSA)
877 clear_bss,
878#endif
530f27ea
SG
879#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
880 !CONFIG_IS_ENABLED(X86_64)
1938f4a5
SG
881 jump_to_copy,
882#endif
883 NULL,
884};
885
886void board_init_f(ulong boot_flags)
887{
1938f4a5 888 gd->flags = boot_flags;
9aed5a27 889 gd->have_console = 0;
1938f4a5
SG
890
891 if (initcall_run_list(init_sequence_f))
892 hang();
893
9b217498 894#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
530f27ea 895 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64)
1938f4a5
SG
896 /* NOTREACHED - jump_to_copy() does not return */
897 hang();
898#endif
899}
900
3fb80163 901#if defined(CONFIG_X86) || defined(CONFIG_ARC)
48a33806
SG
902/*
903 * For now this code is only used on x86.
904 *
905 * init_sequence_f_r is the list of init functions which are run when
906 * U-Boot is executing from Flash with a semi-limited 'C' environment.
907 * The following limitations must be considered when implementing an
908 * '_f_r' function:
909 * - 'static' variables are read-only
910 * - Global Data (gd->xxx) is read/write
911 *
912 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
913 * supported). It _should_, if possible, copy global data to RAM and
914 * initialise the CPU caches (to speed up the relocation process)
915 *
916 * NOTE: At present only x86 uses this route, but it is intended that
917 * all archs will move to this when generic relocation is implemented.
918 */
4acff452 919static const init_fnc_t init_sequence_f_r[] = {
530f27ea 920#if !CONFIG_IS_ENABLED(X86_64)
48a33806 921 init_cache_f_r,
530f27ea 922#endif
48a33806
SG
923
924 NULL,
925};
926
927void board_init_f_r(void)
928{
929 if (initcall_run_list(init_sequence_f_r))
930 hang();
931
e4d6ab0c
SG
932 /*
933 * The pre-relocation drivers may be using memory that has now gone
934 * away. Mark serial as unavailable - this will fall back to the debug
935 * UART if available.
af1bc0cf
SG
936 *
937 * Do the same with log drivers since the memory may not be available.
e4d6ab0c 938 */
af1bc0cf 939 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
5ee94b4f
SG
940#ifdef CONFIG_TIMER
941 gd->timer = NULL;
942#endif
e4d6ab0c 943
48a33806
SG
944 /*
945 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
946 * Transfer execution from Flash to RAM by calculating the address
947 * of the in-RAM copy of board_init_r() and calling it
948 */
7bf9f20d 949 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
48a33806
SG
950
951 /* NOTREACHED - board_init_r() does not return */
952 hang();
953}
5bcd19aa 954#endif /* CONFIG_X86 */