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Commit | Line | Data |
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1938f4a5 SG |
1 | /* |
2 | * Copyright (c) 2011 The Chromium OS Authors. | |
3 | * (C) Copyright 2002-2006 | |
4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
5 | * | |
6 | * (C) Copyright 2002 | |
7 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
8 | * Marius Groeger <mgroeger@sysgo.de> | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
1938f4a5 SG |
11 | */ |
12 | ||
13 | #include <common.h> | |
24b852a7 | 14 | #include <console.h> |
1938f4a5 | 15 | #include <environment.h> |
ab7cd627 | 16 | #include <dm.h> |
1938f4a5 | 17 | #include <fdtdec.h> |
f828bf25 | 18 | #include <fs.h> |
e4fef6cf | 19 | #include <i2c.h> |
1938f4a5 | 20 | #include <initcall.h> |
96d4b75c | 21 | #include <init_helpers.h> |
1938f4a5 | 22 | #include <logbuff.h> |
fb5cf7f1 | 23 | #include <malloc.h> |
0eb25b61 | 24 | #include <mapmem.h> |
a733b06b | 25 | #include <os.h> |
1938f4a5 | 26 | #include <post.h> |
e47b2d67 | 27 | #include <relocate.h> |
e4fef6cf | 28 | #include <spi.h> |
c5d4001a | 29 | #include <status_led.h> |
1057e6cf | 30 | #include <timer.h> |
71c52dba | 31 | #include <trace.h> |
5a541945 | 32 | #include <video.h> |
e4fef6cf | 33 | #include <watchdog.h> |
b885d02e SG |
34 | #ifdef CONFIG_MACH_TYPE |
35 | #include <asm/mach-types.h> | |
36 | #endif | |
1fbf97dc SG |
37 | #if defined(CONFIG_MP) && defined(CONFIG_PPC) |
38 | #include <asm/mp.h> | |
39 | #endif | |
1938f4a5 SG |
40 | #include <asm/io.h> |
41 | #include <asm/sections.h> | |
ab7cd627 | 42 | #include <dm/root.h> |
056285fd | 43 | #include <linux/errno.h> |
1938f4a5 SG |
44 | |
45 | /* | |
46 | * Pointer to initial global data area | |
47 | * | |
48 | * Here we initialize it if needed. | |
49 | */ | |
50 | #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR | |
51 | #undef XTRN_DECLARE_GLOBAL_DATA_PTR | |
52 | #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ | |
53 | DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); | |
54 | #else | |
55 | DECLARE_GLOBAL_DATA_PTR; | |
56 | #endif | |
57 | ||
58 | /* | |
4c509343 | 59 | * TODO(sjg@chromium.org): IMO this code should be |
1938f4a5 SG |
60 | * refactored to a single function, something like: |
61 | * | |
62 | * void led_set_state(enum led_colour_t colour, int on); | |
63 | */ | |
64 | /************************************************************************ | |
65 | * Coloured LED functionality | |
66 | ************************************************************************ | |
67 | * May be supplied by boards if desired | |
68 | */ | |
c5d4001a JH |
69 | __weak void coloured_LED_init(void) {} |
70 | __weak void red_led_on(void) {} | |
71 | __weak void red_led_off(void) {} | |
72 | __weak void green_led_on(void) {} | |
73 | __weak void green_led_off(void) {} | |
74 | __weak void yellow_led_on(void) {} | |
75 | __weak void yellow_led_off(void) {} | |
76 | __weak void blue_led_on(void) {} | |
77 | __weak void blue_led_off(void) {} | |
1938f4a5 SG |
78 | |
79 | /* | |
80 | * Why is gd allocated a register? Prior to reloc it might be better to | |
81 | * just pass it around to each function in this file? | |
82 | * | |
83 | * After reloc one could argue that it is hardly used and doesn't need | |
84 | * to be in a register. Or if it is it should perhaps hold pointers to all | |
85 | * global data for all modules, so that post-reloc we can avoid the massive | |
86 | * literal pool we get on ARM. Or perhaps just encourage each module to use | |
87 | * a structure... | |
88 | */ | |
89 | ||
d54d7eb9 | 90 | #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) |
e4fef6cf SG |
91 | static int init_func_watchdog_init(void) |
92 | { | |
ea3310e8 TR |
93 | # if defined(CONFIG_HW_WATCHDOG) && \ |
94 | (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ | |
14a380a8 | 95 | defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ |
46d7a3b3 | 96 | defined(CONFIG_DESIGNWARE_WATCHDOG) || \ |
14a380a8 | 97 | defined(CONFIG_IMX_WATCHDOG)) |
d54d7eb9 | 98 | hw_watchdog_init(); |
e4fef6cf | 99 | puts(" Watchdog enabled\n"); |
ba169d98 | 100 | # endif |
e4fef6cf SG |
101 | WATCHDOG_RESET(); |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
106 | int init_func_watchdog_reset(void) | |
107 | { | |
108 | WATCHDOG_RESET(); | |
109 | ||
110 | return 0; | |
111 | } | |
112 | #endif /* CONFIG_WATCHDOG */ | |
113 | ||
dd2a6cd0 | 114 | __weak void board_add_ram_info(int use_default) |
e4fef6cf SG |
115 | { |
116 | /* please define platform specific board_add_ram_info() */ | |
117 | } | |
118 | ||
1938f4a5 SG |
119 | static int init_baud_rate(void) |
120 | { | |
121 | gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); | |
122 | return 0; | |
123 | } | |
124 | ||
125 | static int display_text_info(void) | |
126 | { | |
9b217498 | 127 | #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) |
9fdee7d7 | 128 | ulong bss_start, bss_end, text_base; |
1938f4a5 | 129 | |
632efa74 SG |
130 | bss_start = (ulong)&__bss_start; |
131 | bss_end = (ulong)&__bss_end; | |
b60eff31 | 132 | |
d54d7eb9 | 133 | #ifdef CONFIG_SYS_TEXT_BASE |
9fdee7d7 | 134 | text_base = CONFIG_SYS_TEXT_BASE; |
d54d7eb9 | 135 | #else |
9fdee7d7 | 136 | text_base = CONFIG_SYS_MONITOR_BASE; |
d54d7eb9 | 137 | #endif |
9fdee7d7 DS |
138 | |
139 | debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", | |
140 | text_base, bss_start, bss_end); | |
a733b06b | 141 | #endif |
1938f4a5 | 142 | |
1938f4a5 SG |
143 | return 0; |
144 | } | |
145 | ||
146 | static int announce_dram_init(void) | |
147 | { | |
148 | puts("DRAM: "); | |
149 | return 0; | |
150 | } | |
151 | ||
152 | static int show_dram_config(void) | |
153 | { | |
fa39ffe5 | 154 | unsigned long long size; |
1938f4a5 SG |
155 | |
156 | #ifdef CONFIG_NR_DRAM_BANKS | |
157 | int i; | |
158 | ||
159 | debug("\nRAM Configuration:\n"); | |
160 | for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
161 | size += gd->bd->bi_dram[i].size; | |
715f599f BM |
162 | debug("Bank #%d: %llx ", i, |
163 | (unsigned long long)(gd->bd->bi_dram[i].start)); | |
1938f4a5 SG |
164 | #ifdef DEBUG |
165 | print_size(gd->bd->bi_dram[i].size, "\n"); | |
166 | #endif | |
167 | } | |
168 | debug("\nDRAM: "); | |
169 | #else | |
170 | size = gd->ram_size; | |
171 | #endif | |
172 | ||
e4fef6cf SG |
173 | print_size(size, ""); |
174 | board_add_ram_info(0); | |
175 | putc('\n'); | |
1938f4a5 SG |
176 | |
177 | return 0; | |
178 | } | |
179 | ||
76b00aca | 180 | __weak int dram_init_banksize(void) |
1938f4a5 SG |
181 | { |
182 | #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) | |
183 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; | |
184 | gd->bd->bi_dram[0].size = get_effective_memsize(); | |
185 | #endif | |
76b00aca SG |
186 | |
187 | return 0; | |
1938f4a5 SG |
188 | } |
189 | ||
69153988 | 190 | #if defined(CONFIG_SYS_I2C) |
e4fef6cf SG |
191 | static int init_func_i2c(void) |
192 | { | |
193 | puts("I2C: "); | |
815a76f2 | 194 | #ifdef CONFIG_SYS_I2C |
195 | i2c_init_all(); | |
196 | #else | |
e4fef6cf | 197 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
815a76f2 | 198 | #endif |
e4fef6cf SG |
199 | puts("ready\n"); |
200 | return 0; | |
201 | } | |
202 | #endif | |
203 | ||
204 | #if defined(CONFIG_HARD_SPI) | |
205 | static int init_func_spi(void) | |
206 | { | |
207 | puts("SPI: "); | |
208 | spi_init(); | |
209 | puts("ready\n"); | |
210 | return 0; | |
211 | } | |
212 | #endif | |
213 | ||
214 | __maybe_unused | |
1938f4a5 SG |
215 | static int zero_global_data(void) |
216 | { | |
217 | memset((void *)gd, '\0', sizeof(gd_t)); | |
218 | ||
219 | return 0; | |
220 | } | |
221 | ||
222 | static int setup_mon_len(void) | |
223 | { | |
e945f6dc | 224 | #if defined(__ARM__) || defined(__MICROBLAZE__) |
b60eff31 | 225 | gd->mon_len = (ulong)&__bss_end - (ulong)_start; |
9b217498 | 226 | #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) |
a733b06b | 227 | gd->mon_len = (ulong)&_end - (ulong)_init; |
ea3310e8 | 228 | #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) |
d54d7eb9 | 229 | gd->mon_len = CONFIG_SYS_MONITOR_LEN; |
e2099d78 | 230 | #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) |
2e88bb28 | 231 | gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); |
b0b35953 | 232 | #elif defined(CONFIG_SYS_MONITOR_BASE) |
e4fef6cf SG |
233 | /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ |
234 | gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; | |
632efa74 | 235 | #endif |
1938f4a5 SG |
236 | return 0; |
237 | } | |
238 | ||
239 | __weak int arch_cpu_init(void) | |
240 | { | |
241 | return 0; | |
242 | } | |
243 | ||
8ebf5069 PB |
244 | __weak int mach_cpu_init(void) |
245 | { | |
246 | return 0; | |
247 | } | |
248 | ||
1938f4a5 SG |
249 | /* Get the top of usable RAM */ |
250 | __weak ulong board_get_usable_ram_top(ulong total_size) | |
251 | { | |
1e4d11a5 SW |
252 | #ifdef CONFIG_SYS_SDRAM_BASE |
253 | /* | |
4c509343 | 254 | * Detect whether we have so much RAM that it goes past the end of our |
1e4d11a5 SW |
255 | * 32-bit address space. If so, clip the usable RAM so it doesn't. |
256 | */ | |
257 | if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) | |
258 | /* | |
259 | * Will wrap back to top of 32-bit space when reservations | |
260 | * are made. | |
261 | */ | |
262 | return 0; | |
263 | #endif | |
1938f4a5 SG |
264 | return gd->ram_top; |
265 | } | |
266 | ||
267 | static int setup_dest_addr(void) | |
268 | { | |
269 | debug("Monitor len: %08lX\n", gd->mon_len); | |
270 | /* | |
271 | * Ram is setup, size stored in gd !! | |
272 | */ | |
273 | debug("Ram size: %08lX\n", (ulong)gd->ram_size); | |
36cc0de0 | 274 | #if defined(CONFIG_SYS_MEM_TOP_HIDE) |
1938f4a5 SG |
275 | /* |
276 | * Subtract specified amount of memory to hide so that it won't | |
277 | * get "touched" at all by U-Boot. By fixing up gd->ram_size | |
278 | * the Linux kernel should now get passed the now "corrected" | |
36cc0de0 YS |
279 | * memory size and won't touch it either. This should work |
280 | * for arch/ppc and arch/powerpc. Only Linux board ports in | |
281 | * arch/powerpc with bootwrapper support, that recalculate the | |
282 | * memory size from the SDRAM controller setup will have to | |
283 | * get fixed. | |
1938f4a5 | 284 | */ |
36cc0de0 YS |
285 | gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; |
286 | #endif | |
1938f4a5 SG |
287 | #ifdef CONFIG_SYS_SDRAM_BASE |
288 | gd->ram_top = CONFIG_SYS_SDRAM_BASE; | |
289 | #endif | |
e4fef6cf | 290 | gd->ram_top += get_effective_memsize(); |
1938f4a5 | 291 | gd->ram_top = board_get_usable_ram_top(gd->mon_len); |
a0ba279a | 292 | gd->relocaddr = gd->ram_top; |
1938f4a5 | 293 | debug("Ram top: %08lX\n", (ulong)gd->ram_top); |
ec3b4820 | 294 | #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) |
e4fef6cf SG |
295 | /* |
296 | * We need to make sure the location we intend to put secondary core | |
297 | * boot code is reserved and not used by any part of u-boot | |
298 | */ | |
a0ba279a MY |
299 | if (gd->relocaddr > determine_mp_bootpg(NULL)) { |
300 | gd->relocaddr = determine_mp_bootpg(NULL); | |
301 | debug("Reserving MP boot page to %08lx\n", gd->relocaddr); | |
e4fef6cf SG |
302 | } |
303 | #endif | |
1938f4a5 SG |
304 | return 0; |
305 | } | |
306 | ||
b56db486 | 307 | #if defined(CONFIG_LOGBUFFER) |
1938f4a5 SG |
308 | static int reserve_logbuffer(void) |
309 | { | |
b56db486 | 310 | #ifndef CONFIG_ALT_LB_ADDR |
1938f4a5 | 311 | /* reserve kernel log buffer */ |
a0ba279a | 312 | gd->relocaddr -= LOGBUFF_RESERVE; |
1938f4a5 | 313 | debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, |
a0ba279a | 314 | gd->relocaddr); |
b56db486 SG |
315 | #endif |
316 | ||
1938f4a5 SG |
317 | return 0; |
318 | } | |
319 | #endif | |
320 | ||
321 | #ifdef CONFIG_PRAM | |
322 | /* reserve protected RAM */ | |
323 | static int reserve_pram(void) | |
324 | { | |
325 | ulong reg; | |
326 | ||
327 | reg = getenv_ulong("pram", 10, CONFIG_PRAM); | |
a0ba279a | 328 | gd->relocaddr -= (reg << 10); /* size is in kB */ |
1938f4a5 | 329 | debug("Reserving %ldk for protected RAM at %08lx\n", reg, |
a0ba279a | 330 | gd->relocaddr); |
1938f4a5 SG |
331 | return 0; |
332 | } | |
333 | #endif /* CONFIG_PRAM */ | |
334 | ||
335 | /* Round memory pointer down to next 4 kB limit */ | |
336 | static int reserve_round_4k(void) | |
337 | { | |
a0ba279a | 338 | gd->relocaddr &= ~(4096 - 1); |
1938f4a5 SG |
339 | return 0; |
340 | } | |
341 | ||
80d4bcd3 | 342 | #ifdef CONFIG_ARM |
1938f4a5 SG |
343 | static int reserve_mmu(void) |
344 | { | |
80d4bcd3 | 345 | #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) |
1938f4a5 | 346 | /* reserve TLB table */ |
cce6be7f | 347 | gd->arch.tlb_size = PGTABLE_SIZE; |
a0ba279a | 348 | gd->relocaddr -= gd->arch.tlb_size; |
1938f4a5 SG |
349 | |
350 | /* round down to next 64 kB limit */ | |
a0ba279a | 351 | gd->relocaddr &= ~(0x10000 - 1); |
1938f4a5 | 352 | |
a0ba279a | 353 | gd->arch.tlb_addr = gd->relocaddr; |
1938f4a5 SG |
354 | debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, |
355 | gd->arch.tlb_addr + gd->arch.tlb_size); | |
50e93b95 YS |
356 | |
357 | #ifdef CONFIG_SYS_MEM_RESERVE_SECURE | |
358 | /* | |
359 | * Record allocated tlb_addr in case gd->tlb_addr to be overwritten | |
360 | * with location within secure ram. | |
361 | */ | |
362 | gd->arch.tlb_allocated = gd->arch.tlb_addr; | |
80d4bcd3 | 363 | #endif |
50e93b95 YS |
364 | #endif |
365 | ||
1938f4a5 SG |
366 | return 0; |
367 | } | |
368 | #endif | |
369 | ||
5a541945 SG |
370 | static int reserve_video(void) |
371 | { | |
0f079eb5 | 372 | #ifdef CONFIG_DM_VIDEO |
5a541945 SG |
373 | ulong addr; |
374 | int ret; | |
375 | ||
376 | addr = gd->relocaddr; | |
377 | ret = video_reserve(&addr); | |
378 | if (ret) | |
379 | return ret; | |
380 | gd->relocaddr = addr; | |
0f079eb5 | 381 | #elif defined(CONFIG_LCD) |
5a541945 | 382 | # ifdef CONFIG_FB_ADDR |
1938f4a5 | 383 | gd->fb_base = CONFIG_FB_ADDR; |
5a541945 | 384 | # else |
1938f4a5 | 385 | /* reserve memory for LCD display (always full pages) */ |
a0ba279a MY |
386 | gd->relocaddr = lcd_setmem(gd->relocaddr); |
387 | gd->fb_base = gd->relocaddr; | |
5a541945 | 388 | # endif /* CONFIG_FB_ADDR */ |
0f079eb5 | 389 | #elif defined(CONFIG_VIDEO) && \ |
5b8e76c3 | 390 | (!defined(CONFIG_PPC)) && \ |
d54d7eb9 | 391 | !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ |
ea3310e8 | 392 | !defined(CONFIG_M68K) |
e4fef6cf | 393 | /* reserve memory for video display (always full pages) */ |
a0ba279a MY |
394 | gd->relocaddr = video_setmem(gd->relocaddr); |
395 | gd->fb_base = gd->relocaddr; | |
0f079eb5 | 396 | #endif |
e4fef6cf SG |
397 | |
398 | return 0; | |
399 | } | |
e4fef6cf | 400 | |
8703ef3f SG |
401 | static int reserve_trace(void) |
402 | { | |
403 | #ifdef CONFIG_TRACE | |
404 | gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; | |
405 | gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); | |
406 | debug("Reserving %dk for trace data at: %08lx\n", | |
407 | CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); | |
408 | #endif | |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
1938f4a5 SG |
413 | static int reserve_uboot(void) |
414 | { | |
415 | /* | |
416 | * reserve memory for U-Boot code, data & bss | |
417 | * round down to next 4 kB limit | |
418 | */ | |
a0ba279a MY |
419 | gd->relocaddr -= gd->mon_len; |
420 | gd->relocaddr &= ~(4096 - 1); | |
e4fef6cf SG |
421 | #ifdef CONFIG_E500 |
422 | /* round down to next 64 kB limit so that IVPR stays aligned */ | |
a0ba279a | 423 | gd->relocaddr &= ~(65536 - 1); |
e4fef6cf | 424 | #endif |
1938f4a5 SG |
425 | |
426 | debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, | |
a0ba279a MY |
427 | gd->relocaddr); |
428 | ||
429 | gd->start_addr_sp = gd->relocaddr; | |
430 | ||
1938f4a5 SG |
431 | return 0; |
432 | } | |
433 | ||
434 | /* reserve memory for malloc() area */ | |
435 | static int reserve_malloc(void) | |
436 | { | |
a0ba279a | 437 | gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; |
1938f4a5 | 438 | debug("Reserving %dk for malloc() at: %08lx\n", |
a0ba279a | 439 | TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); |
1938f4a5 SG |
440 | return 0; |
441 | } | |
442 | ||
443 | /* (permanently) allocate a Board Info struct */ | |
444 | static int reserve_board(void) | |
445 | { | |
d54d7eb9 SZ |
446 | if (!gd->bd) { |
447 | gd->start_addr_sp -= sizeof(bd_t); | |
448 | gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); | |
449 | memset(gd->bd, '\0', sizeof(bd_t)); | |
450 | debug("Reserving %zu Bytes for Board Info at: %08lx\n", | |
451 | sizeof(bd_t), gd->start_addr_sp); | |
452 | } | |
1938f4a5 SG |
453 | return 0; |
454 | } | |
455 | ||
456 | static int setup_machine(void) | |
457 | { | |
458 | #ifdef CONFIG_MACH_TYPE | |
459 | gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ | |
460 | #endif | |
461 | return 0; | |
462 | } | |
463 | ||
464 | static int reserve_global_data(void) | |
465 | { | |
a0ba279a MY |
466 | gd->start_addr_sp -= sizeof(gd_t); |
467 | gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); | |
1938f4a5 | 468 | debug("Reserving %zu Bytes for Global Data at: %08lx\n", |
a0ba279a | 469 | sizeof(gd_t), gd->start_addr_sp); |
1938f4a5 SG |
470 | return 0; |
471 | } | |
472 | ||
473 | static int reserve_fdt(void) | |
474 | { | |
e9acb9ea | 475 | #ifndef CONFIG_OF_EMBED |
1938f4a5 | 476 | /* |
4c509343 | 477 | * If the device tree is sitting immediately above our image then we |
1938f4a5 SG |
478 | * must relocate it. If it is embedded in the data section, then it |
479 | * will be relocated with other data. | |
480 | */ | |
481 | if (gd->fdt_blob) { | |
482 | gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); | |
483 | ||
a0ba279a MY |
484 | gd->start_addr_sp -= gd->fdt_size; |
485 | gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); | |
a733b06b | 486 | debug("Reserving %lu Bytes for FDT at: %08lx\n", |
a0ba279a | 487 | gd->fdt_size, gd->start_addr_sp); |
1938f4a5 | 488 | } |
e9acb9ea | 489 | #endif |
1938f4a5 SG |
490 | |
491 | return 0; | |
492 | } | |
493 | ||
25e7dc6a SG |
494 | static int reserve_bootstage(void) |
495 | { | |
496 | #ifdef CONFIG_BOOTSTAGE | |
497 | int size = bootstage_get_size(); | |
498 | ||
499 | gd->start_addr_sp -= size; | |
500 | gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); | |
501 | debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, | |
502 | gd->start_addr_sp); | |
503 | #endif | |
504 | ||
505 | return 0; | |
506 | } | |
507 | ||
68145d4c | 508 | int arch_reserve_stacks(void) |
1938f4a5 | 509 | { |
68145d4c AB |
510 | return 0; |
511 | } | |
8cae8a68 | 512 | |
68145d4c AB |
513 | static int reserve_stacks(void) |
514 | { | |
515 | /* make stack pointer 16-byte aligned */ | |
a0ba279a MY |
516 | gd->start_addr_sp -= 16; |
517 | gd->start_addr_sp &= ~0xf; | |
1938f4a5 SG |
518 | |
519 | /* | |
4c509343 | 520 | * let the architecture-specific code tailor gd->start_addr_sp and |
68145d4c | 521 | * gd->irq_sp |
1938f4a5 | 522 | */ |
68145d4c | 523 | return arch_reserve_stacks(); |
1938f4a5 SG |
524 | } |
525 | ||
526 | static int display_new_sp(void) | |
527 | { | |
a0ba279a | 528 | debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); |
1938f4a5 SG |
529 | |
530 | return 0; | |
531 | } | |
532 | ||
e2099d78 VZ |
533 | #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ |
534 | defined(CONFIG_SH) | |
e4fef6cf SG |
535 | static int setup_board_part1(void) |
536 | { | |
537 | bd_t *bd = gd->bd; | |
538 | ||
539 | /* | |
540 | * Save local variables to board info struct | |
541 | */ | |
e4fef6cf SG |
542 | bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ |
543 | bd->bi_memsize = gd->ram_size; /* size in bytes */ | |
544 | ||
545 | #ifdef CONFIG_SYS_SRAM_BASE | |
546 | bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ | |
547 | bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ | |
548 | #endif | |
549 | ||
50258977 | 550 | #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) |
e4fef6cf SG |
551 | bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ |
552 | #endif | |
064b55cf | 553 | #if defined(CONFIG_M68K) |
e4fef6cf SG |
554 | bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ |
555 | #endif | |
556 | #if defined(CONFIG_MPC83xx) | |
557 | bd->bi_immrbar = CONFIG_SYS_IMMR; | |
558 | #endif | |
e4fef6cf SG |
559 | |
560 | return 0; | |
561 | } | |
fb3db635 | 562 | #endif |
e4fef6cf | 563 | |
fb3db635 | 564 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
565 | static int setup_board_part2(void) |
566 | { | |
567 | bd_t *bd = gd->bd; | |
568 | ||
569 | bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ | |
570 | bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ | |
571 | #if defined(CONFIG_CPM2) | |
572 | bd->bi_cpmfreq = gd->arch.cpm_clk; | |
573 | bd->bi_brgfreq = gd->arch.brg_clk; | |
574 | bd->bi_sccfreq = gd->arch.scc_clk; | |
575 | bd->bi_vco = gd->arch.vco_out; | |
576 | #endif /* CONFIG_CPM2 */ | |
1313db48 AW |
577 | #if defined(CONFIG_M68K) && defined(CONFIG_PCI) |
578 | bd->bi_pcifreq = gd->pci_clk; | |
579 | #endif | |
580 | #if defined(CONFIG_EXTRA_CLOCK) | |
581 | bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ | |
582 | bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ | |
583 | bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ | |
584 | #endif | |
e4fef6cf SG |
585 | |
586 | return 0; | |
587 | } | |
588 | #endif | |
589 | ||
1938f4a5 SG |
590 | #ifdef CONFIG_POST |
591 | static int init_post(void) | |
592 | { | |
593 | post_bootmode_init(); | |
594 | post_run(NULL, POST_ROM | post_bootmode_get(0)); | |
595 | ||
596 | return 0; | |
597 | } | |
598 | #endif | |
599 | ||
1938f4a5 SG |
600 | static int reloc_fdt(void) |
601 | { | |
e9acb9ea | 602 | #ifndef CONFIG_OF_EMBED |
f05ad9ba SG |
603 | if (gd->flags & GD_FLG_SKIP_RELOC) |
604 | return 0; | |
1938f4a5 SG |
605 | if (gd->new_fdt) { |
606 | memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); | |
607 | gd->fdt_blob = gd->new_fdt; | |
608 | } | |
e9acb9ea | 609 | #endif |
1938f4a5 SG |
610 | |
611 | return 0; | |
612 | } | |
613 | ||
25e7dc6a SG |
614 | static int reloc_bootstage(void) |
615 | { | |
616 | #ifdef CONFIG_BOOTSTAGE | |
617 | if (gd->flags & GD_FLG_SKIP_RELOC) | |
618 | return 0; | |
619 | if (gd->new_bootstage) { | |
620 | int size = bootstage_get_size(); | |
621 | ||
622 | debug("Copying bootstage from %p to %p, size %x\n", | |
623 | gd->bootstage, gd->new_bootstage, size); | |
624 | memcpy(gd->new_bootstage, gd->bootstage, size); | |
625 | gd->bootstage = gd->new_bootstage; | |
626 | } | |
627 | #endif | |
628 | ||
629 | return 0; | |
630 | } | |
631 | ||
1938f4a5 SG |
632 | static int setup_reloc(void) |
633 | { | |
f05ad9ba SG |
634 | if (gd->flags & GD_FLG_SKIP_RELOC) { |
635 | debug("Skipping relocation due to flag\n"); | |
636 | return 0; | |
637 | } | |
638 | ||
d54d7eb9 | 639 | #ifdef CONFIG_SYS_TEXT_BASE |
53207bfd LW |
640 | #ifdef ARM |
641 | gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; | |
642 | #elif defined(CONFIG_M68K) | |
e310b93e | 643 | /* |
644 | * On all ColdFire arch cpu, monitor code starts always | |
645 | * just after the default vector table location, so at 0x400 | |
646 | */ | |
647 | gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); | |
53207bfd LW |
648 | #else |
649 | gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; | |
e310b93e | 650 | #endif |
d54d7eb9 | 651 | #endif |
1938f4a5 SG |
652 | memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); |
653 | ||
654 | debug("Relocation Offset is: %08lx\n", gd->reloc_off); | |
a733b06b | 655 | debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", |
a0ba279a MY |
656 | gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), |
657 | gd->start_addr_sp); | |
1938f4a5 SG |
658 | |
659 | return 0; | |
660 | } | |
661 | ||
2a792753 | 662 | #ifdef CONFIG_OF_BOARD_FIXUP |
663 | static int fix_fdt(void) | |
664 | { | |
665 | return board_fix_fdt((void *)gd->fdt_blob); | |
666 | } | |
667 | #endif | |
668 | ||
1938f4a5 | 669 | /* ARM calls relocate_code from its crt0.S */ |
530f27ea SG |
670 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ |
671 | !CONFIG_IS_ENABLED(X86_64) | |
1938f4a5 SG |
672 | |
673 | static int jump_to_copy(void) | |
674 | { | |
f05ad9ba SG |
675 | if (gd->flags & GD_FLG_SKIP_RELOC) |
676 | return 0; | |
48a33806 SG |
677 | /* |
678 | * x86 is special, but in a nice way. It uses a trampoline which | |
679 | * enables the dcache if possible. | |
680 | * | |
681 | * For now, other archs use relocate_code(), which is implemented | |
682 | * similarly for all archs. When we do generic relocation, hopefully | |
683 | * we can make all archs enable the dcache prior to relocation. | |
684 | */ | |
3fb80163 | 685 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
686 | /* |
687 | * SDRAM and console are now initialised. The final stack can now | |
688 | * be setup in SDRAM. Code execution will continue in Flash, but | |
689 | * with the stack in SDRAM and Global Data in temporary memory | |
690 | * (CPU cache) | |
691 | */ | |
f0c7d9c7 | 692 | arch_setup_gd(gd->new_gd); |
48a33806 SG |
693 | board_init_f_r_trampoline(gd->start_addr_sp); |
694 | #else | |
a0ba279a | 695 | relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); |
48a33806 | 696 | #endif |
1938f4a5 SG |
697 | |
698 | return 0; | |
699 | } | |
700 | #endif | |
701 | ||
702 | /* Record the board_init_f() bootstage (after arch_cpu_init()) */ | |
b383d6c0 | 703 | static int initf_bootstage(void) |
1938f4a5 | 704 | { |
baa7d345 SG |
705 | bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) && |
706 | IS_ENABLED(CONFIG_BOOTSTAGE_STASH); | |
b383d6c0 SG |
707 | int ret; |
708 | ||
824bb1b4 | 709 | ret = bootstage_init(!from_spl); |
b383d6c0 SG |
710 | if (ret) |
711 | return ret; | |
824bb1b4 SG |
712 | if (from_spl) { |
713 | const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR, | |
714 | CONFIG_BOOTSTAGE_STASH_SIZE); | |
715 | ||
716 | ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE); | |
717 | if (ret && ret != -ENOENT) { | |
718 | debug("Failed to unstash bootstage: err=%d\n", ret); | |
719 | return ret; | |
720 | } | |
721 | } | |
b383d6c0 | 722 | |
1938f4a5 SG |
723 | bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); |
724 | ||
725 | return 0; | |
726 | } | |
727 | ||
9854a874 SG |
728 | static int initf_console_record(void) |
729 | { | |
730 | #if defined(CONFIG_CONSOLE_RECORD) && defined(CONFIG_SYS_MALLOC_F_LEN) | |
731 | return console_record_init(); | |
732 | #else | |
733 | return 0; | |
734 | #endif | |
735 | } | |
736 | ||
ab7cd627 SG |
737 | static int initf_dm(void) |
738 | { | |
739 | #if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F_LEN) | |
740 | int ret; | |
741 | ||
63c5bf48 | 742 | bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f"); |
ab7cd627 | 743 | ret = dm_init_and_scan(true); |
63c5bf48 | 744 | bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F); |
ab7cd627 SG |
745 | if (ret) |
746 | return ret; | |
747 | #endif | |
1057e6cf SG |
748 | #ifdef CONFIG_TIMER_EARLY |
749 | ret = dm_timer_init(); | |
750 | if (ret) | |
751 | return ret; | |
752 | #endif | |
ab7cd627 SG |
753 | |
754 | return 0; | |
755 | } | |
756 | ||
146251f8 SG |
757 | /* Architecture-specific memory reservation */ |
758 | __weak int reserve_arch(void) | |
759 | { | |
760 | return 0; | |
761 | } | |
762 | ||
d4c671cc SG |
763 | __weak int arch_cpu_init_dm(void) |
764 | { | |
765 | return 0; | |
766 | } | |
767 | ||
4acff452 | 768 | static const init_fnc_t init_sequence_f[] = { |
1938f4a5 | 769 | setup_mon_len, |
b45122fd | 770 | #ifdef CONFIG_OF_CONTROL |
0879361f | 771 | fdtdec_setup, |
b45122fd | 772 | #endif |
d210718d | 773 | #ifdef CONFIG_TRACE |
71c52dba | 774 | trace_early_init, |
d210718d | 775 | #endif |
768e0f52 | 776 | initf_malloc, |
5ac44a55 | 777 | initf_bootstage, /* uses its own timer, so does not need DM */ |
9854a874 | 778 | initf_console_record, |
671549e5 SG |
779 | #if defined(CONFIG_HAVE_FSP) |
780 | arch_fsp_init, | |
e4fef6cf | 781 | #endif |
1938f4a5 | 782 | arch_cpu_init, /* basic arch cpu dependent setup */ |
8ebf5069 | 783 | mach_cpu_init, /* SoC/machine dependent CPU setup */ |
3ea0953d | 784 | initf_dm, |
d4c671cc | 785 | arch_cpu_init_dm, |
1938f4a5 SG |
786 | #if defined(CONFIG_BOARD_EARLY_INIT_F) |
787 | board_early_init_f, | |
788 | #endif | |
727e94a4 | 789 | #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) |
c252c068 | 790 | /* get CPU and bus clocks according to the environment variable */ |
e4fef6cf | 791 | get_clocks, /* get CPU and bus clocks (etc.) */ |
1793e782 | 792 | #endif |
0ce45287 | 793 | #if !defined(CONFIG_M68K) |
1938f4a5 | 794 | timer_init, /* initialize timer */ |
0ce45287 | 795 | #endif |
e4fef6cf SG |
796 | #if defined(CONFIG_BOARD_POSTCLK_INIT) |
797 | board_postclk_init, | |
1938f4a5 SG |
798 | #endif |
799 | env_init, /* initialize environment */ | |
800 | init_baud_rate, /* initialze baudrate settings */ | |
801 | serial_init, /* serial communications setup */ | |
802 | console_init_f, /* stage 1 init of console */ | |
803 | display_options, /* say that we are here */ | |
804 | display_text_info, /* show debugging info if required */ | |
76d1d02f SG |
805 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH) || \ |
806 | defined(CONFIG_X86) | |
e4fef6cf SG |
807 | checkcpu, |
808 | #endif | |
cc664000 | 809 | #if defined(CONFIG_DISPLAY_CPUINFO) |
1938f4a5 | 810 | print_cpuinfo, /* display cpu info (and speed) */ |
cc664000 | 811 | #endif |
af9e6ad4 CJF |
812 | #if defined(CONFIG_DTB_RESELECT) |
813 | embedded_dtb_select, | |
814 | #endif | |
1938f4a5 | 815 | #if defined(CONFIG_DISPLAY_BOARDINFO) |
0365ffcc | 816 | show_board_info, |
e4fef6cf SG |
817 | #endif |
818 | INIT_FUNC_WATCHDOG_INIT | |
819 | #if defined(CONFIG_MISC_INIT_F) | |
820 | misc_init_f, | |
821 | #endif | |
822 | INIT_FUNC_WATCHDOG_RESET | |
69153988 | 823 | #if defined(CONFIG_SYS_I2C) |
e4fef6cf SG |
824 | init_func_i2c, |
825 | #endif | |
826 | #if defined(CONFIG_HARD_SPI) | |
827 | init_func_spi, | |
1938f4a5 SG |
828 | #endif |
829 | announce_dram_init, | |
1938f4a5 | 830 | dram_init, /* configure available RAM banks */ |
e4fef6cf SG |
831 | #ifdef CONFIG_POST |
832 | post_init_f, | |
833 | #endif | |
834 | INIT_FUNC_WATCHDOG_RESET | |
835 | #if defined(CONFIG_SYS_DRAM_TEST) | |
836 | testdram, | |
837 | #endif /* CONFIG_SYS_DRAM_TEST */ | |
838 | INIT_FUNC_WATCHDOG_RESET | |
839 | ||
1938f4a5 SG |
840 | #ifdef CONFIG_POST |
841 | init_post, | |
842 | #endif | |
e4fef6cf | 843 | INIT_FUNC_WATCHDOG_RESET |
1938f4a5 SG |
844 | /* |
845 | * Now that we have DRAM mapped and working, we can | |
846 | * relocate the code and continue running from DRAM. | |
847 | * | |
848 | * Reserve memory at end of RAM for (top down in that order): | |
849 | * - area that won't get touched by U-Boot and Linux (optional) | |
850 | * - kernel log buffer | |
851 | * - protected RAM | |
852 | * - LCD framebuffer | |
853 | * - monitor code | |
854 | * - board info struct | |
855 | */ | |
856 | setup_dest_addr, | |
b56db486 | 857 | #if defined(CONFIG_LOGBUFFER) |
1938f4a5 SG |
858 | reserve_logbuffer, |
859 | #endif | |
860 | #ifdef CONFIG_PRAM | |
861 | reserve_pram, | |
862 | #endif | |
863 | reserve_round_4k, | |
80d4bcd3 | 864 | #ifdef CONFIG_ARM |
1938f4a5 SG |
865 | reserve_mmu, |
866 | #endif | |
5a541945 | 867 | reserve_video, |
8703ef3f | 868 | reserve_trace, |
1938f4a5 SG |
869 | reserve_uboot, |
870 | reserve_malloc, | |
871 | reserve_board, | |
872 | setup_machine, | |
873 | reserve_global_data, | |
874 | reserve_fdt, | |
25e7dc6a | 875 | reserve_bootstage, |
146251f8 | 876 | reserve_arch, |
1938f4a5 | 877 | reserve_stacks, |
76b00aca | 878 | dram_init_banksize, |
1938f4a5 | 879 | show_dram_config, |
e2099d78 VZ |
880 | #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ |
881 | defined(CONFIG_SH) | |
e4fef6cf | 882 | setup_board_part1, |
fb3db635 DS |
883 | #endif |
884 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) | |
e4fef6cf SG |
885 | INIT_FUNC_WATCHDOG_RESET |
886 | setup_board_part2, | |
887 | #endif | |
1938f4a5 | 888 | display_new_sp, |
2a792753 | 889 | #ifdef CONFIG_OF_BOARD_FIXUP |
890 | fix_fdt, | |
e4fef6cf SG |
891 | #endif |
892 | INIT_FUNC_WATCHDOG_RESET | |
1938f4a5 | 893 | reloc_fdt, |
25e7dc6a | 894 | reloc_bootstage, |
1938f4a5 | 895 | setup_reloc, |
3fb80163 | 896 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
313aef37 | 897 | copy_uboot_to_ram, |
313aef37 | 898 | do_elf_reloc_fixups, |
6bda55a3 | 899 | clear_bss, |
313aef37 | 900 | #endif |
de5e5cea CZ |
901 | #if defined(CONFIG_XTENSA) |
902 | clear_bss, | |
903 | #endif | |
530f27ea SG |
904 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ |
905 | !CONFIG_IS_ENABLED(X86_64) | |
1938f4a5 SG |
906 | jump_to_copy, |
907 | #endif | |
908 | NULL, | |
909 | }; | |
910 | ||
911 | void board_init_f(ulong boot_flags) | |
912 | { | |
2a1680e3 YS |
913 | #ifdef CONFIG_SYS_GENERIC_GLOBAL_DATA |
914 | /* | |
fc0b5948 | 915 | * For some architectures, global data is initialized and used before |
2a1680e3 YS |
916 | * calling this function. The data should be preserved. For others, |
917 | * CONFIG_SYS_GENERIC_GLOBAL_DATA should be defined and use the stack | |
918 | * here to host global data until relocation. | |
919 | */ | |
1938f4a5 SG |
920 | gd_t data; |
921 | ||
922 | gd = &data; | |
923 | ||
cce6be7f DF |
924 | /* |
925 | * Clear global data before it is accessed at debug print | |
926 | * in initcall_run_list. Otherwise the debug print probably | |
fc0b5948 | 927 | * get the wrong value of gd->have_console. |
cce6be7f | 928 | */ |
cce6be7f DF |
929 | zero_global_data(); |
930 | #endif | |
931 | ||
1938f4a5 | 932 | gd->flags = boot_flags; |
9aed5a27 | 933 | gd->have_console = 0; |
1938f4a5 SG |
934 | |
935 | if (initcall_run_list(init_sequence_f)) | |
936 | hang(); | |
937 | ||
9b217498 | 938 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ |
530f27ea | 939 | !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) |
1938f4a5 SG |
940 | /* NOTREACHED - jump_to_copy() does not return */ |
941 | hang(); | |
942 | #endif | |
943 | } | |
944 | ||
3fb80163 | 945 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
946 | /* |
947 | * For now this code is only used on x86. | |
948 | * | |
949 | * init_sequence_f_r is the list of init functions which are run when | |
950 | * U-Boot is executing from Flash with a semi-limited 'C' environment. | |
951 | * The following limitations must be considered when implementing an | |
952 | * '_f_r' function: | |
953 | * - 'static' variables are read-only | |
954 | * - Global Data (gd->xxx) is read/write | |
955 | * | |
956 | * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if | |
957 | * supported). It _should_, if possible, copy global data to RAM and | |
958 | * initialise the CPU caches (to speed up the relocation process) | |
959 | * | |
960 | * NOTE: At present only x86 uses this route, but it is intended that | |
961 | * all archs will move to this when generic relocation is implemented. | |
962 | */ | |
4acff452 | 963 | static const init_fnc_t init_sequence_f_r[] = { |
530f27ea | 964 | #if !CONFIG_IS_ENABLED(X86_64) |
48a33806 | 965 | init_cache_f_r, |
530f27ea | 966 | #endif |
48a33806 SG |
967 | |
968 | NULL, | |
969 | }; | |
970 | ||
971 | void board_init_f_r(void) | |
972 | { | |
973 | if (initcall_run_list(init_sequence_f_r)) | |
974 | hang(); | |
975 | ||
e4d6ab0c SG |
976 | /* |
977 | * The pre-relocation drivers may be using memory that has now gone | |
978 | * away. Mark serial as unavailable - this will fall back to the debug | |
979 | * UART if available. | |
980 | */ | |
981 | gd->flags &= ~GD_FLG_SERIAL_READY; | |
982 | ||
48a33806 SG |
983 | /* |
984 | * U-Boot has been copied into SDRAM, the BSS has been cleared etc. | |
985 | * Transfer execution from Flash to RAM by calculating the address | |
986 | * of the in-RAM copy of board_init_r() and calling it | |
987 | */ | |
7bf9f20d | 988 | (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); |
48a33806 SG |
989 | |
990 | /* NOTREACHED - board_init_r() does not return */ | |
991 | hang(); | |
992 | } | |
5bcd19aa | 993 | #endif /* CONFIG_X86 */ |