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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
1938f4a5 SG |
2 | /* |
3 | * Copyright (c) 2011 The Chromium OS Authors. | |
4 | * (C) Copyright 2002-2006 | |
5 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
6 | * | |
7 | * (C) Copyright 2002 | |
8 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
9 | * Marius Groeger <mgroeger@sysgo.de> | |
1938f4a5 SG |
10 | */ |
11 | ||
12 | #include <common.h> | |
f0293d33 | 13 | #include <bloblist.h> |
52f24238 | 14 | #include <bootstage.h> |
d96c2604 | 15 | #include <clock_legacy.h> |
24b852a7 | 16 | #include <console.h> |
5d6c61ac | 17 | #include <cpu.h> |
30c7c434 | 18 | #include <cpu_func.h> |
70545642 | 19 | #include <cyclic.h> |
4e4bf944 | 20 | #include <display_options.h> |
ab7cd627 | 21 | #include <dm.h> |
4bfd1f5d | 22 | #include <env.h> |
f3998fdc | 23 | #include <env_internal.h> |
5a421904 | 24 | #include <event.h> |
1938f4a5 | 25 | #include <fdtdec.h> |
f828bf25 | 26 | #include <fs.h> |
db41d65a | 27 | #include <hang.h> |
e4fef6cf | 28 | #include <i2c.h> |
67c4e9f8 | 29 | #include <init.h> |
1938f4a5 | 30 | #include <initcall.h> |
f7ae49fc | 31 | #include <log.h> |
fb5cf7f1 | 32 | #include <malloc.h> |
0eb25b61 | 33 | #include <mapmem.h> |
a733b06b | 34 | #include <os.h> |
1938f4a5 | 35 | #include <post.h> |
e47b2d67 | 36 | #include <relocate.h> |
b03e0510 | 37 | #include <serial.h> |
b0edea3c | 38 | #include <spl.h> |
c5d4001a | 39 | #include <status_led.h> |
23471aed | 40 | #include <sysreset.h> |
1057e6cf | 41 | #include <timer.h> |
71c52dba | 42 | #include <trace.h> |
5a541945 | 43 | #include <video.h> |
e4fef6cf | 44 | #include <watchdog.h> |
90526e9f | 45 | #include <asm/cache.h> |
401d1c4f | 46 | #include <asm/global_data.h> |
1938f4a5 SG |
47 | #include <asm/io.h> |
48 | #include <asm/sections.h> | |
ab7cd627 | 49 | #include <dm/root.h> |
056285fd | 50 | #include <linux/errno.h> |
236f7396 | 51 | #include <linux/log2.h> |
1938f4a5 | 52 | |
1938f4a5 | 53 | DECLARE_GLOBAL_DATA_PTR; |
1938f4a5 SG |
54 | |
55 | /* | |
4c509343 | 56 | * TODO(sjg@chromium.org): IMO this code should be |
1938f4a5 SG |
57 | * refactored to a single function, something like: |
58 | * | |
59 | * void led_set_state(enum led_colour_t colour, int on); | |
60 | */ | |
61 | /************************************************************************ | |
62 | * Coloured LED functionality | |
63 | ************************************************************************ | |
64 | * May be supplied by boards if desired | |
65 | */ | |
c5d4001a JH |
66 | __weak void coloured_LED_init(void) {} |
67 | __weak void red_led_on(void) {} | |
68 | __weak void red_led_off(void) {} | |
69 | __weak void green_led_on(void) {} | |
70 | __weak void green_led_off(void) {} | |
71 | __weak void yellow_led_on(void) {} | |
72 | __weak void yellow_led_off(void) {} | |
73 | __weak void blue_led_on(void) {} | |
74 | __weak void blue_led_off(void) {} | |
1938f4a5 SG |
75 | |
76 | /* | |
77 | * Why is gd allocated a register? Prior to reloc it might be better to | |
78 | * just pass it around to each function in this file? | |
79 | * | |
80 | * After reloc one could argue that it is hardly used and doesn't need | |
81 | * to be in a register. Or if it is it should perhaps hold pointers to all | |
82 | * global data for all modules, so that post-reloc we can avoid the massive | |
83 | * literal pool we get on ARM. Or perhaps just encourage each module to use | |
84 | * a structure... | |
85 | */ | |
86 | ||
d54d7eb9 | 87 | #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) |
e4fef6cf SG |
88 | static int init_func_watchdog_init(void) |
89 | { | |
ea3310e8 TR |
90 | # if defined(CONFIG_HW_WATCHDOG) && \ |
91 | (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ | |
1473f6ac | 92 | defined(CONFIG_SH) || \ |
46d7a3b3 | 93 | defined(CONFIG_DESIGNWARE_WATCHDOG) || \ |
14a380a8 | 94 | defined(CONFIG_IMX_WATCHDOG)) |
d54d7eb9 | 95 | hw_watchdog_init(); |
e4fef6cf | 96 | puts(" Watchdog enabled\n"); |
ba169d98 | 97 | # endif |
29caf930 | 98 | schedule(); |
e4fef6cf SG |
99 | |
100 | return 0; | |
101 | } | |
102 | ||
103 | int init_func_watchdog_reset(void) | |
104 | { | |
29caf930 | 105 | schedule(); |
e4fef6cf SG |
106 | |
107 | return 0; | |
108 | } | |
109 | #endif /* CONFIG_WATCHDOG */ | |
110 | ||
dd2a6cd0 | 111 | __weak void board_add_ram_info(int use_default) |
e4fef6cf SG |
112 | { |
113 | /* please define platform specific board_add_ram_info() */ | |
114 | } | |
115 | ||
1938f4a5 SG |
116 | static int init_baud_rate(void) |
117 | { | |
bfebc8c9 | 118 | gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE); |
1938f4a5 SG |
119 | return 0; |
120 | } | |
121 | ||
122 | static int display_text_info(void) | |
123 | { | |
9b217498 | 124 | #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) |
9fdee7d7 | 125 | ulong bss_start, bss_end, text_base; |
1938f4a5 | 126 | |
ccea96f4 SY |
127 | bss_start = (ulong)__bss_start; |
128 | bss_end = (ulong)__bss_end; | |
b60eff31 | 129 | |
98463903 SG |
130 | #ifdef CONFIG_TEXT_BASE |
131 | text_base = CONFIG_TEXT_BASE; | |
d54d7eb9 | 132 | #else |
9fdee7d7 | 133 | text_base = CONFIG_SYS_MONITOR_BASE; |
d54d7eb9 | 134 | #endif |
9fdee7d7 DS |
135 | |
136 | debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", | |
16ef1474 | 137 | text_base, bss_start, bss_end); |
a733b06b | 138 | #endif |
1938f4a5 | 139 | |
1938f4a5 SG |
140 | return 0; |
141 | } | |
142 | ||
23471aed MS |
143 | #ifdef CONFIG_SYSRESET |
144 | static int print_resetinfo(void) | |
145 | { | |
146 | struct udevice *dev; | |
147 | char status[256]; | |
9259bd17 | 148 | bool status_printed = false; |
23471aed MS |
149 | int ret; |
150 | ||
d8cb1dc9 BM |
151 | /* |
152 | * Not all boards have sysreset drivers available during early | |
9259bd17 MS |
153 | * boot, so don't fail if one can't be found. |
154 | */ | |
155 | for (ret = uclass_first_device_check(UCLASS_SYSRESET, &dev); dev; | |
d8cb1dc9 | 156 | ret = uclass_next_device_check(&dev)) { |
9259bd17 MS |
157 | if (ret) { |
158 | debug("%s: %s sysreset device (error: %d)\n", | |
159 | __func__, dev->name, ret); | |
160 | continue; | |
161 | } | |
162 | ||
163 | if (!sysreset_get_status(dev, status, sizeof(status))) { | |
164 | printf("%s%s", status_printed ? " " : "", status); | |
165 | status_printed = true; | |
166 | } | |
23471aed | 167 | } |
9259bd17 MS |
168 | if (status_printed) |
169 | printf("\n"); | |
23471aed MS |
170 | |
171 | return 0; | |
172 | } | |
173 | #endif | |
174 | ||
5d6c61ac MS |
175 | #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU) |
176 | static int print_cpuinfo(void) | |
177 | { | |
178 | struct udevice *dev; | |
179 | char desc[512]; | |
180 | int ret; | |
181 | ||
f5b66af2 YL |
182 | dev = cpu_get_current_dev(); |
183 | if (!dev) { | |
184 | debug("%s: Could not get CPU device\n", | |
185 | __func__); | |
186 | return -ENODEV; | |
5d6c61ac MS |
187 | } |
188 | ||
189 | ret = cpu_get_desc(dev, desc, sizeof(desc)); | |
190 | if (ret) { | |
191 | debug("%s: Could not get CPU description (err = %d)\n", | |
192 | dev->name, ret); | |
193 | return ret; | |
194 | } | |
195 | ||
ecfe6633 | 196 | printf("CPU: %s\n", desc); |
5d6c61ac MS |
197 | |
198 | return 0; | |
199 | } | |
200 | #endif | |
201 | ||
1938f4a5 SG |
202 | static int announce_dram_init(void) |
203 | { | |
204 | puts("DRAM: "); | |
205 | return 0; | |
206 | } | |
207 | ||
236f7396 T |
208 | /* |
209 | * From input size calculate its nearest rounded unit scale (multiply of 2^10) | |
210 | * and value in calculated unit scale multiplied by 10 (as fractional fixed | |
211 | * point number with one decimal digit), which is human natural format, | |
212 | * same what uses print_size() function for displaying. Mathematically it is: | |
213 | * round_nearest(val * 2^scale) = size * 10; where: 10 <= val < 10240. | |
214 | * | |
215 | * For example for size=87654321 we calculate scale=20 and val=836 which means | |
216 | * that input has natural human format 83.6 M (mega = 2^20). | |
217 | */ | |
218 | #define compute_size_scale_val(size, scale, val) do { \ | |
219 | scale = ilog2(size) / 10 * 10; \ | |
220 | val = (10 * size + ((1ULL << scale) >> 1)) >> scale; \ | |
221 | if (val == 10240) { val = 10; scale += 10; } \ | |
222 | } while (0) | |
223 | ||
224 | /* | |
225 | * Check if the sizes in their natural units written in decimal format with | |
226 | * one fraction number are same. | |
227 | */ | |
228 | static int sizes_near(unsigned long long size1, unsigned long long size2) | |
229 | { | |
230 | unsigned int size1_scale, size1_val, size2_scale, size2_val; | |
231 | ||
232 | compute_size_scale_val(size1, size1_scale, size1_val); | |
233 | compute_size_scale_val(size2, size2_scale, size2_val); | |
234 | ||
235 | return size1_scale == size2_scale && size1_val == size2_val; | |
236 | } | |
237 | ||
1938f4a5 SG |
238 | static int show_dram_config(void) |
239 | { | |
fa39ffe5 | 240 | unsigned long long size; |
1938f4a5 SG |
241 | int i; |
242 | ||
243 | debug("\nRAM Configuration:\n"); | |
244 | for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
245 | size += gd->bd->bi_dram[i].size; | |
715f599f BM |
246 | debug("Bank #%d: %llx ", i, |
247 | (unsigned long long)(gd->bd->bi_dram[i].start)); | |
1938f4a5 SG |
248 | #ifdef DEBUG |
249 | print_size(gd->bd->bi_dram[i].size, "\n"); | |
250 | #endif | |
251 | } | |
252 | debug("\nDRAM: "); | |
1938f4a5 | 253 | |
236f7396 T |
254 | print_size(gd->ram_size, ""); |
255 | if (!sizes_near(gd->ram_size, size)) { | |
256 | printf(" (effective "); | |
257 | print_size(size, ")"); | |
258 | } | |
e4fef6cf SG |
259 | board_add_ram_info(0); |
260 | putc('\n'); | |
1938f4a5 SG |
261 | |
262 | return 0; | |
263 | } | |
264 | ||
76b00aca | 265 | __weak int dram_init_banksize(void) |
1938f4a5 | 266 | { |
f120aa75 | 267 | gd->bd->bi_dram[0].start = gd->ram_base; |
1938f4a5 | 268 | gd->bd->bi_dram[0].size = get_effective_memsize(); |
76b00aca SG |
269 | |
270 | return 0; | |
1938f4a5 SG |
271 | } |
272 | ||
55dabcc8 | 273 | #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) |
e4fef6cf SG |
274 | static int init_func_i2c(void) |
275 | { | |
276 | puts("I2C: "); | |
815a76f2 | 277 | i2c_init_all(); |
e4fef6cf SG |
278 | puts("ready\n"); |
279 | return 0; | |
280 | } | |
281 | #endif | |
282 | ||
1938f4a5 SG |
283 | static int setup_mon_len(void) |
284 | { | |
d819250c SB |
285 | #if defined(CONFIG_ARCH_NEXELL) |
286 | gd->mon_len = (ulong)__bss_end - (ulong)__image_copy_start; | |
287 | #elif defined(__ARM__) || defined(__MICROBLAZE__) | |
ccea96f4 | 288 | gd->mon_len = (ulong)__bss_end - (ulong)_start; |
2c88d5e1 | 289 | #elif defined(CONFIG_SANDBOX) && !defined(__riscv) |
ccea96f4 | 290 | gd->mon_len = (ulong)_end - (ulong)_init; |
3c9fc23c | 291 | #elif defined(CONFIG_SANDBOX) |
2c88d5e1 | 292 | /* gcc does not provide _init in crti.o on RISC-V */ |
3c9fc23c HS |
293 | gd->mon_len = 0; |
294 | #elif defined(CONFIG_EFI_APP) | |
ccea96f4 | 295 | gd->mon_len = (ulong)_end - (ulong)_init; |
ea3310e8 | 296 | #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) |
d54d7eb9 | 297 | gd->mon_len = CONFIG_SYS_MONITOR_LEN; |
11232139 | 298 | #elif defined(CONFIG_SH) || defined(CONFIG_RISCV) |
ccea96f4 | 299 | gd->mon_len = (ulong)(__bss_end) - (ulong)(_start); |
b0b35953 | 300 | #elif defined(CONFIG_SYS_MONITOR_BASE) |
ccea96f4 SY |
301 | /* TODO: use (ulong)__bss_end - (ulong)__text_start; ? */ |
302 | gd->mon_len = (ulong)__bss_end - CONFIG_SYS_MONITOR_BASE; | |
632efa74 | 303 | #endif |
1938f4a5 SG |
304 | return 0; |
305 | } | |
306 | ||
b0edea3c SG |
307 | static int setup_spl_handoff(void) |
308 | { | |
309 | #if CONFIG_IS_ENABLED(HANDOFF) | |
7f3b79af | 310 | gd->spl_handoff = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, |
b0edea3c SG |
311 | sizeof(struct spl_handoff)); |
312 | debug("Found SPL hand-off info %p\n", gd->spl_handoff); | |
313 | #endif | |
314 | ||
315 | return 0; | |
316 | } | |
317 | ||
1938f4a5 SG |
318 | __weak int arch_cpu_init(void) |
319 | { | |
320 | return 0; | |
321 | } | |
322 | ||
8ebf5069 PB |
323 | __weak int mach_cpu_init(void) |
324 | { | |
325 | return 0; | |
326 | } | |
327 | ||
1938f4a5 | 328 | /* Get the top of usable RAM */ |
d768dd88 | 329 | __weak phys_addr_t board_get_usable_ram_top(phys_size_t total_size) |
1938f4a5 | 330 | { |
aa6e94de | 331 | #if defined(CFG_SYS_SDRAM_BASE) && CFG_SYS_SDRAM_BASE > 0 |
1e4d11a5 | 332 | /* |
4c509343 | 333 | * Detect whether we have so much RAM that it goes past the end of our |
1e4d11a5 SW |
334 | * 32-bit address space. If so, clip the usable RAM so it doesn't. |
335 | */ | |
aa6e94de | 336 | if (gd->ram_top < CFG_SYS_SDRAM_BASE) |
1e4d11a5 SW |
337 | /* |
338 | * Will wrap back to top of 32-bit space when reservations | |
339 | * are made. | |
340 | */ | |
341 | return 0; | |
342 | #endif | |
1938f4a5 SG |
343 | return gd->ram_top; |
344 | } | |
345 | ||
d63fc994 OP |
346 | __weak int arch_setup_dest_addr(void) |
347 | { | |
348 | return 0; | |
349 | } | |
350 | ||
1938f4a5 SG |
351 | static int setup_dest_addr(void) |
352 | { | |
353 | debug("Monitor len: %08lX\n", gd->mon_len); | |
354 | /* | |
355 | * Ram is setup, size stored in gd !! | |
356 | */ | |
d92aee57 | 357 | debug("Ram size: %08llX\n", (unsigned long long)gd->ram_size); |
24c904f3 | 358 | #if CONFIG_VAL(SYS_MEM_TOP_HIDE) |
1938f4a5 SG |
359 | /* |
360 | * Subtract specified amount of memory to hide so that it won't | |
361 | * get "touched" at all by U-Boot. By fixing up gd->ram_size | |
362 | * the Linux kernel should now get passed the now "corrected" | |
36cc0de0 YS |
363 | * memory size and won't touch it either. This should work |
364 | * for arch/ppc and arch/powerpc. Only Linux board ports in | |
365 | * arch/powerpc with bootwrapper support, that recalculate the | |
366 | * memory size from the SDRAM controller setup will have to | |
367 | * get fixed. | |
1938f4a5 | 368 | */ |
36cc0de0 YS |
369 | gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; |
370 | #endif | |
aa6e94de TR |
371 | #ifdef CFG_SYS_SDRAM_BASE |
372 | gd->ram_base = CFG_SYS_SDRAM_BASE; | |
1938f4a5 | 373 | #endif |
1473b12a | 374 | gd->ram_top = gd->ram_base + get_effective_memsize(); |
1938f4a5 | 375 | gd->ram_top = board_get_usable_ram_top(gd->mon_len); |
a0ba279a | 376 | gd->relocaddr = gd->ram_top; |
d92aee57 | 377 | debug("Ram top: %08llX\n", (unsigned long long)gd->ram_top); |
d63fc994 OP |
378 | |
379 | return arch_setup_dest_addr(); | |
1938f4a5 SG |
380 | } |
381 | ||
7c5c137c | 382 | #ifdef CFG_PRAM |
1938f4a5 SG |
383 | /* reserve protected RAM */ |
384 | static int reserve_pram(void) | |
385 | { | |
386 | ulong reg; | |
387 | ||
7c5c137c | 388 | reg = env_get_ulong("pram", 10, CFG_PRAM); |
a0ba279a | 389 | gd->relocaddr -= (reg << 10); /* size is in kB */ |
1938f4a5 | 390 | debug("Reserving %ldk for protected RAM at %08lx\n", reg, |
a0ba279a | 391 | gd->relocaddr); |
1938f4a5 SG |
392 | return 0; |
393 | } | |
7c5c137c | 394 | #endif /* CFG_PRAM */ |
1938f4a5 SG |
395 | |
396 | /* Round memory pointer down to next 4 kB limit */ | |
397 | static int reserve_round_4k(void) | |
398 | { | |
a0ba279a | 399 | gd->relocaddr &= ~(4096 - 1); |
1938f4a5 SG |
400 | return 0; |
401 | } | |
402 | ||
79926e4f OP |
403 | __weak int arch_reserve_mmu(void) |
404 | { | |
405 | return 0; | |
406 | } | |
407 | ||
4ef9c772 | 408 | static int reserve_video_from_videoblob(void) |
5a541945 | 409 | { |
b7080bfc | 410 | if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && spl_phase() > PHASE_SPL) { |
5bc610a7 | 411 | struct video_handoff *ho; |
eefe23c1 | 412 | int ret = 0; |
5bc610a7 NJ |
413 | |
414 | ho = bloblist_find(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho)); | |
415 | if (!ho) | |
eefe23c1 DT |
416 | return log_msg_ret("Missing video bloblist", -ENOENT); |
417 | ||
418 | ret = video_reserve_from_bloblist(ho); | |
419 | if (ret) | |
420 | return log_msg_ret("Invalid Video handoff info", ret); | |
4ef9c772 DT |
421 | |
422 | /* Sanity check fb from blob is before current relocaddr */ | |
423 | if (likely(gd->relocaddr > (unsigned long)ho->fb)) | |
424 | gd->relocaddr = ho->fb; | |
425 | } | |
426 | ||
427 | return 0; | |
428 | } | |
429 | ||
430 | /* | |
431 | * Check if any bloblist received specifying reserved areas from previous stage and adjust | |
432 | * gd->relocaddr accordingly, so that we start reserving after pre-reserved areas | |
433 | * from previous stage. | |
434 | * | |
435 | * NOTE: | |
436 | * IT is recommended that all bloblists from previous stage are reserved from ram_top | |
437 | * as next stage will simply start reserving further regions after them. | |
438 | */ | |
439 | static int setup_relocaddr_from_bloblist(void) | |
440 | { | |
441 | reserve_video_from_videoblob(); | |
442 | ||
443 | return 0; | |
444 | } | |
445 | ||
446 | static int reserve_video(void) | |
447 | { | |
448 | if (CONFIG_IS_ENABLED(VIDEO)) { | |
f9b7bd7e SG |
449 | ulong addr; |
450 | int ret; | |
451 | ||
452 | addr = gd->relocaddr; | |
453 | ret = video_reserve(&addr); | |
454 | if (ret) | |
455 | return ret; | |
456 | debug("Reserving %luk for video at: %08lx\n", | |
457 | ((unsigned long)gd->relocaddr - addr) >> 10, addr); | |
458 | gd->relocaddr = addr; | |
459 | } | |
e4fef6cf SG |
460 | |
461 | return 0; | |
462 | } | |
e4fef6cf | 463 | |
8703ef3f SG |
464 | static int reserve_trace(void) |
465 | { | |
466 | #ifdef CONFIG_TRACE | |
467 | gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; | |
468 | gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); | |
7ea33579 HS |
469 | debug("Reserving %luk for trace data at: %08lx\n", |
470 | (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); | |
8703ef3f SG |
471 | #endif |
472 | ||
473 | return 0; | |
474 | } | |
475 | ||
1938f4a5 SG |
476 | static int reserve_uboot(void) |
477 | { | |
ff2b2ba8 AB |
478 | if (!(gd->flags & GD_FLG_SKIP_RELOC)) { |
479 | /* | |
480 | * reserve memory for U-Boot code, data & bss | |
481 | * round down to next 4 kB limit | |
482 | */ | |
483 | gd->relocaddr -= gd->mon_len; | |
484 | gd->relocaddr &= ~(4096 - 1); | |
485 | #if defined(CONFIG_E500) || defined(CONFIG_MIPS) | |
486 | /* round down to next 64 kB limit so that IVPR stays aligned */ | |
487 | gd->relocaddr &= ~(65536 - 1); | |
488 | #endif | |
489 | ||
490 | debug("Reserving %ldk for U-Boot at: %08lx\n", | |
491 | gd->mon_len >> 10, gd->relocaddr); | |
492 | } | |
a0ba279a MY |
493 | |
494 | gd->start_addr_sp = gd->relocaddr; | |
495 | ||
1938f4a5 SG |
496 | return 0; |
497 | } | |
498 | ||
65c141eb PD |
499 | /* |
500 | * reserve after start_addr_sp the requested size and make the stack pointer | |
501 | * 16-byte aligned, this alignment is needed for cast on the reserved memory | |
502 | * ref = x86_64 ABI: https://reviews.llvm.org/D30049: 16 bytes | |
503 | * = ARMv8 Instruction Set Overview: quad word, 16 bytes | |
504 | */ | |
505 | static unsigned long reserve_stack_aligned(size_t size) | |
506 | { | |
507 | return ALIGN_DOWN(gd->start_addr_sp - size, 16); | |
508 | } | |
509 | ||
5f7adb5b VM |
510 | #ifdef CONFIG_SYS_NONCACHED_MEMORY |
511 | static int reserve_noncached(void) | |
512 | { | |
5e0404ff SW |
513 | /* |
514 | * The value of gd->start_addr_sp must match the value of malloc_start | |
02f5a014 TR |
515 | * calculated in board_r.c:initr_malloc(), which is passed to |
516 | * dlmalloc.c:mem_malloc_init() and then used by | |
5e0404ff SW |
517 | * cache.c:noncached_init() |
518 | * | |
519 | * These calculations must match the code in cache.c:noncached_init() | |
520 | */ | |
521 | gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) - | |
522 | MMU_SECTION_SIZE; | |
523 | gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY, | |
524 | MMU_SECTION_SIZE); | |
5f7adb5b VM |
525 | debug("Reserving %dM for noncached_alloc() at: %08lx\n", |
526 | CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp); | |
527 | ||
528 | return 0; | |
529 | } | |
530 | #endif | |
531 | ||
1938f4a5 SG |
532 | /* reserve memory for malloc() area */ |
533 | static int reserve_malloc(void) | |
534 | { | |
65c141eb | 535 | gd->start_addr_sp = reserve_stack_aligned(TOTAL_MALLOC_LEN); |
1938f4a5 | 536 | debug("Reserving %dk for malloc() at: %08lx\n", |
16ef1474 | 537 | TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); |
5f7adb5b VM |
538 | #ifdef CONFIG_SYS_NONCACHED_MEMORY |
539 | reserve_noncached(); | |
540 | #endif | |
541 | ||
1938f4a5 SG |
542 | return 0; |
543 | } | |
544 | ||
545 | /* (permanently) allocate a Board Info struct */ | |
546 | static int reserve_board(void) | |
547 | { | |
d54d7eb9 | 548 | if (!gd->bd) { |
b75d8dc5 MY |
549 | gd->start_addr_sp = reserve_stack_aligned(sizeof(struct bd_info)); |
550 | gd->bd = (struct bd_info *)map_sysmem(gd->start_addr_sp, | |
551 | sizeof(struct bd_info)); | |
552 | memset(gd->bd, '\0', sizeof(struct bd_info)); | |
d54d7eb9 | 553 | debug("Reserving %zu Bytes for Board Info at: %08lx\n", |
b75d8dc5 | 554 | sizeof(struct bd_info), gd->start_addr_sp); |
d54d7eb9 | 555 | } |
1938f4a5 SG |
556 | return 0; |
557 | } | |
558 | ||
1938f4a5 SG |
559 | static int reserve_global_data(void) |
560 | { | |
65c141eb | 561 | gd->start_addr_sp = reserve_stack_aligned(sizeof(gd_t)); |
a0ba279a | 562 | gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); |
1938f4a5 | 563 | debug("Reserving %zu Bytes for Global Data at: %08lx\n", |
16ef1474 | 564 | sizeof(gd_t), gd->start_addr_sp); |
1938f4a5 SG |
565 | return 0; |
566 | } | |
567 | ||
568 | static int reserve_fdt(void) | |
569 | { | |
19b18daa OP |
570 | if (!IS_ENABLED(CONFIG_OF_EMBED)) { |
571 | /* | |
572 | * If the device tree is sitting immediately above our image | |
573 | * then we must relocate it. If it is embedded in the data | |
574 | * section, then it will be relocated with other data. | |
575 | */ | |
576 | if (gd->fdt_blob) { | |
577 | gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob), 32); | |
578 | ||
579 | gd->start_addr_sp = reserve_stack_aligned(gd->fdt_size); | |
580 | gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); | |
581 | debug("Reserving %lu Bytes for FDT at: %08lx\n", | |
582 | gd->fdt_size, gd->start_addr_sp); | |
583 | } | |
1938f4a5 SG |
584 | } |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
25e7dc6a SG |
589 | static int reserve_bootstage(void) |
590 | { | |
591 | #ifdef CONFIG_BOOTSTAGE | |
592 | int size = bootstage_get_size(); | |
593 | ||
65c141eb | 594 | gd->start_addr_sp = reserve_stack_aligned(size); |
25e7dc6a SG |
595 | gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); |
596 | debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, | |
597 | gd->start_addr_sp); | |
598 | #endif | |
599 | ||
600 | return 0; | |
601 | } | |
602 | ||
d6f87712 | 603 | __weak int arch_reserve_stacks(void) |
1938f4a5 | 604 | { |
68145d4c AB |
605 | return 0; |
606 | } | |
8cae8a68 | 607 | |
68145d4c AB |
608 | static int reserve_stacks(void) |
609 | { | |
610 | /* make stack pointer 16-byte aligned */ | |
65c141eb | 611 | gd->start_addr_sp = reserve_stack_aligned(16); |
1938f4a5 SG |
612 | |
613 | /* | |
4c509343 | 614 | * let the architecture-specific code tailor gd->start_addr_sp and |
68145d4c | 615 | * gd->irq_sp |
1938f4a5 | 616 | */ |
68145d4c | 617 | return arch_reserve_stacks(); |
1938f4a5 SG |
618 | } |
619 | ||
f0293d33 SG |
620 | static int reserve_bloblist(void) |
621 | { | |
622 | #ifdef CONFIG_BLOBLIST | |
4a08fae1 | 623 | /* Align to a 4KB boundary for easier reading of addresses */ |
9fe06464 SG |
624 | gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp - |
625 | CONFIG_BLOBLIST_SIZE_RELOC, 0x1000); | |
626 | gd->new_bloblist = map_sysmem(gd->start_addr_sp, | |
627 | CONFIG_BLOBLIST_SIZE_RELOC); | |
f0293d33 SG |
628 | #endif |
629 | ||
630 | return 0; | |
631 | } | |
632 | ||
1938f4a5 SG |
633 | static int display_new_sp(void) |
634 | { | |
a0ba279a | 635 | debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); |
1938f4a5 SG |
636 | |
637 | return 0; | |
638 | } | |
639 | ||
81e7cb1e | 640 | __weak int arch_setup_bdinfo(void) |
ba743103 OP |
641 | { |
642 | return 0; | |
643 | } | |
644 | ||
81e7cb1e OP |
645 | int setup_bdinfo(void) |
646 | { | |
a4aa1889 OP |
647 | struct bd_info *bd = gd->bd; |
648 | ||
49122242 OP |
649 | if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) { |
650 | bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ | |
651 | bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ | |
652 | } | |
653 | ||
81e7cb1e OP |
654 | return arch_setup_bdinfo(); |
655 | } | |
656 | ||
1938f4a5 SG |
657 | #ifdef CONFIG_POST |
658 | static int init_post(void) | |
659 | { | |
660 | post_bootmode_init(); | |
661 | post_run(NULL, POST_ROM | post_bootmode_get(0)); | |
662 | ||
663 | return 0; | |
664 | } | |
665 | #endif | |
666 | ||
1938f4a5 SG |
667 | static int reloc_fdt(void) |
668 | { | |
19b18daa | 669 | if (!IS_ENABLED(CONFIG_OF_EMBED)) { |
19b18daa OP |
670 | if (gd->new_fdt) { |
671 | memcpy(gd->new_fdt, gd->fdt_blob, | |
672 | fdt_totalsize(gd->fdt_blob)); | |
673 | gd->fdt_blob = gd->new_fdt; | |
674 | } | |
1938f4a5 SG |
675 | } |
676 | ||
677 | return 0; | |
678 | } | |
679 | ||
25e7dc6a SG |
680 | static int reloc_bootstage(void) |
681 | { | |
682 | #ifdef CONFIG_BOOTSTAGE | |
683 | if (gd->flags & GD_FLG_SKIP_RELOC) | |
684 | return 0; | |
685 | if (gd->new_bootstage) { | |
686 | int size = bootstage_get_size(); | |
687 | ||
688 | debug("Copying bootstage from %p to %p, size %x\n", | |
689 | gd->bootstage, gd->new_bootstage, size); | |
690 | memcpy(gd->new_bootstage, gd->bootstage, size); | |
691 | gd->bootstage = gd->new_bootstage; | |
ac9cd480 | 692 | bootstage_relocate(); |
25e7dc6a SG |
693 | } |
694 | #endif | |
695 | ||
696 | return 0; | |
697 | } | |
698 | ||
f0293d33 SG |
699 | static int reloc_bloblist(void) |
700 | { | |
701 | #ifdef CONFIG_BLOBLIST | |
d5b6e91b SG |
702 | /* |
703 | * Relocate only if we are supposed to send it | |
704 | */ | |
705 | if ((gd->flags & GD_FLG_SKIP_RELOC) && | |
706 | CONFIG_BLOBLIST_SIZE == CONFIG_BLOBLIST_SIZE_RELOC) { | |
707 | debug("Not relocating bloblist\n"); | |
f0293d33 | 708 | return 0; |
d5b6e91b | 709 | } |
f0293d33 | 710 | if (gd->new_bloblist) { |
f0293d33 | 711 | debug("Copying bloblist from %p to %p, size %x\n", |
1ef43f3b RM |
712 | gd->bloblist, gd->new_bloblist, gd->bloblist->total_size); |
713 | return bloblist_reloc(gd->new_bloblist, | |
714 | CONFIG_BLOBLIST_SIZE_RELOC); | |
f0293d33 SG |
715 | } |
716 | #endif | |
717 | ||
718 | return 0; | |
719 | } | |
720 | ||
1938f4a5 SG |
721 | static int setup_reloc(void) |
722 | { | |
47d7d036 | 723 | if (!(gd->flags & GD_FLG_SKIP_RELOC)) { |
98463903 | 724 | #ifdef CONFIG_TEXT_BASE |
53207bfd | 725 | #ifdef ARM |
47d7d036 | 726 | gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; |
d58c0074 MS |
727 | #elif defined(CONFIG_MICROBLAZE) |
728 | gd->reloc_off = gd->relocaddr - (u32)_start; | |
53207bfd | 729 | #elif defined(CONFIG_M68K) |
47d7d036 MV |
730 | /* |
731 | * On all ColdFire arch cpu, monitor code starts always | |
732 | * just after the default vector table location, so at 0x400 | |
733 | */ | |
98463903 | 734 | gd->reloc_off = gd->relocaddr - (CONFIG_TEXT_BASE + 0x400); |
001d1885 | 735 | #elif !defined(CONFIG_SANDBOX) |
98463903 | 736 | gd->reloc_off = gd->relocaddr - CONFIG_TEXT_BASE; |
e310b93e | 737 | #endif |
d54d7eb9 | 738 | #endif |
47d7d036 MV |
739 | } |
740 | ||
1938f4a5 SG |
741 | memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); |
742 | ||
47d7d036 MV |
743 | if (gd->flags & GD_FLG_SKIP_RELOC) { |
744 | debug("Skipping relocation due to flag\n"); | |
745 | } else { | |
746 | debug("Relocation Offset is: %08lx\n", gd->reloc_off); | |
747 | debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", | |
748 | gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), | |
749 | gd->start_addr_sp); | |
750 | } | |
1938f4a5 SG |
751 | |
752 | return 0; | |
753 | } | |
754 | ||
2a792753 | 755 | #ifdef CONFIG_OF_BOARD_FIXUP |
756 | static int fix_fdt(void) | |
757 | { | |
758 | return board_fix_fdt((void *)gd->fdt_blob); | |
759 | } | |
760 | #endif | |
761 | ||
1938f4a5 | 762 | /* ARM calls relocate_code from its crt0.S */ |
8f015d37 | 763 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5 SG |
764 | |
765 | static int jump_to_copy(void) | |
766 | { | |
f05ad9ba SG |
767 | if (gd->flags & GD_FLG_SKIP_RELOC) |
768 | return 0; | |
48a33806 SG |
769 | /* |
770 | * x86 is special, but in a nice way. It uses a trampoline which | |
771 | * enables the dcache if possible. | |
772 | * | |
773 | * For now, other archs use relocate_code(), which is implemented | |
774 | * similarly for all archs. When we do generic relocation, hopefully | |
775 | * we can make all archs enable the dcache prior to relocation. | |
776 | */ | |
3fb80163 | 777 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
778 | /* |
779 | * SDRAM and console are now initialised. The final stack can now | |
780 | * be setup in SDRAM. Code execution will continue in Flash, but | |
781 | * with the stack in SDRAM and Global Data in temporary memory | |
782 | * (CPU cache) | |
783 | */ | |
f0c7d9c7 | 784 | arch_setup_gd(gd->new_gd); |
8f015d37 SG |
785 | # if CONFIG_IS_ENABLED(X86_64) |
786 | board_init_f_r_trampoline64(gd->new_gd, gd->start_addr_sp); | |
787 | # else | |
788 | board_init_f_r_trampoline(gd->start_addr_sp); | |
789 | # endif | |
48a33806 | 790 | #else |
a0ba279a | 791 | relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); |
48a33806 | 792 | #endif |
1938f4a5 SG |
793 | |
794 | return 0; | |
795 | } | |
796 | #endif | |
797 | ||
798 | /* Record the board_init_f() bootstage (after arch_cpu_init()) */ | |
b383d6c0 | 799 | static int initf_bootstage(void) |
1938f4a5 | 800 | { |
baa7d345 SG |
801 | bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) && |
802 | IS_ENABLED(CONFIG_BOOTSTAGE_STASH); | |
b383d6c0 SG |
803 | int ret; |
804 | ||
824bb1b4 | 805 | ret = bootstage_init(!from_spl); |
b383d6c0 SG |
806 | if (ret) |
807 | return ret; | |
824bb1b4 SG |
808 | if (from_spl) { |
809 | const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR, | |
810 | CONFIG_BOOTSTAGE_STASH_SIZE); | |
811 | ||
812 | ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE); | |
813 | if (ret && ret != -ENOENT) { | |
814 | debug("Failed to unstash bootstage: err=%d\n", ret); | |
815 | return ret; | |
816 | } | |
817 | } | |
b383d6c0 | 818 | |
1938f4a5 SG |
819 | bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); |
820 | ||
821 | return 0; | |
822 | } | |
823 | ||
ab7cd627 SG |
824 | static int initf_dm(void) |
825 | { | |
3d6d5075 | 826 | #if defined(CONFIG_DM) && CONFIG_IS_ENABLED(SYS_MALLOC_F) |
ab7cd627 SG |
827 | int ret; |
828 | ||
b67eefdb | 829 | bootstage_start(BOOTSTAGE_ID_ACCUM_DM_F, "dm_f"); |
ab7cd627 | 830 | ret = dm_init_and_scan(true); |
b67eefdb | 831 | bootstage_accum(BOOTSTAGE_ID_ACCUM_DM_F); |
ab7cd627 SG |
832 | if (ret) |
833 | return ret; | |
4b9a121f OP |
834 | |
835 | if (IS_ENABLED(CONFIG_TIMER_EARLY)) { | |
836 | ret = dm_timer_init(); | |
837 | if (ret) | |
838 | return ret; | |
839 | } | |
1057e6cf | 840 | #endif |
ab7cd627 SG |
841 | |
842 | return 0; | |
843 | } | |
844 | ||
146251f8 SG |
845 | /* Architecture-specific memory reservation */ |
846 | __weak int reserve_arch(void) | |
847 | { | |
848 | return 0; | |
849 | } | |
850 | ||
016e4ae7 OP |
851 | __weak int checkcpu(void) |
852 | { | |
853 | return 0; | |
854 | } | |
855 | ||
fbf9c154 OP |
856 | __weak int clear_bss(void) |
857 | { | |
858 | return 0; | |
859 | } | |
860 | ||
4acff452 | 861 | static const init_fnc_t init_sequence_f[] = { |
1938f4a5 | 862 | setup_mon_len, |
b45122fd | 863 | #ifdef CONFIG_OF_CONTROL |
0879361f | 864 | fdtdec_setup, |
b45122fd | 865 | #endif |
7ef8e9b0 | 866 | #ifdef CONFIG_TRACE_EARLY |
71c52dba | 867 | trace_early_init, |
d210718d | 868 | #endif |
768e0f52 | 869 | initf_malloc, |
af1bc0cf | 870 | log_init, |
5ac44a55 | 871 | initf_bootstage, /* uses its own timer, so does not need DM */ |
5a421904 | 872 | event_init, |
3d653180 | 873 | bloblist_maybe_init, |
b0edea3c | 874 | setup_spl_handoff, |
8e8d45ee OP |
875 | #if defined(CONFIG_CONSOLE_RECORD_INIT_F) |
876 | console_record_init, | |
877 | #endif | |
13a7db9a | 878 | INITCALL_EVENT(EVT_FSP_INIT_F), |
1938f4a5 | 879 | arch_cpu_init, /* basic arch cpu dependent setup */ |
8ebf5069 | 880 | mach_cpu_init, /* SoC/machine dependent CPU setup */ |
3ea0953d | 881 | initf_dm, |
1938f4a5 SG |
882 | #if defined(CONFIG_BOARD_EARLY_INIT_F) |
883 | board_early_init_f, | |
884 | #endif | |
727e94a4 | 885 | #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) |
c252c068 | 886 | /* get CPU and bus clocks according to the environment variable */ |
e4fef6cf | 887 | get_clocks, /* get CPU and bus clocks (etc.) */ |
1793e782 | 888 | #endif |
56c3aa9a | 889 | #if !defined(CONFIG_M68K) || (defined(CONFIG_M68K) && !defined(CONFIG_MCFTMR)) |
1938f4a5 | 890 | timer_init, /* initialize timer */ |
0ce45287 | 891 | #endif |
e4fef6cf SG |
892 | #if defined(CONFIG_BOARD_POSTCLK_INIT) |
893 | board_postclk_init, | |
1938f4a5 SG |
894 | #endif |
895 | env_init, /* initialize environment */ | |
896 | init_baud_rate, /* initialze baudrate settings */ | |
897 | serial_init, /* serial communications setup */ | |
898 | console_init_f, /* stage 1 init of console */ | |
899 | display_options, /* say that we are here */ | |
900 | display_text_info, /* show debugging info if required */ | |
e4fef6cf | 901 | checkcpu, |
23471aed MS |
902 | #if defined(CONFIG_SYSRESET) |
903 | print_resetinfo, | |
904 | #endif | |
cc664000 | 905 | #if defined(CONFIG_DISPLAY_CPUINFO) |
1938f4a5 | 906 | print_cpuinfo, /* display cpu info (and speed) */ |
cc664000 | 907 | #endif |
af9e6ad4 CJF |
908 | #if defined(CONFIG_DTB_RESELECT) |
909 | embedded_dtb_select, | |
910 | #endif | |
1938f4a5 | 911 | #if defined(CONFIG_DISPLAY_BOARDINFO) |
0365ffcc | 912 | show_board_info, |
e4fef6cf SG |
913 | #endif |
914 | INIT_FUNC_WATCHDOG_INIT | |
c9eff0a6 | 915 | INITCALL_EVENT(EVT_MISC_INIT_F), |
e4fef6cf | 916 | INIT_FUNC_WATCHDOG_RESET |
55dabcc8 | 917 | #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) |
e4fef6cf | 918 | init_func_i2c, |
1938f4a5 SG |
919 | #endif |
920 | announce_dram_init, | |
1938f4a5 | 921 | dram_init, /* configure available RAM banks */ |
e4fef6cf SG |
922 | #ifdef CONFIG_POST |
923 | post_init_f, | |
924 | #endif | |
925 | INIT_FUNC_WATCHDOG_RESET | |
65cc0e2a | 926 | #if defined(CFG_SYS_DRAM_TEST) |
e4fef6cf | 927 | testdram, |
65cc0e2a | 928 | #endif /* CFG_SYS_DRAM_TEST */ |
e4fef6cf SG |
929 | INIT_FUNC_WATCHDOG_RESET |
930 | ||
1938f4a5 SG |
931 | #ifdef CONFIG_POST |
932 | init_post, | |
933 | #endif | |
e4fef6cf | 934 | INIT_FUNC_WATCHDOG_RESET |
1938f4a5 SG |
935 | /* |
936 | * Now that we have DRAM mapped and working, we can | |
937 | * relocate the code and continue running from DRAM. | |
938 | * | |
939 | * Reserve memory at end of RAM for (top down in that order): | |
940 | * - area that won't get touched by U-Boot and Linux (optional) | |
941 | * - kernel log buffer | |
942 | * - protected RAM | |
943 | * - LCD framebuffer | |
944 | * - monitor code | |
945 | * - board info struct | |
946 | */ | |
947 | setup_dest_addr, | |
313981c2 PP |
948 | #ifdef CONFIG_OF_BOARD_FIXUP |
949 | fix_fdt, | |
950 | #endif | |
7c5c137c | 951 | #ifdef CFG_PRAM |
1938f4a5 SG |
952 | reserve_pram, |
953 | #endif | |
954 | reserve_round_4k, | |
4ef9c772 | 955 | setup_relocaddr_from_bloblist, |
79926e4f | 956 | arch_reserve_mmu, |
5a541945 | 957 | reserve_video, |
8703ef3f | 958 | reserve_trace, |
1938f4a5 SG |
959 | reserve_uboot, |
960 | reserve_malloc, | |
961 | reserve_board, | |
1938f4a5 SG |
962 | reserve_global_data, |
963 | reserve_fdt, | |
25e7dc6a | 964 | reserve_bootstage, |
f0293d33 | 965 | reserve_bloblist, |
146251f8 | 966 | reserve_arch, |
1938f4a5 | 967 | reserve_stacks, |
76b00aca | 968 | dram_init_banksize, |
1938f4a5 | 969 | show_dram_config, |
e4fef6cf | 970 | INIT_FUNC_WATCHDOG_RESET |
1532885c | 971 | setup_bdinfo, |
1938f4a5 | 972 | display_new_sp, |
e4fef6cf | 973 | INIT_FUNC_WATCHDOG_RESET |
1938f4a5 | 974 | reloc_fdt, |
25e7dc6a | 975 | reloc_bootstage, |
f0293d33 | 976 | reloc_bloblist, |
1938f4a5 | 977 | setup_reloc, |
3fb80163 | 978 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
313aef37 | 979 | copy_uboot_to_ram, |
313aef37 SG |
980 | do_elf_reloc_fixups, |
981 | #endif | |
de5e5cea | 982 | clear_bss, |
50128aeb RV |
983 | /* |
984 | * Deregister all cyclic functions before relocation, so that | |
985 | * gd->cyclic_list does not contain any references to pre-relocation | |
986 | * devices. Drivers will register their cyclic functions anew when the | |
987 | * devices are probed again. | |
988 | * | |
989 | * This should happen as late as possible so that the window where a | |
990 | * watchdog device is not serviced is as small as possible. | |
991 | */ | |
992 | cyclic_unregister_all, | |
8f015d37 | 993 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5 SG |
994 | jump_to_copy, |
995 | #endif | |
996 | NULL, | |
997 | }; | |
998 | ||
999 | void board_init_f(ulong boot_flags) | |
1000 | { | |
1938f4a5 | 1001 | gd->flags = boot_flags; |
9aed5a27 | 1002 | gd->have_console = 0; |
1938f4a5 SG |
1003 | |
1004 | if (initcall_run_list(init_sequence_f)) | |
1005 | hang(); | |
1006 | ||
9b217498 | 1007 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ |
264d298f AB |
1008 | !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \ |
1009 | !defined(CONFIG_ARC) | |
1938f4a5 SG |
1010 | /* NOTREACHED - jump_to_copy() does not return */ |
1011 | hang(); | |
1012 | #endif | |
1013 | } | |
1014 | ||
3fb80163 | 1015 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
1016 | /* |
1017 | * For now this code is only used on x86. | |
1018 | * | |
1019 | * init_sequence_f_r is the list of init functions which are run when | |
1020 | * U-Boot is executing from Flash with a semi-limited 'C' environment. | |
1021 | * The following limitations must be considered when implementing an | |
1022 | * '_f_r' function: | |
1023 | * - 'static' variables are read-only | |
1024 | * - Global Data (gd->xxx) is read/write | |
1025 | * | |
1026 | * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if | |
1027 | * supported). It _should_, if possible, copy global data to RAM and | |
1028 | * initialise the CPU caches (to speed up the relocation process) | |
1029 | * | |
1030 | * NOTE: At present only x86 uses this route, but it is intended that | |
1031 | * all archs will move to this when generic relocation is implemented. | |
1032 | */ | |
4acff452 | 1033 | static const init_fnc_t init_sequence_f_r[] = { |
530f27ea | 1034 | #if !CONFIG_IS_ENABLED(X86_64) |
48a33806 | 1035 | init_cache_f_r, |
530f27ea | 1036 | #endif |
48a33806 SG |
1037 | |
1038 | NULL, | |
1039 | }; | |
1040 | ||
1041 | void board_init_f_r(void) | |
1042 | { | |
1043 | if (initcall_run_list(init_sequence_f_r)) | |
1044 | hang(); | |
1045 | ||
e4d6ab0c SG |
1046 | /* |
1047 | * The pre-relocation drivers may be using memory that has now gone | |
1048 | * away. Mark serial as unavailable - this will fall back to the debug | |
1049 | * UART if available. | |
af1bc0cf SG |
1050 | * |
1051 | * Do the same with log drivers since the memory may not be available. | |
e4d6ab0c | 1052 | */ |
af1bc0cf | 1053 | gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY); |
5ee94b4f SG |
1054 | #ifdef CONFIG_TIMER |
1055 | gd->timer = NULL; | |
1056 | #endif | |
e4d6ab0c | 1057 | |
48a33806 SG |
1058 | /* |
1059 | * U-Boot has been copied into SDRAM, the BSS has been cleared etc. | |
1060 | * Transfer execution from Flash to RAM by calculating the address | |
1061 | * of the in-RAM copy of board_init_r() and calling it | |
1062 | */ | |
7bf9f20d | 1063 | (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); |
48a33806 SG |
1064 | |
1065 | /* NOTREACHED - board_init_r() does not return */ | |
1066 | hang(); | |
1067 | } | |
5bcd19aa | 1068 | #endif /* CONFIG_X86 */ |