[people/ms/u-boot.git] / common / cmd_fpga.c

/*
 * (C) Copyright 2000, 2001
 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

/*
 *  FPGA support
 */
#include <common.h>
#include <command.h>
#if defined(CONFIG_CMD_NET)
#include <net.h>
#endif
#include <fpga.h>
#include <malloc.h>

#if 0
#define	FPGA_DEBUG
#endif

#ifdef	FPGA_DEBUG
#define	PRINTF(fmt,args...)	printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif

/* Local functions */
static int fpga_get_op (char *opstr);

/* Local defines */
#define FPGA_NONE   -1
#define FPGA_INFO   0
#define FPGA_LOAD   1
#define FPGA_LOADB  2
#define FPGA_DUMP   3
#define FPGA_LOADMK 4

/* Convert bitstream data and load into the fpga */
int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
{
#if defined(CONFIG_FPGA_XILINX)
	unsigned int length;
	unsigned int swapsize;
	char buffer[80];
	unsigned char *dataptr;
	unsigned int i;
	int rc;

	dataptr = (unsigned char *)fpgadata;

	/* skip the first bytes of the bitsteam, their meaning is unknown */
	length = (*dataptr << 8) + *(dataptr+1);
	dataptr+=2;
	dataptr+=length;

	/* get design name (identifier, length, string) */
	length = (*dataptr << 8) + *(dataptr+1);
	dataptr+=2;
	if (*dataptr++ != 0x61) {
		PRINTF ("%s: Design name identifier not recognized in bitstream\n",
			__FUNCTION__ );
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr+1);
	dataptr+=2;
	for(i=0;i<length;i++)
		buffer[i] = *dataptr++;

	printf("  design filename = \"%s\"\n", buffer);

	/* get part number (identifier, length, string) */
	if (*dataptr++ != 0x62) {
		printf("%s: Part number identifier not recognized in bitstream\n",
			__FUNCTION__ );
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr+1);
	dataptr+=2;
	for(i=0;i<length;i++)
		buffer[i] = *dataptr++;
	printf("  part number = \"%s\"\n", buffer);

	/* get date (identifier, length, string) */
	if (*dataptr++ != 0x63) {
		printf("%s: Date identifier not recognized in bitstream\n",
		       __FUNCTION__);
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr+1);
	dataptr+=2;
	for(i=0;i<length;i++)
		buffer[i] = *dataptr++;
	printf("  date = \"%s\"\n", buffer);

	/* get time (identifier, length, string) */
	if (*dataptr++ != 0x64) {
		printf("%s: Time identifier not recognized in bitstream\n",__FUNCTION__);
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr+1);
	dataptr+=2;
	for(i=0;i<length;i++)
		buffer[i] = *dataptr++;
	printf("  time = \"%s\"\n", buffer);

	/* get fpga data length (identifier, length) */
	if (*dataptr++ != 0x65) {
		printf("%s: Data length identifier not recognized in bitstream\n",
			__FUNCTION__);
		return FPGA_FAIL;
	}
	swapsize = ((unsigned int) *dataptr     <<24) +
	           ((unsigned int) *(dataptr+1) <<16) +
	           ((unsigned int) *(dataptr+2) <<8 ) +
	           ((unsigned int) *(dataptr+3)     ) ;
	dataptr+=4;
	printf("  bytes in bitstream = %d\n", swapsize);

	rc = fpga_load(dev, dataptr, swapsize);
	return rc;
#else
	printf("Bitstream support only for Xilinx devices\n");
	return FPGA_FAIL;
#endif
}

/* ------------------------------------------------------------------------- */
/* command form:
 *   fpga <op> <device number> <data addr> <datasize>
 * where op is 'load', 'dump', or 'info'
 * If there is no device number field, the fpga environment variable is used.
 * If there is no data addr field, the fpgadata environment variable is used.
 * The info command requires no data address field.
 */
int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	int op, dev = FPGA_INVALID_DEVICE;
	size_t data_size = 0;
	void *fpga_data = NULL;
	char *devstr = getenv ("fpga");
	char *datastr = getenv ("fpgadata");
	int rc = FPGA_FAIL;
	int wrong_parms = 0;
#if defined (CONFIG_FIT)
	const char *fit_uname = NULL;
	ulong fit_addr;
#endif

	if (devstr)
		dev = (int) simple_strtoul (devstr, NULL, 16);
	if (datastr)
		fpga_data = (void *) simple_strtoul (datastr, NULL, 16);

	switch (argc) {
	case 5:		/* fpga <op> <dev> <data> <datasize> */
		data_size = simple_strtoul (argv[4], NULL, 16);

	case 4:		/* fpga <op> <dev> <data> */
#if defined(CONFIG_FIT)
		if (fit_parse_subimage (argv[3], (ulong)fpga_data,
					&fit_addr, &fit_uname)) {
			fpga_data = (void *)fit_addr;
			debug ("*  fpga: subimage '%s' from FIT image at 0x%08lx\n",
					fit_uname, fit_addr);
		} else
#endif
		{
			fpga_data = (void *) simple_strtoul (argv[3], NULL, 16);
			debug ("*  fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data);
		}
		PRINTF ("%s: fpga_data = 0x%x\n", __FUNCTION__, (uint) fpga_data);

	case 3:		/* fpga <op> <dev | data addr> */
		dev = (int) simple_strtoul (argv[2], NULL, 16);
		PRINTF ("%s: device = %d\n", __FUNCTION__, dev);
		/* FIXME - this is a really weak test */
		if ((argc == 3) && (dev > fpga_count ())) {	/* must be buffer ptr */
			PRINTF ("%s: Assuming buffer pointer in arg 3\n",
				__FUNCTION__);

#if defined(CONFIG_FIT)
			if (fit_parse_subimage (argv[2], (ulong)fpga_data,
						&fit_addr, &fit_uname)) {
				fpga_data = (void *)fit_addr;
				debug ("*  fpga: subimage '%s' from FIT image at 0x%08lx\n",
						fit_uname, fit_addr);
			} else
#endif
			{
				fpga_data = (void *) dev;
				debug ("*  fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data);
			}

			PRINTF ("%s: fpga_data = 0x%x\n",
				__FUNCTION__, (uint) fpga_data);
			dev = FPGA_INVALID_DEVICE;	/* reset device num */
		}

	case 2:		/* fpga <op> */
		op = (int) fpga_get_op (argv[1]);
		break;

	default:
		PRINTF ("%s: Too many or too few args (%d)\n",
			__FUNCTION__, argc);
		op = FPGA_NONE;	/* force usage display */
		break;
	}

	if (dev == FPGA_INVALID_DEVICE) {
		puts("FPGA device not specified\n");
		op = FPGA_NONE;
	}

	switch (op) {
	case FPGA_NONE:
	case FPGA_INFO:
		break;
	case FPGA_LOAD:
	case FPGA_LOADB:
	case FPGA_DUMP:
		if (!fpga_data || !data_size)
			wrong_parms = 1;
		break;
	case FPGA_LOADMK:
		if (!fpga_data)
			wrong_parms = 1;
		break;
	}

	if (wrong_parms) {
		puts("Wrong parameters for FPGA request\n");
		op = FPGA_NONE;
	}

	switch (op) {
	case FPGA_NONE:
		return cmd_usage(cmdtp);

	case FPGA_INFO:
		rc = fpga_info (dev);
		break;

	case FPGA_LOAD:
		rc = fpga_load (dev, fpga_data, data_size);
		break;

	case FPGA_LOADB:
		rc = fpga_loadbitstream(dev, fpga_data, data_size);
		break;

	case FPGA_LOADMK:
		switch (genimg_get_format (fpga_data)) {
		case IMAGE_FORMAT_LEGACY:
			{
				image_header_t *hdr = (image_header_t *)fpga_data;
				ulong	data;

				data = (ulong)image_get_data (hdr);
				data_size = image_get_data_size (hdr);
				rc = fpga_load (dev, (void *)data, data_size);
			}
			break;
#if defined(CONFIG_FIT)
		case IMAGE_FORMAT_FIT:
			{
				const void *fit_hdr = (const void *)fpga_data;
				int noffset;
				void *fit_data;

				if (fit_uname == NULL) {
					puts ("No FIT subimage unit name\n");
					return 1;
				}

				if (!fit_check_format (fit_hdr)) {
					puts ("Bad FIT image format\n");
					return 1;
				}

				/* get fpga component image node offset */
				noffset = fit_image_get_node (fit_hdr, fit_uname);
				if (noffset < 0) {
					printf ("Can't find '%s' FIT subimage\n", fit_uname);
					return 1;
				}

				/* verify integrity */
				if (!fit_image_check_hashes (fit_hdr, noffset)) {
					puts ("Bad Data Hash\n");
					return 1;
				}

				/* get fpga subimage data address and length */
				if (fit_image_get_data (fit_hdr, noffset, &fit_data, &data_size)) {
					puts ("Could not find fpga subimage data\n");
					return 1;
				}

				rc = fpga_load (dev, fit_data, data_size);
			}
			break;
#endif
		default:
			puts ("** Unknown image type\n");
			rc = FPGA_FAIL;
			break;
		}
		break;

	case FPGA_DUMP:
		rc = fpga_dump (dev, fpga_data, data_size);
		break;

	default:
		printf ("Unknown operation\n");
		return cmd_usage(cmdtp);
	}
	return (rc);
}

/*
 * Map op to supported operations.  We don't use a table since we
 * would just have to relocate it from flash anyway.
 */
static int fpga_get_op (char *opstr)
{
	int op = FPGA_NONE;

	if (!strcmp ("info", opstr)) {
		op = FPGA_INFO;
	} else if (!strcmp ("loadb", opstr)) {
		op = FPGA_LOADB;
	} else if (!strcmp ("load", opstr)) {
		op = FPGA_LOAD;
	} else if (!strcmp ("loadmk", opstr)) {
		op = FPGA_LOADMK;
	} else if (!strcmp ("dump", opstr)) {
		op = FPGA_DUMP;
	}

	if (op == FPGA_NONE) {
		printf ("Unknown fpga operation \"%s\"\n", opstr);
	}
	return op;
}

U_BOOT_CMD (fpga, 6, 1, do_fpga,
	"loadable FPGA image support",
	"[operation type] [device number] [image address] [image size]\n"
	"fpga operations:\n"
	"  dump\t[dev]\t\t\tLoad device to memory buffer\n"
	"  info\t[dev]\t\t\tlist known device information\n"
	"  load\t[dev] [address] [size]\tLoad device from memory buffer\n"
	"  loadb\t[dev] [address] [size]\t"
	"Load device from bitstream buffer (Xilinx only)\n"
	"  loadmk [dev] [address]\tLoad device generated with mkimage"
#if defined(CONFIG_FIT)
	"\n"
	"\tFor loadmk operating on FIT format uImage address must include\n"
	"\tsubimage unit name in the form of addr:<subimg_uname>"
#endif
);
Commit	Line	Data
4a9cbbe8 WD	1	/*
	2	* (C) Copyright 2000, 2001
	3	* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*
	23	*/
	24
	25	/*
	26	* FPGA support
	27	*/
	28	#include <common.h>
	29	#include <command.h>
baa26db4	30	#if defined(CONFIG_CMD_NET)
4a9cbbe8 WD	31	#include <net.h>
4a9cbbe8 WD	32	#endif
8bde7f77	33	#include <fpga.h>
c3d2b4b4	34	#include <malloc.h>
4a9cbbe8 WD	35
	36	#if 0
	37	#define FPGA_DEBUG
	38	#endif
	39
	40	#ifdef FPGA_DEBUG
	41	#define PRINTF(fmt,args...) printf (fmt ,##args)
	42	#else
	43	#define PRINTF(fmt,args...)
	44	#endif
	45
4a9cbbe8	46	/* Local functions */
d4ca31c4	47	static int fpga_get_op (char *opstr);
4a9cbbe8 WD	48
	49	/* Local defines */
	50	#define FPGA_NONE -1
	51	#define FPGA_INFO 0
	52	#define FPGA_LOAD 1
30ce5ab0	53	#define FPGA_LOADB 2
4a9cbbe8	54	#define FPGA_DUMP 3
f0ff4692	55	#define FPGA_LOADMK 4
4a9cbbe8	56
30ce5ab0 WD	57	/* Convert bitstream data and load into the fpga */
	58	int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
	59	{
0133502e	60	#if defined(CONFIG_FPGA_XILINX)
8b019da6	61	unsigned int length;
8b019da6	62	unsigned int swapsize;
30ce5ab0	63	char buffer[80];
8b019da6	64	unsigned char *dataptr;
8b019da6	65	unsigned int i;
30ce5ab0 WD	66	int rc;
30ce5ab0 WD	67
77ddac94	68	dataptr = (unsigned char *)fpgadata;
30ce5ab0	69
8b019da6 WD	70	/* skip the first bytes of the bitsteam, their meaning is unknown */
	71	length = (dataptr << 8) + (dataptr+1);
	72	dataptr+=2;
	73	dataptr+=length;
30ce5ab0 WD	74
30ce5ab0 WD	75	/* get design name (identifier, length, string) */
8b019da6 WD	76	length = (dataptr << 8) + (dataptr+1);
8b019da6 WD	77	dataptr+=2;
30ce5ab0	78	if (*dataptr++ != 0x61) {
8b019da6 WD	79	PRINTF ("%s: Design name identifier not recognized in bitstream\n",
8b019da6 WD	80	__FUNCTION__ );
30ce5ab0 WD	81	return FPGA_FAIL;
	82	}
	83
a562e1bd	84	length = (dataptr << 8) + (dataptr+1);
30ce5ab0 WD	85	dataptr+=2;
30ce5ab0 WD	86	for(i=0;i<length;i++)
d0ff51ba	87	buffer[i] = *dataptr++;
a562e1bd	88
8b019da6	89	printf(" design filename = \"%s\"\n", buffer);
30ce5ab0 WD	90
	91	/* get part number (identifier, length, string) */
	92	if (*dataptr++ != 0x62) {
8b019da6 WD	93	printf("%s: Part number identifier not recognized in bitstream\n",
8b019da6 WD	94	__FUNCTION__ );
30ce5ab0 WD	95	return FPGA_FAIL;
30ce5ab0 WD	96	}
a562e1bd	97
8b019da6 WD	98	length = (dataptr << 8) + (dataptr+1);
8b019da6 WD	99	dataptr+=2;
a562e1bd	100	for(i=0;i<length;i++)
d0ff51ba	101	buffer[i] = *dataptr++;
8b019da6	102	printf(" part number = \"%s\"\n", buffer);
a562e1bd	103
30ce5ab0 WD	104	/* get date (identifier, length, string) */
30ce5ab0 WD	105	if (*dataptr++ != 0x63) {
8b019da6 WD	106	printf("%s: Date identifier not recognized in bitstream\n",
8b019da6 WD	107	__FUNCTION__);
30ce5ab0 WD	108	return FPGA_FAIL;
30ce5ab0 WD	109	}
a562e1bd	110
8b019da6 WD	111	length = (dataptr << 8) + (dataptr+1);
8b019da6 WD	112	dataptr+=2;
30ce5ab0	113	for(i=0;i<length;i++)
d0ff51ba	114	buffer[i] = *dataptr++;
8b019da6	115	printf(" date = \"%s\"\n", buffer);
30ce5ab0 WD	116
	117	/* get time (identifier, length, string) */
	118	if (*dataptr++ != 0x64) {
8b019da6	119	printf("%s: Time identifier not recognized in bitstream\n",__FUNCTION__);
30ce5ab0 WD	120	return FPGA_FAIL;
30ce5ab0 WD	121	}
a562e1bd	122
8b019da6 WD	123	length = (dataptr << 8) + (dataptr+1);
8b019da6 WD	124	dataptr+=2;
30ce5ab0	125	for(i=0;i<length;i++)
d0ff51ba	126	buffer[i] = *dataptr++;
8b019da6	127	printf(" time = \"%s\"\n", buffer);
a562e1bd	128
30ce5ab0 WD	129	/* get fpga data length (identifier, length) */
30ce5ab0 WD	130	if (*dataptr++ != 0x65) {
8b019da6 WD	131	printf("%s: Data length identifier not recognized in bitstream\n",
8b019da6 WD	132	__FUNCTION__);
30ce5ab0 WD	133	return FPGA_FAIL;
30ce5ab0 WD	134	}
8f79e4c2 WD	135	swapsize = ((unsigned int) *dataptr <<24) +
	136	((unsigned int) *(dataptr+1) <<16) +
	137	((unsigned int) *(dataptr+2) <<8 ) +
8b019da6	138	((unsigned int) *(dataptr+3) ) ;
30ce5ab0	139	dataptr+=4;
8b019da6	140	printf(" bytes in bitstream = %d\n", swapsize);
a562e1bd	141
c26acc1a	142	rc = fpga_load(dev, dataptr, swapsize);
30ce5ab0 WD	143	return rc;
30ce5ab0 WD	144	#else
8b019da6	145	printf("Bitstream support only for Xilinx devices\n");
30ce5ab0 WD	146	return FPGA_FAIL;
	147	#endif
	148	}
	149
4a9cbbe8 WD	150	/* ------------------------------------------------------------------------- */
	151	/* command form:
	152	* fpga <op> <device number> <data addr> <datasize>
	153	* where op is 'load', 'dump', or 'info'
	154	* If there is no device number field, the fpga environment variable is used.
	155	* If there is no data addr field, the fpgadata environment variable is used.
	156	* The info command requires no data address field.
	157	*/
54841ab5	158	int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
4a9cbbe8	159	{
d4ca31c4 WD	160	int op, dev = FPGA_INVALID_DEVICE;
	161	size_t data_size = 0;
	162	void *fpga_data = NULL;
	163	char *devstr = getenv ("fpga");
	164	char *datastr = getenv ("fpgadata");
	165	int rc = FPGA_FAIL;
a790b5b2	166	int wrong_parms = 0;
c28c4d19 MB	167	#if defined (CONFIG_FIT)
	168	const char *fit_uname = NULL;
	169	ulong fit_addr;
	170	#endif
d4ca31c4 WD	171
	172	if (devstr)
	173	dev = (int) simple_strtoul (devstr, NULL, 16);
	174	if (datastr)
	175	fpga_data = (void *) simple_strtoul (datastr, NULL, 16);
	176
	177	switch (argc) {
	178	case 5: /* fpga <op> <dev> <data> <datasize> */
	179	data_size = simple_strtoul (argv[4], NULL, 16);
c28c4d19	180
d4ca31c4	181	case 4: /* fpga <op> <dev> <data> */
c28c4d19 MB	182	#if defined(CONFIG_FIT)
	183	if (fit_parse_subimage (argv[3], (ulong)fpga_data,
	184	&fit_addr, &fit_uname)) {
	185	fpga_data = (void *)fit_addr;
	186	debug ("* fpga: subimage '%s' from FIT image at 0x%08lx\n",
	187	fit_uname, fit_addr);
	188	} else
	189	#endif
	190	{
	191	fpga_data = (void *) simple_strtoul (argv[3], NULL, 16);
	192	debug ("* fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data);
	193	}
8b019da6	194	PRINTF ("%s: fpga_data = 0x%x\n", __FUNCTION__, (uint) fpga_data);
c28c4d19	195
d4ca31c4 WD	196	case 3: /* fpga <op> <dev \| data addr> */
d4ca31c4 WD	197	dev = (int) simple_strtoul (argv[2], NULL, 16);
8b019da6	198	PRINTF ("%s: device = %d\n", __FUNCTION__, dev);
d4ca31c4 WD	199	/* FIXME - this is a really weak test */
d4ca31c4 WD	200	if ((argc == 3) && (dev > fpga_count ())) { /* must be buffer ptr */
8f79e4c2	201	PRINTF ("%s: Assuming buffer pointer in arg 3\n",
8b019da6	202	__FUNCTION__);
c28c4d19 MB	203
	204	#if defined(CONFIG_FIT)
	205	if (fit_parse_subimage (argv[2], (ulong)fpga_data,
	206	&fit_addr, &fit_uname)) {
	207	fpga_data = (void *)fit_addr;
	208	debug ("* fpga: subimage '%s' from FIT image at 0x%08lx\n",
	209	fit_uname, fit_addr);
	210	} else
	211	#endif
	212	{
	213	fpga_data = (void *) dev;
	214	debug ("* fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data);
	215	}
	216
8b019da6 WD	217	PRINTF ("%s: fpga_data = 0x%x\n",
8b019da6 WD	218	__FUNCTION__, (uint) fpga_data);
d4ca31c4 WD	219	dev = FPGA_INVALID_DEVICE; /* reset device num */
d4ca31c4 WD	220	}
c28c4d19	221
d4ca31c4 WD	222	case 2: /* fpga <op> */
	223	op = (int) fpga_get_op (argv[1]);
	224	break;
c28c4d19	225
d4ca31c4	226	default:
8b019da6 WD	227	PRINTF ("%s: Too many or too few args (%d)\n",
8b019da6 WD	228	__FUNCTION__, argc);
d4ca31c4 WD	229	op = FPGA_NONE; /* force usage display */
	230	break;
	231	}
	232
a790b5b2 SB	233	if (dev == FPGA_INVALID_DEVICE) {
	234	puts("FPGA device not specified\n");
	235	op = FPGA_NONE;
	236	}
	237
	238	switch (op) {
	239	case FPGA_NONE:
	240	case FPGA_INFO:
	241	break;
	242	case FPGA_LOAD:
	243	case FPGA_LOADB:
	244	case FPGA_DUMP:
	245	if (!fpga_data \|\| !data_size)
	246	wrong_parms = 1;
	247	break;
	248	case FPGA_LOADMK:
	249	if (!fpga_data)
	250	wrong_parms = 1;
	251	break;
	252	}
	253
	254	if (wrong_parms) {
	255	puts("Wrong parameters for FPGA request\n");
	256	op = FPGA_NONE;
	257	}
	258
d4ca31c4 WD	259	switch (op) {
d4ca31c4 WD	260	case FPGA_NONE:
47e26b1b	261	return cmd_usage(cmdtp);
d4ca31c4 WD	262
	263	case FPGA_INFO:
	264	rc = fpga_info (dev);
	265	break;
	266
	267	case FPGA_LOAD:
	268	rc = fpga_load (dev, fpga_data, data_size);
	269	break;
	270
30ce5ab0 WD	271	case FPGA_LOADB:
	272	rc = fpga_loadbitstream(dev, fpga_data, data_size);
	273	break;
	274
f0ff4692	275	case FPGA_LOADMK:
9a4daad0	276	switch (genimg_get_format (fpga_data)) {
d5934ad7 MB	277	case IMAGE_FORMAT_LEGACY:
	278	{
	279	image_header_t hdr = (image_header_t )fpga_data;
	280	ulong data;
	281
d5934ad7 MB	282	data = (ulong)image_get_data (hdr);
	283	data_size = image_get_data_size (hdr);
	284	rc = fpga_load (dev, (void *)data, data_size);
f0ff4692	285	}
d5934ad7 MB	286	break;
	287	#if defined(CONFIG_FIT)
	288	case IMAGE_FORMAT_FIT:
c28c4d19 MB	289	{
	290	const void fit_hdr = (const void )fpga_data;
	291	int noffset;
	292	void *fit_data;
	293
	294	if (fit_uname == NULL) {
	295	puts ("No FIT subimage unit name\n");
	296	return 1;
	297	}
	298
	299	if (!fit_check_format (fit_hdr)) {
	300	puts ("Bad FIT image format\n");
	301	return 1;
	302	}
	303
	304	/* get fpga component image node offset */
	305	noffset = fit_image_get_node (fit_hdr, fit_uname);
	306	if (noffset < 0) {
	307	printf ("Can't find '%s' FIT subimage\n", fit_uname);
	308	return 1;
	309	}
	310
	311	/* verify integrity */
	312	if (!fit_image_check_hashes (fit_hdr, noffset)) {
	313	puts ("Bad Data Hash\n");
	314	return 1;
	315	}
	316
	317	/* get fpga subimage data address and length */
	318	if (fit_image_get_data (fit_hdr, noffset, &fit_data, &data_size)) {
	319	puts ("Could not find fpga subimage data\n");
	320	return 1;
	321	}
	322
	323	rc = fpga_load (dev, fit_data, data_size);
	324	}
d5934ad7 MB	325	break;
	326	#endif
	327	default:
	328	puts ("** Unknown image type\n");
	329	rc = FPGA_FAIL;
	330	break;
f0ff4692 SR	331	}
	332	break;
	333
d4ca31c4 WD	334	case FPGA_DUMP:
	335	rc = fpga_dump (dev, fpga_data, data_size);
	336	break;
	337
	338	default:
8b019da6	339	printf ("Unknown operation\n");
47e26b1b	340	return cmd_usage(cmdtp);
d4ca31c4 WD	341	}
d4ca31c4 WD	342	return (rc);
4a9cbbe8 WD	343	}
4a9cbbe8 WD	344
4a9cbbe8 WD	345	/*
	346	* Map op to supported operations. We don't use a table since we
	347	* would just have to relocate it from flash anyway.
	348	*/
d4ca31c4	349	static int fpga_get_op (char *opstr)
4a9cbbe8 WD	350	{
	351	int op = FPGA_NONE;
	352
	353	if (!strcmp ("info", opstr)) {
	354	op = FPGA_INFO;
30ce5ab0 WD	355	} else if (!strcmp ("loadb", opstr)) {
30ce5ab0 WD	356	op = FPGA_LOADB;
d4ca31c4	357	} else if (!strcmp ("load", opstr)) {
4a9cbbe8	358	op = FPGA_LOAD;
f0ff4692 SR	359	} else if (!strcmp ("loadmk", opstr)) {
f0ff4692 SR	360	op = FPGA_LOADMK;
d4ca31c4	361	} else if (!strcmp ("dump", opstr)) {
4a9cbbe8 WD	362	op = FPGA_DUMP;
	363	}
	364
d4ca31c4	365	if (op == FPGA_NONE) {
4a9cbbe8 WD	366	printf ("Unknown fpga operation \"%s\"\n", opstr);
	367	}
	368	return op;
	369	}
	370
d4ca31c4	371	U_BOOT_CMD (fpga, 6, 1, do_fpga,
a790b5b2 SB	372	"loadable FPGA image support",
	373	"[operation type] [device number] [image address] [image size]\n"
	374	"fpga operations:\n"
	375	" dump\t[dev]\t\t\tLoad device to memory buffer\n"
	376	" info\t[dev]\t\t\tlist known device information\n"
	377	" load\t[dev] [address] [size]\tLoad device from memory buffer\n"
	378	" loadb\t[dev] [address] [size]\t"
	379	"Load device from bitstream buffer (Xilinx only)\n"
	380	" loadmk [dev] [address]\tLoad device generated with mkimage"
c28c4d19	381	#if defined(CONFIG_FIT)
a790b5b2 SB	382	"\n"
	383	"\tFor loadmk operating on FIT format uImage address must include\n"
	384	"\tsubimage unit name in the form of addr:<subimg_uname>"
c28c4d19 MB	385	#endif
c28c4d19 MB	386	);