[people/ms/u-boot.git] / common / cmd_pci.c

/*
 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Andreas Heppel <aheppel@sysgo.de>
 *
 * (C) Copyright 2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * PCI routines
 */

#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>

extern int cmd_get_data_size(char* arg, int default_size);

unsigned char	ShortPCIListing = 1;

/*
 * Follows routines for the output of infos about devices on PCI bus.
 */

void pci_header_show(pci_dev_t dev);
void pci_header_show_brief(pci_dev_t dev);

/*
 * Subroutine:  pciinfo
 *
 * Description: Show information about devices on PCI bus.
 *				Depending on the define CFG_SHORT_PCI_LISTING
 *				the output will be more or less exhaustive.
 *
 * Inputs:	bus_no		the number of the bus to be scanned.
 *
 * Return:      None
 *
 */
void pciinfo(int BusNum, int ShortPCIListing)
{
	int Device;
	int Function;
	unsigned char HeaderType;
	unsigned short VendorID;
	pci_dev_t dev;

	printf("Scanning PCI devices on bus %d\n", BusNum);

	if (ShortPCIListing) {
		printf("BusDevFun  VendorId   DeviceId   Device Class       Sub-Class\n");
		printf("_____________________________________________________________\n");
	}

	for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
		HeaderType = 0;
		VendorID = 0;
		for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
			/*
			 * If this is not a multi-function device, we skip the rest.
			 */
			if (Function && !(HeaderType & 0x80))
				break;

			dev = PCI_BDF(BusNum, Device, Function);

			pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
			if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
				continue;

			if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);

			if (ShortPCIListing)
			{
				printf("%02x.%02x.%02x   ", BusNum, Device, Function);
				pci_header_show_brief(dev);
			}
			else
			{
				printf("\nFound PCI device %02x.%02x.%02x:\n",
				       BusNum, Device, Function);
				pci_header_show(dev);
			}
	    }
    }
}

static char *pci_classes_str(u8 class)
{
	switch (class) {
	case PCI_CLASS_NOT_DEFINED:
		return "Build before PCI Rev2.0";
		break;
	case PCI_BASE_CLASS_STORAGE:
		return "Mass storage controller";
		break;
	case PCI_BASE_CLASS_NETWORK:
		return "Network controller";
		break;
	case PCI_BASE_CLASS_DISPLAY:
		return "Display controller";
		break;
	case PCI_BASE_CLASS_MULTIMEDIA:
		return "Multimedia device";
		break;
	case PCI_BASE_CLASS_MEMORY:
		return "Memory controller";
		break;
	case PCI_BASE_CLASS_BRIDGE:
		return "Bridge device";
		break;
	case PCI_BASE_CLASS_COMMUNICATION:
		return "Simple comm. controller";
		break;
	case PCI_BASE_CLASS_SYSTEM:
		return "Base system peripheral";
		break;
	case PCI_BASE_CLASS_INPUT:
		return "Input device";
		break;
	case PCI_BASE_CLASS_DOCKING:
		return "Docking station";
		break;
	case PCI_BASE_CLASS_PROCESSOR:
		return "Processor";
		break;
	case PCI_BASE_CLASS_SERIAL:
		return "Serial bus controller";
		break;
	case PCI_BASE_CLASS_INTELLIGENT:
		return "Intelligent controller";
		break;
	case PCI_BASE_CLASS_SATELLITE:
		return "Satellite controller";
		break;
	case PCI_BASE_CLASS_CRYPT:
		return "Cryptographic device";
		break;
	case PCI_BASE_CLASS_SIGNAL_PROCESSING:
		return "DSP";
		break;
	case PCI_CLASS_OTHERS:
		return "Does not fit any class";
		break;
	default:
	return  "???";
		break;
	};
}

/*
 * Subroutine:  pci_header_show_brief
 *
 * Description: Reads and prints the header of the
 * 		specified PCI device in short form.
 *
 * Inputs:	dev      Bus+Device+Function number
 *
 * Return:      None
 *
 */
void pci_header_show_brief(pci_dev_t dev)
{
	u16 vendor, device;
	u8 class, subclass;

	pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
	pci_read_config_word(dev, PCI_DEVICE_ID, &device);
	pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
	pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);

	printf("0x%.4x     0x%.4x     %-23s 0x%.2x\n",
	       vendor, device,
	       pci_classes_str(class), subclass);
}

/*
 * Subroutine:  PCI_Header_Show
 *
 * Description: Reads the header of the specified PCI device.
 *
 * Inputs:		BusDevFunc      Bus+Device+Function number
 *
 * Return:      None
 *
 */
void pci_header_show(pci_dev_t dev)
{
	u8 _byte, header_type;
	u16 _word;
	u32 _dword;

#define PRINT(msg, type, reg) \
	pci_read_config_##type(dev, reg, &_##type); \
	printf(msg, _##type)

#define PRINT2(msg, type, reg, func) \
	pci_read_config_##type(dev, reg, &_##type); \
	printf(msg, _##type, func(_##type))

	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);

	PRINT ("  vendor ID =                   0x%.4x\n", word, PCI_VENDOR_ID);
	PRINT ("  device ID =                   0x%.4x\n", word, PCI_DEVICE_ID);
	PRINT ("  command register =            0x%.4x\n", word, PCI_COMMAND);
	PRINT ("  status register =             0x%.4x\n", word, PCI_STATUS);
	PRINT ("  revision ID =                 0x%.2x\n", byte, PCI_REVISION_ID);
	PRINT2("  class code =                  0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
								pci_classes_str);
	PRINT ("  sub class code =              0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
	PRINT ("  programming interface =       0x%.2x\n", byte, PCI_CLASS_PROG);
	PRINT ("  cache line =                  0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
	PRINT ("  latency time =                0x%.2x\n", byte, PCI_LATENCY_TIMER);
	PRINT ("  header type =                 0x%.2x\n", byte, PCI_HEADER_TYPE);
	PRINT ("  BIST =                        0x%.2x\n", byte, PCI_BIST);
	PRINT ("  base address 0 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_0);

	switch (header_type & 0x03) {
	case PCI_HEADER_TYPE_NORMAL:	/* "normal" PCI device */
		PRINT ("  base address 1 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
		PRINT ("  base address 2 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
		PRINT ("  base address 3 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
		PRINT ("  base address 4 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
		PRINT ("  base address 5 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
		PRINT ("  cardBus CIS pointer =         0x%.8x\n", dword, PCI_CARDBUS_CIS);
		PRINT ("  sub system vendor ID =        0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
		PRINT ("  sub system ID =               0x%.4x\n", word, PCI_SUBSYSTEM_ID);
		PRINT ("  expansion ROM base address =  0x%.8x\n", dword, PCI_ROM_ADDRESS);
		PRINT ("  interrupt line =              0x%.2x\n", byte, PCI_INTERRUPT_LINE);
		PRINT ("  interrupt pin =               0x%.2x\n", byte, PCI_INTERRUPT_PIN);
		PRINT ("  min Grant =                   0x%.2x\n", byte, PCI_MIN_GNT);
		PRINT ("  max Latency =                 0x%.2x\n", byte, PCI_MAX_LAT);
		break;

	case PCI_HEADER_TYPE_BRIDGE:	/* PCI-to-PCI bridge */

		PRINT ("  base address 1 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
		PRINT ("  primary bus number =          0x%.2x\n", byte, PCI_PRIMARY_BUS);
		PRINT ("  secondary bus number =        0x%.2x\n", byte, PCI_SECONDARY_BUS);
		PRINT ("  subordinate bus number =      0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
		PRINT ("  secondary latency timer =     0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
		PRINT ("  IO base =                     0x%.2x\n", byte, PCI_IO_BASE);
		PRINT ("  IO limit =                    0x%.2x\n", byte, PCI_IO_LIMIT);
		PRINT ("  secondary status =            0x%.4x\n", word, PCI_SEC_STATUS);
		PRINT ("  memory base =                 0x%.4x\n", word, PCI_MEMORY_BASE);
		PRINT ("  memory limit =                0x%.4x\n", word, PCI_MEMORY_LIMIT);
		PRINT ("  prefetch memory base =        0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
		PRINT ("  prefetch memory limit =       0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
		PRINT ("  prefetch memory base upper =  0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
		PRINT ("  prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
		PRINT ("  IO base upper 16 bits =       0x%.4x\n", word, PCI_IO_BASE_UPPER16);
		PRINT ("  IO limit upper 16 bits =      0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
		PRINT ("  expansion ROM base address =  0x%.8x\n", dword, PCI_ROM_ADDRESS1);
		PRINT ("  interrupt line =              0x%.2x\n", byte, PCI_INTERRUPT_LINE);
		PRINT ("  interrupt pin =               0x%.2x\n", byte, PCI_INTERRUPT_PIN);
		PRINT ("  bridge control =              0x%.4x\n", word, PCI_BRIDGE_CONTROL);
		break;

	case PCI_HEADER_TYPE_CARDBUS:	/* PCI-to-CardBus bridge */

		PRINT ("  capabilities =                0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
		PRINT ("  secondary status =            0x%.4x\n", word, PCI_CB_SEC_STATUS);
		PRINT ("  primary bus number =          0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
		PRINT ("  CardBus number =              0x%.2x\n", byte, PCI_CB_CARD_BUS);
		PRINT ("  subordinate bus number =      0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
		PRINT ("  CardBus latency timer =       0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
		PRINT ("  CardBus memory base 0 =       0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
		PRINT ("  CardBus memory limit 0 =      0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
		PRINT ("  CardBus memory base 1 =       0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
		PRINT ("  CardBus memory limit 1 =      0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
		PRINT ("  CardBus IO base 0 =           0x%.4x\n", word, PCI_CB_IO_BASE_0);
		PRINT ("  CardBus IO base high 0 =      0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
		PRINT ("  CardBus IO limit 0 =          0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
		PRINT ("  CardBus IO limit high 0 =     0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
		PRINT ("  CardBus IO base 1 =           0x%.4x\n", word, PCI_CB_IO_BASE_1);
		PRINT ("  CardBus IO base high 1 =      0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
		PRINT ("  CardBus IO limit 1 =          0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
		PRINT ("  CardBus IO limit high 1 =     0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
		PRINT ("  interrupt line =              0x%.2x\n", byte, PCI_INTERRUPT_LINE);
		PRINT ("  interrupt pin =               0x%.2x\n", byte, PCI_INTERRUPT_PIN);
		PRINT ("  bridge control =              0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
		PRINT ("  subvendor ID =                0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
		PRINT ("  subdevice ID =                0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
		PRINT ("  PC Card 16bit base address =  0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
		break;

	default:
		printf("unknown header\n");
		break;
    }

#undef PRINT
#undef PRINT2
}

/* Convert the "bus.device.function" identifier into a number.
 */
static pci_dev_t get_pci_dev(char* name)
{
	char cnum[12];
	int len, i, iold, n;
	int bdfs[3] = {0,0,0};

	len = strlen(name);
	if (len > 8)
		return -1;
	for (i = 0, iold = 0, n = 0; i < len; i++) {
		if (name[i] == '.') {
			memcpy(cnum, &name[iold], i - iold);
			cnum[i - iold] = '\0';
			bdfs[n++] = simple_strtoul(cnum, NULL, 16);
			iold = i + 1;
		}
	}
	strcpy(cnum, &name[iold]);
	if (n == 0)
		n = 1;
	bdfs[n] = simple_strtoul(cnum, NULL, 16);
	return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
}

static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
{
#define DISP_LINE_LEN	16
	ulong i, nbytes, linebytes;
	int rc = 0;

	if (length == 0)
		length = 0x40 / size; /* Standard PCI configuration space */

	/* Print the lines.
	 * once, and all accesses are with the specified bus width.
	 */
	nbytes = length * size;
	do {
		uint	val4;
		ushort  val2;
		u_char	val1;

		printf("%08lx:", addr);
		linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
		for (i=0; i<linebytes; i+= size) {
			if (size == 4) {
				pci_read_config_dword(bdf, addr, &val4);
				printf(" %08x", val4);
			} else if (size == 2) {
				pci_read_config_word(bdf, addr, &val2);
				printf(" %04x", val2);
			} else {
				pci_read_config_byte(bdf, addr, &val1);
				printf(" %02x", val1);
			}
			addr += size;
		}
		printf("\n");
		nbytes -= linebytes;
		if (ctrlc()) {
			rc = 1;
			break;
		}
	} while (nbytes > 0);

	return (rc);
}

static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
{
	if (size == 4) {
		pci_write_config_dword(bdf, addr, value);
	}
	else if (size == 2) {
		ushort val = value & 0xffff;
		pci_write_config_word(bdf, addr, val);
	}
	else {
		u_char val = value & 0xff;
		pci_write_config_byte(bdf, addr, val);
	}
	return 0;
}

static int
pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
{
	ulong	i;
	int	nbytes;
	extern char console_buffer[];
	uint	val4;
	ushort  val2;
	u_char	val1;

	/* Print the address, followed by value.  Then accept input for
	 * the next value.  A non-converted value exits.
	 */
	do {
		printf("%08lx:", addr);
		if (size == 4) {
			pci_read_config_dword(bdf, addr, &val4);
			printf(" %08x", val4);
		}
		else if (size == 2) {
			pci_read_config_word(bdf, addr, &val2);
			printf(" %04x", val2);
		}
		else {
			pci_read_config_byte(bdf, addr, &val1);
			printf(" %02x", val1);
		}

		nbytes = readline (" ? ");
		if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
			/* <CR> pressed as only input, don't modify current
			 * location and move to next. "-" pressed will go back.
			 */
			if (incrflag)
				addr += nbytes ? -size : size;
			nbytes = 1;
#ifdef CONFIG_BOOT_RETRY_TIME
			reset_cmd_timeout(); /* good enough to not time out */
#endif
		}
#ifdef CONFIG_BOOT_RETRY_TIME
		else if (nbytes == -2) {
			break;	/* timed out, exit the command	*/
		}
#endif
		else {
			char *endp;
			i = simple_strtoul(console_buffer, &endp, 16);
			nbytes = endp - console_buffer;
			if (nbytes) {
#ifdef CONFIG_BOOT_RETRY_TIME
				/* good enough to not time out
				 */
				reset_cmd_timeout();
#endif
				pci_cfg_write (bdf, addr, size, i);
				if (incrflag)
					addr += size;
			}
		}
	} while (nbytes);

	return 0;
}

/* PCI Configuration Space access commands
 *
 * Syntax:
 *	pci display[.b, .w, .l] bus.device.function} [addr] [len]
 *	pci next[.b, .w, .l] bus.device.function [addr]
 *      pci modify[.b, .w, .l] bus.device.function [addr]
 *      pci write[.b, .w, .l] bus.device.function addr value
 */
int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	ulong addr = 0, value = 0, size = 0;
	pci_dev_t bdf = 0;
	char cmd = 's';

	if (argc > 1)
		cmd = argv[1][0];

	switch (cmd) {
	case 'd':		/* display */
	case 'n':		/* next */
	case 'm':		/* modify */
	case 'w':		/* write */
		/* Check for a size specification. */
		size = cmd_get_data_size(argv[1], 4);
		if (argc > 3)
			addr = simple_strtoul(argv[3], NULL, 16);
		if (argc > 4)
			value = simple_strtoul(argv[4], NULL, 16);
	case 'h':		/* header */
		if (argc < 3)
			goto usage;
		if ((bdf = get_pci_dev(argv[2])) == -1)
			return 1;
		break;
	default:		/* scan bus */
		value = 1; /* short listing */
		bdf = 0;   /* bus number  */
		if (argc > 1) {
			if (argv[argc-1][0] == 'l') {
				value = 0;
				argc--;
			}
			if (argc > 1)
				bdf = simple_strtoul(argv[1], NULL, 16);
		}
		pciinfo(bdf, value);
		return 0;
	}

	switch (argv[1][0]) {
	case 'h':		/* header */
		pci_header_show(bdf);
		return 0;
	case 'd':		/* display */
		return pci_cfg_display(bdf, addr, size, value);
	case 'n':		/* next */
		if (argc < 4)
			goto usage;
		return pci_cfg_modify(bdf, addr, size, value, 0);
	case 'm':		/* modify */
		if (argc < 4)
			goto usage;
		return pci_cfg_modify(bdf, addr, size, value, 1);
	case 'w':		/* write */
		if (argc < 5)
			goto usage;
		return pci_cfg_write(bdf, addr, size, value);
	}

	return 1;
 usage:
	printf ("Usage:\n%s\n", cmdtp->usage);
	return 1;
}

/***************************************************/


U_BOOT_CMD(
	pci,	5,	1,	do_pci,
	"pci     - list and access PCI Configuration Space\n",
	"[bus] [long]\n"
	"    - short or long list of PCI devices on bus 'bus'\n"
	"pci header b.d.f\n"
	"    - show header of PCI device 'bus.device.function'\n"
	"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
	"    - display PCI configuration space (CFG)\n"
	"pci next[.b, .w, .l] b.d.f address\n"
	"    - modify, read and keep CFG address\n"
	"pci modify[.b, .w, .l] b.d.f address\n"
	"    -  modify, auto increment CFG address\n"
	"pci write[.b, .w, .l] b.d.f address value\n"
	"    - write to CFG address\n"
);
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	3	* Andreas Heppel <aheppel@sysgo.de>
	4	*
	5	* (C) Copyright 2002
	6	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	7	* Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	/*
	29	* PCI routines
	30	*/
	31
	32	#include <common.h>
c609719b	33	#include <command.h>
c609719b WD	34	#include <asm/processor.h>
c609719b WD	35	#include <asm/io.h>
c609719b WD	36	#include <pci.h>
c609719b WD	37
c609719b WD	38	extern int cmd_get_data_size(char* arg, int default_size);
	39
	40	unsigned char ShortPCIListing = 1;
	41
	42	/*
	43	* Follows routines for the output of infos about devices on PCI bus.
	44	*/
	45
	46	void pci_header_show(pci_dev_t dev);
	47	void pci_header_show_brief(pci_dev_t dev);
	48
	49	/*
	50	* Subroutine: pciinfo
	51	*
	52	* Description: Show information about devices on PCI bus.
	53	* Depending on the define CFG_SHORT_PCI_LISTING
	54	* the output will be more or less exhaustive.
	55	*
	56	* Inputs: bus_no the number of the bus to be scanned.
	57	*
	58	* Return: None
	59	*
	60	*/
	61	void pciinfo(int BusNum, int ShortPCIListing)
	62	{
	63	int Device;
	64	int Function;
	65	unsigned char HeaderType;
	66	unsigned short VendorID;
	67	pci_dev_t dev;
	68
	69	printf("Scanning PCI devices on bus %d\n", BusNum);
	70
	71	if (ShortPCIListing) {
	72	printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
	73	printf("_____________________________________________________________\n");
	74	}
	75
	76	for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
	77	HeaderType = 0;
	78	VendorID = 0;
	79	for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
	80	/*
	81	* If this is not a multi-function device, we skip the rest.
	82	*/
	83	if (Function && !(HeaderType & 0x80))
	84	break;
	85
	86	dev = PCI_BDF(BusNum, Device, Function);
	87
	88	pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
	89	if ((VendorID == 0xFFFF) \|\| (VendorID == 0x0000))
	90	continue;
	91
c7de829c	92	if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);
c609719b WD	93
	94	if (ShortPCIListing)
	95	{
	96	printf("%02x.%02x.%02x ", BusNum, Device, Function);
	97	pci_header_show_brief(dev);
	98	}
	99	else
	100	{
	101	printf("\nFound PCI device %02x.%02x.%02x:\n",
	102	BusNum, Device, Function);
	103	pci_header_show(dev);
	104	}
	105	}
	106	}
	107	}
	108
5d232d0e	109	static char *pci_classes_str(u8 class)
c609719b	110	{
06d01dbe	111	switch (class) {
8bde7f77 WD	112	case PCI_CLASS_NOT_DEFINED:
	113	return "Build before PCI Rev2.0";
	114	break;
	115	case PCI_BASE_CLASS_STORAGE:
	116	return "Mass storage controller";
	117	break;
	118	case PCI_BASE_CLASS_NETWORK:
	119	return "Network controller";
	120	break;
	121	case PCI_BASE_CLASS_DISPLAY:
	122	return "Display controller";
	123	break;
	124	case PCI_BASE_CLASS_MULTIMEDIA:
	125	return "Multimedia device";
	126	break;
	127	case PCI_BASE_CLASS_MEMORY:
	128	return "Memory controller";
	129	break;
	130	case PCI_BASE_CLASS_BRIDGE:
	131	return "Bridge device";
	132	break;
	133	case PCI_BASE_CLASS_COMMUNICATION:
	134	return "Simple comm. controller";
	135	break;
	136	case PCI_BASE_CLASS_SYSTEM:
	137	return "Base system peripheral";
	138	break;
	139	case PCI_BASE_CLASS_INPUT:
	140	return "Input device";
	141	break;
	142	case PCI_BASE_CLASS_DOCKING:
	143	return "Docking station";
	144	break;
	145	case PCI_BASE_CLASS_PROCESSOR:
	146	return "Processor";
	147	break;
	148	case PCI_BASE_CLASS_SERIAL:
	149	return "Serial bus controller";
	150	break;
	151	case PCI_BASE_CLASS_INTELLIGENT:
	152	return "Intelligent controller";
	153	break;
	154	case PCI_BASE_CLASS_SATELLITE:
	155	return "Satellite controller";
	156	break;
	157	case PCI_BASE_CLASS_CRYPT:
	158	return "Cryptographic device";
	159	break;
	160	case PCI_BASE_CLASS_SIGNAL_PROCESSING:
	161	return "DSP";
	162	break;
	163	case PCI_CLASS_OTHERS:
	164	return "Does not fit any class";
	165	break;
	166	default:
5d232d0e	167	return "???";
8bde7f77	168	break;
06d01dbe	169	};
c609719b WD	170	}
	171
	172	/*
	173	* Subroutine: pci_header_show_brief
	174	*
	175	* Description: Reads and prints the header of the
	176	* specified PCI device in short form.
	177	*
	178	* Inputs: dev Bus+Device+Function number
	179	*
	180	* Return: None
	181	*
	182	*/
	183	void pci_header_show_brief(pci_dev_t dev)
	184	{
	185	u16 vendor, device;
	186	u8 class, subclass;
	187
	188	pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
	189	pci_read_config_word(dev, PCI_DEVICE_ID, &device);
	190	pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
	191	pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
	192
5d232d0e	193	printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
c609719b WD	194	vendor, device,
	195	pci_classes_str(class), subclass);
	196	}
	197
	198	/*
	199	* Subroutine: PCI_Header_Show
	200	*
	201	* Description: Reads the header of the specified PCI device.
	202	*
	203	* Inputs: BusDevFunc Bus+Device+Function number
	204	*
	205	* Return: None
	206	*
	207	*/
	208	void pci_header_show(pci_dev_t dev)
	209	{
	210	u8 _byte, header_type;
	211	u16 _word;
	212	u32 _dword;
	213
	214	#define PRINT(msg, type, reg) \
	215	pci_read_config_##type(dev, reg, &_##type); \
	216	printf(msg, _##type)
	217
	218	#define PRINT2(msg, type, reg, func) \
	219	pci_read_config_##type(dev, reg, &_##type); \
	220	printf(msg, _##type, func(_##type))
	221
	222	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
	223
	224	PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID);
	225	PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID);
	226	PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND);
	227	PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
	228	PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
	229	PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
8bde7f77	230	pci_classes_str);
c609719b WD	231	PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
	232	PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
	233	PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
	234	PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER);
	235	PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
	236	PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
	237	PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
c609719b	238
7c7a23bd WD	239	switch (header_type & 0x03) {
	240	case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
	241	PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
	242	PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
	243	PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
	244	PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
	245	PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
	246	PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
	247	PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
	248	PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
	249	PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
	250	PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
	251	PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
	252	PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
	253	PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
	254	break;
8bde7f77	255
7c7a23bd WD	256	case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
	257
	258	PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
c609719b WD	259	PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
	260	PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
	261	PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
	262	PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
	263	PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE);
	264	PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT);
	265	PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS);
	266	PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE);
	267	PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT);
	268	PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
	269	PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
	270	PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
	271	PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
	272	PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16);
	273	PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
	274	PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1);
	275	PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
	276	PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
	277	PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
7c7a23bd WD	278	break;
	279
	280	case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
	281
	282	PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
	283	PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
	284	PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
	285	PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
	286	PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
8bde7f77	287	PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
7c7a23bd WD	288	PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
	289	PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
	290	PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
	291	PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
	292	PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
	293	PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
	294	PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
	295	PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
	296	PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
	297	PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
	298	PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
	299	PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
	300	PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
	301	PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
	302	PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
	303	PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
	304	PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
	305	PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
	306	break;
8bde7f77	307
7c7a23bd WD	308	default:
7c7a23bd WD	309	printf("unknown header\n");
8bde7f77	310	break;
c609719b WD	311	}
	312
	313	#undef PRINT
	314	#undef PRINT2
	315	}
	316
	317	/* Convert the "bus.device.function" identifier into a number.
	318	*/
	319	static pci_dev_t get_pci_dev(char* name)
	320	{
	321	char cnum[12];
	322	int len, i, iold, n;
	323	int bdfs[3] = {0,0,0};
	324
	325	len = strlen(name);
	326	if (len > 8)
	327	return -1;
	328	for (i = 0, iold = 0, n = 0; i < len; i++) {
	329	if (name[i] == '.') {
	330	memcpy(cnum, &name[iold], i - iold);
	331	cnum[i - iold] = '\0';
	332	bdfs[n++] = simple_strtoul(cnum, NULL, 16);
	333	iold = i + 1;
	334	}
	335	}
	336	strcpy(cnum, &name[iold]);
	337	if (n == 0)
	338	n = 1;
	339	bdfs[n] = simple_strtoul(cnum, NULL, 16);
	340	return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
	341	}
	342
	343	static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
	344	{
	345	#define DISP_LINE_LEN 16
	346	ulong i, nbytes, linebytes;
	347	int rc = 0;
	348
	349	if (length == 0)
	350	length = 0x40 / size; /* Standard PCI configuration space */
	351
	352	/* Print the lines.
	353	* once, and all accesses are with the specified bus width.
	354	*/
	355	nbytes = length * size;
	356	do {
	357	uint val4;
	358	ushort val2;
	359	u_char val1;
	360
	361	printf("%08lx:", addr);
	362	linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
	363	for (i=0; i<linebytes; i+= size) {
	364	if (size == 4) {
	365	pci_read_config_dword(bdf, addr, &val4);
	366	printf(" %08x", val4);
	367	} else if (size == 2) {
	368	pci_read_config_word(bdf, addr, &val2);
	369	printf(" %04x", val2);
	370	} else {
	371	pci_read_config_byte(bdf, addr, &val1);
	372	printf(" %02x", val1);
	373	}
	374	addr += size;
375	}
376	printf("\n");
377	nbytes -= linebytes;
378	if (ctrlc()) {
379	rc = 1;
380	break;
381	}
382	} while (nbytes > 0);
383
384	return (rc);
385	}
386
387	static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
388	{
389	if (size == 4) {
390	pci_write_config_dword(bdf, addr, value);
391	}
392	else if (size == 2) {
393	ushort val = value & 0xffff;
394	pci_write_config_word(bdf, addr, val);
395	}
396	else {
397	u_char val = value & 0xff;
398	pci_write_config_byte(bdf, addr, val);
399	}
400	return 0;
401	}
402
403	static int
404	pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
405	{
406	ulong i;
407	int nbytes;
408	extern char console_buffer[];
409	uint val4;
410	ushort val2;
411	u_char val1;
412
413	/* Print the address, followed by value. Then accept input for
414	* the next value. A non-converted value exits.
415	*/
416	do {
417	printf("%08lx:", addr);
418	if (size == 4) {
419	pci_read_config_dword(bdf, addr, &val4);
420	printf(" %08x", val4);
421	}
422	else if (size == 2) {
423	pci_read_config_word(bdf, addr, &val2);
424	printf(" %04x", val2);
425	}
426	else {
427	pci_read_config_byte(bdf, addr, &val1);
428	printf(" %02x", val1);
429	}
430
431	nbytes = readline (" ? ");
432	if (nbytes == 0 \|\| (nbytes == 1 && console_buffer[0] == '-')) {
433	/* <CR> pressed as only input, don't modify current
434	* location and move to next. "-" pressed will go back.
435	*/
436	if (incrflag)
437	addr += nbytes ? -size : size;
438	nbytes = 1;
439	#ifdef CONFIG_BOOT_RETRY_TIME
440	reset_cmd_timeout(); /* good enough to not time out */
441	#endif
442	}
443	#ifdef CONFIG_BOOT_RETRY_TIME
444	else if (nbytes == -2) {
445	break; /* timed out, exit the command */
446	}
447	#endif
448	else {
449	char *endp;
450	i = simple_strtoul(console_buffer, &endp, 16);
451	nbytes = endp - console_buffer;
452	if (nbytes) {
453	#ifdef CONFIG_BOOT_RETRY_TIME
454	/* good enough to not time out
455	*/
456	reset_cmd_timeout();
457	#endif
458	pci_cfg_write (bdf, addr, size, i);
459	if (incrflag)
460	addr += size;
461	}
462	}
463	} while (nbytes);
464
465	return 0;
466	}
467
468	/* PCI Configuration Space access commands
469	*
470	* Syntax:
471	* pci display[.b, .w, .l] bus.device.function} [addr] [len]
472	* pci next[.b, .w, .l] bus.device.function [addr]
473	* pci modify[.b, .w, .l] bus.device.function [addr]
474	* pci write[.b, .w, .l] bus.device.function addr value
475	*/
476	int do_pci (cmd_tbl_t cmdtp, int flag, int argc, char argv[])
477	{
478	ulong addr = 0, value = 0, size = 0;
479	pci_dev_t bdf = 0;
480	char cmd = 's';
481
482	if (argc > 1)
483	cmd = argv[1][0];
484
485	switch (cmd) {
486	case 'd': /* display */
487	case 'n': /* next */
488	case 'm': /* modify */
489	case 'w': /* write */
490	/* Check for a size specification. */
491	size = cmd_get_data_size(argv[1], 4);
492	if (argc > 3)
493	addr = simple_strtoul(argv[3], NULL, 16);
494	if (argc > 4)
495	value = simple_strtoul(argv[4], NULL, 16);
496	case 'h': /* header */
497	if (argc < 3)
498	goto usage;
499	if ((bdf = get_pci_dev(argv[2])) == -1)
500	return 1;
501	break;
502	default: /* scan bus */
503	value = 1; /* short listing */
504	bdf = 0; /* bus number */
505	if (argc > 1) {
506	if (argv[argc-1][0] == 'l') {
507	value = 0;
508	argc--;
509	}
510	if (argc > 1)
511	bdf = simple_strtoul(argv[1], NULL, 16);
512	}
513	pciinfo(bdf, value);
514	return 0;
515	}
516
517	switch (argv[1][0]) {
518	case 'h': /* header */
519	pci_header_show(bdf);
520	return 0;
521	case 'd': /* display */
522	return pci_cfg_display(bdf, addr, size, value);
523	case 'n': /* next */
524	if (argc < 4)
525	goto usage;
526	return pci_cfg_modify(bdf, addr, size, value, 0);
527	case 'm': /* modify */
528	if (argc < 4)
529	goto usage;
530	return pci_cfg_modify(bdf, addr, size, value, 1);
531	case 'w': /* write */
532	if (argc < 5)
533	goto usage;
534	return pci_cfg_write(bdf, addr, size, value);
535	}
536
537	return 1;
538	usage:
539	printf ("Usage:\n%s\n", cmdtp->usage);
540	return 1;
541	}
542
8bde7f77 WD	543	/***************************************************/
	544
	545
0d498393 WD	546	U_BOOT_CMD(
0d498393 WD	547	pci, 5, 1, do_pci,
256d31c0	548	"pci - list and access PCI Configuration Space\n",
8bde7f77 WD	549	"[bus] [long]\n"
	550	" - short or long list of PCI devices on bus 'bus'\n"
	551	"pci header b.d.f\n"
	552	" - show header of PCI device 'bus.device.function'\n"
	553	"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
	554	" - display PCI configuration space (CFG)\n"
	555	"pci next[.b, .w, .l] b.d.f address\n"
	556	" - modify, read and keep CFG address\n"
	557	"pci modify[.b, .w, .l] b.d.f address\n"
	558	" - modify, auto increment CFG address\n"
	559	"pci write[.b, .w, .l] b.d.f address value\n"
	560	" - write to CFG address\n"
	561	);