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9b56f4f0 SH |
1 | /* |
2 | * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <common.h> | |
21 | ||
22 | #if defined CONFIG_MX31_UART | |
23 | ||
24 | #include <asm/arch/mx31.h> | |
25 | ||
26 | #define __REG(x) (*((volatile u32 *)(x))) | |
27 | ||
6d0f6bcf | 28 | #ifdef CONFIG_SYS_MX31_UART1 |
9b56f4f0 | 29 | #define UART_PHYS 0x43f90000 |
6d0f6bcf | 30 | #elif defined(CONFIG_SYS_MX31_UART2) |
9b56f4f0 | 31 | #define UART_PHYS 0x43f94000 |
6d0f6bcf | 32 | #elif defined(CONFIG_SYS_MX31_UART3) |
9b56f4f0 | 33 | #define UART_PHYS 0x5000c000 |
6d0f6bcf | 34 | #elif defined(CONFIG_SYS_MX31_UART4) |
9b56f4f0 | 35 | #define UART_PHYS 0x43fb0000 |
6d0f6bcf | 36 | #elif defined(CONFIG_SYS_MX31_UART5) |
9b56f4f0 SH |
37 | #define UART_PHYS 0x43fb4000 |
38 | #else | |
6d0f6bcf | 39 | #error "define CONFIG_SYS_MX31_UARTx to use the mx31 UART driver" |
9b56f4f0 SH |
40 | #endif |
41 | ||
42 | /* Register definitions */ | |
43 | #define URXD 0x0 /* Receiver Register */ | |
44 | #define UTXD 0x40 /* Transmitter Register */ | |
45 | #define UCR1 0x80 /* Control Register 1 */ | |
46 | #define UCR2 0x84 /* Control Register 2 */ | |
47 | #define UCR3 0x88 /* Control Register 3 */ | |
48 | #define UCR4 0x8c /* Control Register 4 */ | |
49 | #define UFCR 0x90 /* FIFO Control Register */ | |
50 | #define USR1 0x94 /* Status Register 1 */ | |
51 | #define USR2 0x98 /* Status Register 2 */ | |
52 | #define UESC 0x9c /* Escape Character Register */ | |
53 | #define UTIM 0xa0 /* Escape Timer Register */ | |
54 | #define UBIR 0xa4 /* BRM Incremental Register */ | |
55 | #define UBMR 0xa8 /* BRM Modulator Register */ | |
56 | #define UBRC 0xac /* Baud Rate Count Register */ | |
57 | #define UTS 0xb4 /* UART Test Register (mx31) */ | |
58 | ||
59 | /* UART Control Register Bit Fields.*/ | |
60 | #define URXD_CHARRDY (1<<15) | |
61 | #define URXD_ERR (1<<14) | |
62 | #define URXD_OVRRUN (1<<13) | |
63 | #define URXD_FRMERR (1<<12) | |
64 | #define URXD_BRK (1<<11) | |
65 | #define URXD_PRERR (1<<10) | |
d92ea21b | 66 | #define URXD_RX_DATA (0xFF) |
9b56f4f0 SH |
67 | #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ |
68 | #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ | |
69 | #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ | |
70 | #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ | |
71 | #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ | |
72 | #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ | |
73 | #define UCR1_IREN (1<<7) /* Infrared interface enable */ | |
74 | #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ | |
75 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ | |
76 | #define UCR1_SNDBRK (1<<4) /* Send break */ | |
77 | #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ | |
78 | #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ | |
79 | #define UCR1_DOZE (1<<1) /* Doze */ | |
80 | #define UCR1_UARTEN (1<<0) /* UART enabled */ | |
53677ef1 WD |
81 | #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ |
82 | #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ | |
83 | #define UCR2_CTSC (1<<13) /* CTS pin control */ | |
9b56f4f0 SH |
84 | #define UCR2_CTS (1<<12) /* Clear to send */ |
85 | #define UCR2_ESCEN (1<<11) /* Escape enable */ | |
86 | #define UCR2_PREN (1<<8) /* Parity enable */ | |
87 | #define UCR2_PROE (1<<7) /* Parity odd/even */ | |
88 | #define UCR2_STPB (1<<6) /* Stop */ | |
89 | #define UCR2_WS (1<<5) /* Word size */ | |
90 | #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ | |
91 | #define UCR2_TXEN (1<<2) /* Transmitter enabled */ | |
92 | #define UCR2_RXEN (1<<1) /* Receiver enabled */ | |
53677ef1 WD |
93 | #define UCR2_SRST (1<<0) /* SW reset */ |
94 | #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ | |
9b56f4f0 SH |
95 | #define UCR3_PARERREN (1<<12) /* Parity enable */ |
96 | #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ | |
97 | #define UCR3_DSR (1<<10) /* Data set ready */ | |
98 | #define UCR3_DCD (1<<9) /* Data carrier detect */ | |
99 | #define UCR3_RI (1<<8) /* Ring indicator */ | |
100 | #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ | |
101 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ | |
102 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ | |
103 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ | |
53677ef1 WD |
104 | #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ |
105 | #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ | |
106 | #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ | |
107 | #define UCR3_BPEN (1<<0) /* Preset registers enable */ | |
9b56f4f0 | 108 | #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ |
53677ef1 WD |
109 | #define UCR4_INVR (1<<9) /* Inverted infrared reception */ |
110 | #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ | |
111 | #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ | |
112 | #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ | |
113 | #define UCR4_IRSC (1<<5) /* IR special case */ | |
114 | #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ | |
115 | #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ | |
116 | #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ | |
117 | #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ | |
9b56f4f0 SH |
118 | #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ |
119 | #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ | |
120 | #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ | |
121 | #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ | |
53677ef1 WD |
122 | #define USR1_RTSS (1<<14) /* RTS pin status */ |
123 | #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ | |
124 | #define USR1_RTSD (1<<12) /* RTS delta */ | |
125 | #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ | |
9b56f4f0 SH |
126 | #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ |
127 | #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ | |
128 | #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ | |
53677ef1 | 129 | #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ |
9b56f4f0 | 130 | #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ |
53677ef1 WD |
131 | #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ |
132 | #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ | |
133 | #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ | |
134 | #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ | |
135 | #define USR2_IDLE (1<<12) /* Idle condition */ | |
136 | #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ | |
137 | #define USR2_WAKE (1<<7) /* Wake */ | |
138 | #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ | |
139 | #define USR2_TXDC (1<<3) /* Transmitter complete */ | |
140 | #define USR2_BRCD (1<<2) /* Break condition */ | |
9b56f4f0 SH |
141 | #define USR2_ORE (1<<1) /* Overrun error */ |
142 | #define USR2_RDR (1<<0) /* Recv data ready */ | |
143 | #define UTS_FRCPERR (1<<13) /* Force parity error */ | |
144 | #define UTS_LOOP (1<<12) /* Loop tx and rx */ | |
145 | #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ | |
146 | #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ | |
53677ef1 WD |
147 | #define UTS_TXFULL (1<<4) /* TxFIFO full */ |
148 | #define UTS_RXFULL (1<<3) /* RxFIFO full */ | |
9b56f4f0 SH |
149 | #define UTS_SOFTRST (1<<0) /* Software reset */ |
150 | ||
151 | DECLARE_GLOBAL_DATA_PTR; | |
152 | ||
153 | void serial_setbrg (void) | |
154 | { | |
155 | u32 clk = mx31_get_ipg_clk(); | |
156 | ||
157 | if (!gd->baudrate) | |
158 | gd->baudrate = CONFIG_BAUDRATE; | |
159 | ||
160 | __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ | |
161 | __REG(UART_PHYS + UBIR) = 0xf; | |
162 | __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); | |
163 | ||
164 | } | |
165 | ||
166 | int serial_getc (void) | |
167 | { | |
168 | while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY); | |
d92ea21b | 169 | return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */ |
9b56f4f0 SH |
170 | } |
171 | ||
172 | void serial_putc (const char c) | |
173 | { | |
174 | __REG(UART_PHYS + UTXD) = c; | |
175 | ||
176 | /* wait for transmitter to be ready */ | |
177 | while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)); | |
178 | ||
179 | /* If \n, also do \r */ | |
180 | if (c == '\n') | |
181 | serial_putc ('\r'); | |
182 | } | |
183 | ||
184 | /* | |
185 | * Test whether a character is in the RX buffer | |
186 | */ | |
187 | int serial_tstc (void) | |
188 | { | |
189 | /* If receive fifo is empty, return false */ | |
190 | if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) | |
191 | return 0; | |
192 | return 1; | |
193 | } | |
194 | ||
195 | void | |
196 | serial_puts (const char *s) | |
197 | { | |
198 | while (*s) { | |
199 | serial_putc (*s++); | |
200 | } | |
201 | } | |
202 | ||
203 | /* | |
204 | * Initialise the serial port with the given baudrate. The settings | |
205 | * are always 8 data bits, no parity, 1 stop bit, no start bits. | |
206 | * | |
207 | */ | |
208 | int serial_init (void) | |
209 | { | |
210 | __REG(UART_PHYS + UCR1) = 0x0; | |
211 | __REG(UART_PHYS + UCR2) = 0x0; | |
212 | ||
213 | while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)); | |
214 | ||
215 | __REG(UART_PHYS + UCR3) = 0x0704; | |
216 | __REG(UART_PHYS + UCR4) = 0x8000; | |
217 | __REG(UART_PHYS + UESC) = 0x002b; | |
218 | __REG(UART_PHYS + UTIM) = 0x0; | |
219 | ||
220 | __REG(UART_PHYS + UTS) = 0x0; | |
221 | ||
222 | serial_setbrg(); | |
223 | ||
224 | __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST; | |
225 | ||
226 | __REG(UART_PHYS + UCR1) = UCR1_UARTEN; | |
227 | ||
228 | return 0; | |
229 | } | |
230 | ||
231 | ||
232 | #endif /* CONFIG_MX31 */ |