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2cbe571a WD |
1 | /* |
2 | * Memory Setup stuff - taken from blob memsetup.S | |
3 | * | |
4 | * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and | |
b6508513 | 5 | * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) |
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6 | * |
7 | * Modified for the at91rm9200dk board by | |
8 | * (C) Copyright 2004 | |
9d5028c2 | 9 | * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
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10 | * |
11 | * See file CREDITS for list of people who contributed to this | |
12 | * project. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of | |
17 | * the License, or (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
b6508513 | 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
2cbe571a WD |
22 | * GNU General Public License for more details. |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
27 | * MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | #include <config.h> | |
31 | #include <version.h> | |
32 | ||
8aa1a2d1 | 33 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
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34 | /* |
35 | * some parameters for the board | |
36 | * | |
37 | * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in | |
9d5028c2 | 38 | * turn is based on the boot.bin code from ATMEL |
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39 | * |
40 | */ | |
41 | ||
42 | /* flash */ | |
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43 | #define MC_PUIA 0xFFFFFF10 |
44 | #define MC_PUP 0xFFFFFF50 | |
45 | #define MC_PUER 0xFFFFFF54 | |
46 | #define MC_ASR 0xFFFFFF04 | |
47 | #define MC_AASR 0xFFFFFF08 | |
48 | #define EBI_CFGR 0xFFFFFF64 | |
480ed1de | 49 | #define SMC_CSR0 0xFFFFFF70 |
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50 | |
51 | /* clocks */ | |
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52 | #define PLLAR 0xFFFFFC28 |
53 | #define PLLBR 0xFFFFFC2C | |
54 | #define MCKR 0xFFFFFC30 | |
55 | ||
56 | #define AT91C_BASE_CKGR 0xFFFFFC20 | |
57 | #define CKGR_MOR 0 | |
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58 | |
59 | /* sdram */ | |
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60 | #define PIOC_ASR 0xFFFFF870 |
61 | #define PIOC_BSR 0xFFFFF874 | |
62 | #define PIOC_PDR 0xFFFFF804 | |
63 | #define EBI_CSA 0xFFFFFF60 | |
64 | #define SDRC_CR 0xFFFFFF98 | |
65 | #define SDRC_MR 0xFFFFFF90 | |
66 | #define SDRC_TR 0xFFFFFF94 | |
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67 | |
68 | ||
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69 | _MTEXT_BASE: |
70 | #undef START_FROM_MEM | |
71 | #ifdef START_FROM_MEM | |
72 | .word TEXT_BASE-PHYS_FLASH_1 | |
73 | #else | |
2cbe571a | 74 | .word TEXT_BASE |
9d5028c2 | 75 | #endif |
2cbe571a | 76 | |
986ef434 WD |
77 | .globl lowlevel_init |
78 | lowlevel_init: | |
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79 | /* Get the CKGR Base Address */ |
80 | ldr r1, =AT91C_BASE_CKGR | |
81 | /* Main oscillator Enable register */ | |
6d0f6bcf | 82 | #ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR |
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83 | ldr r0, =0x0000FF01 /* Enable main oscillator, OSCOUNT = 0xFF */ |
84 | #else | |
85 | ldr r0, =0x0000FF00 /* Disable main oscillator, OSCOUNT = 0xFF */ | |
86 | #endif | |
87 | str r0, [r1, #CKGR_MOR] | |
88 | /* Add loop to compensate Main Oscillator startup time */ | |
89 | ldr r0, =0x00000010 | |
90 | LoopOsc: | |
91 | subs r0, r0, #1 | |
92 | bhi LoopOsc | |
93 | ||
2cbe571a | 94 | /* memory control configuration */ |
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95 | /* this isn't very elegant, but what the heck */ |
96 | ldr r0, =SMRDATA | |
9d5028c2 | 97 | ldr r1, _MTEXT_BASE |
2cbe571a | 98 | sub r0, r0, r1 |
b6508513 | 99 | add r2, r0, #80 |
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100 | 0: |
101 | /* the address */ | |
b6508513 | 102 | ldr r1, [r0], #4 |
2cbe571a | 103 | /* the value */ |
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104 | ldr r3, [r0], #4 |
105 | str r3, [r1] | |
106 | cmp r2, r0 | |
107 | bne 0b | |
2cbe571a | 108 | /* delay - this is all done by guess */ |
9d5028c2 | 109 | ldr r0, =0x00010000 |
2cbe571a | 110 | 1: |
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111 | subs r0, r0, #1 |
112 | bhi 1b | |
113 | ldr r0, =SMRDATA1 | |
9d5028c2 | 114 | ldr r1, _MTEXT_BASE |
2cbe571a | 115 | sub r0, r0, r1 |
b6508513 | 116 | add r2, r0, #176 |
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117 | 2: |
118 | /* the address */ | |
b6508513 | 119 | ldr r1, [r0], #4 |
2cbe571a | 120 | /* the value */ |
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121 | ldr r3, [r0], #4 |
122 | str r3, [r1] | |
123 | cmp r2, r0 | |
124 | bne 2b | |
2cbe571a | 125 | |
c0e82d50 | 126 | /* switch from FastBus to Asynchronous clock mode */ |
3b9dfddf | 127 | mrc p15, 0, r0, c1, c0, 0 |
c0e82d50 | 128 | orr r0, r0, #0xC0000000 @ set bit 31 (iA) and 30 (nF) |
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129 | mcr p15, 0, r0, c1, c0, 0 |
130 | ||
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131 | /* everything is fine now */ |
132 | mov pc, lr | |
133 | ||
134 | .ltorg | |
135 | ||
136 | SMRDATA: | |
137 | .word MC_PUIA | |
138 | .word MC_PUIA_VAL | |
139 | .word MC_PUP | |
140 | .word MC_PUP_VAL | |
141 | .word MC_PUER | |
142 | .word MC_PUER_VAL | |
143 | .word MC_ASR | |
144 | .word MC_ASR_VAL | |
145 | .word MC_AASR | |
146 | .word MC_AASR_VAL | |
147 | .word EBI_CFGR | |
148 | .word EBI_CFGR_VAL | |
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149 | .word SMC_CSR0 |
150 | .word SMC_CSR0_VAL | |
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151 | .word PLLAR |
152 | .word PLLAR_VAL | |
153 | .word PLLBR | |
154 | .word PLLBR_VAL | |
155 | .word MCKR | |
156 | .word MCKR_VAL | |
157 | /* SMRDATA is 80 bytes long */ | |
158 | /* here there's a delay of 100 */ | |
159 | SMRDATA1: | |
160 | .word PIOC_ASR | |
161 | .word PIOC_ASR_VAL | |
162 | .word PIOC_BSR | |
163 | .word PIOC_BSR_VAL | |
164 | .word PIOC_PDR | |
165 | .word PIOC_PDR_VAL | |
166 | .word EBI_CSA | |
167 | .word EBI_CSA_VAL | |
168 | .word SDRC_CR | |
169 | .word SDRC_CR_VAL | |
170 | .word SDRC_MR | |
171 | .word SDRC_MR_VAL | |
172 | .word SDRAM | |
173 | .word SDRAM_VAL | |
174 | .word SDRC_MR | |
175 | .word SDRC_MR_VAL1 | |
176 | .word SDRAM | |
177 | .word SDRAM_VAL | |
178 | .word SDRAM | |
179 | .word SDRAM_VAL | |
180 | .word SDRAM | |
181 | .word SDRAM_VAL | |
182 | .word SDRAM | |
183 | .word SDRAM_VAL | |
184 | .word SDRAM | |
185 | .word SDRAM_VAL | |
186 | .word SDRAM | |
187 | .word SDRAM_VAL | |
188 | .word SDRAM | |
189 | .word SDRAM_VAL | |
190 | .word SDRAM | |
191 | .word SDRAM_VAL | |
192 | .word SDRC_MR | |
193 | .word SDRC_MR_VAL2 | |
194 | .word SDRAM1 | |
195 | .word SDRAM_VAL | |
196 | .word SDRC_TR | |
197 | .word SDRC_TR_VAL | |
198 | .word SDRAM | |
199 | .word SDRAM_VAL | |
200 | .word SDRC_MR | |
201 | .word SDRC_MR_VAL3 | |
202 | .word SDRAM | |
203 | .word SDRAM_VAL | |
204 | /* SMRDATA1 is 176 bytes long */ | |
8aa1a2d1 | 205 | #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ |