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* Patch by Gary Jennejohn, 11 Sep 2003:
[people/ms/u-boot.git] / cpu / arm920t / usb_ohci.c
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149dded2
WD		 1/*
2 * URB OHCI HCD (Host Controller Driver) for USB on the S3C2400.
3 *
4 * (C) Copyright 2003
5 * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 *
25 * Note: Part of this code has been derived from linux
26 *
27 */
28/*
29 * IMPORTANT NOTES
30 * 1 - you MUST define LITTLEENDIAN in the configuration file for the
31 * board or this driver will NOT work!
32 * 2 - this driver is intended for use with USB Mass Storage Devices
33 * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
34 */
35
36#include <common.h>
37/* #include <pci.h> no PCI on the S3C2400 */
38
39#ifdef CONFIG_USB_OHCI
40
41#include <s3c2400.h>
42#include <malloc.h>
43#include <usb.h>
44#include "usb_ohci.h"
45
46#define OHCI_USE_NPS /* force NoPowerSwitching mode */
47#undef OHCI_VERBOSE_DEBUG /* not always helpful */
48
49
50/* For initializing controller (mask in an HCFS mode too) */
51#define OHCI_CONTROL_INIT \
52 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
53
54#define OHCI_UNLINK_TIMEOUT (CFG_HZ / 10)
55
56#define readl(a) (*((vu_long *)(a)))
57#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
58
59#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
60
61#undef DEBUG
62#ifdef DEBUG
63#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
64#else
65#define dbg(format, arg...) do {} while(0)
66#endif /* DEBUG */
67#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
68#undef SHOW_INFO
69#ifdef SHOW_INFO
70#define info(format, arg...) printf("INFO: " format "\n", ## arg)
71#else
72#define info(format, arg...) do {} while(0)
73#endif
74
75#define m16_swap(x) swap_16(x)
76#define m32_swap(x) swap_32(x)
77
78/* global ohci_t */
79static ohci_t gohci;
80/* this must be aligned to a 256 byte boundary */
81struct ohci_hcca ghcca[1];
82/* a pointer to the aligned storage */
83struct ohci_hcca *phcca;
84/* this allocates EDs for all possible endpoints */
85struct ohci_device ohci_dev;
86/* urb_priv */
87urb_priv_t urb_priv;
88
89/*-------------------------------------------------------------------------*/
90
91/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
92 * The erratum (#4) description is incorrect. AMD's workaround waits
93 * till some bits (mostly reserved) are clear; ok for all revs.
94 */
95#define OHCI_QUIRK_AMD756 0xabcd
96#define read_roothub(hc, register, mask) ({ \
97 u32 temp = readl (&hc->regs->roothub.register); \
98 if (hc->flags & OHCI_QUIRK_AMD756) \
99 while (temp & mask) \
100 temp = readl (&hc->regs->roothub.register); \
101 temp; })
102
103static u32 roothub_a (struct ohci *hc)
104 { return read_roothub (hc, a, 0xfc0fe000); }
105static inline u32 roothub_b (struct ohci *hc)
106 { return readl (&hc->regs->roothub.b); }
107static inline u32 roothub_status (struct ohci *hc)
108 { return readl (&hc->regs->roothub.status); }
109static u32 roothub_portstatus (struct ohci *hc, int i)
110 { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
111
112
113/* forward declaration */
114static int hc_interrupt (void);
115static void
116td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
117 int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
118
119/*-------------------------------------------------------------------------*
120 * URB support functions
121 *-------------------------------------------------------------------------*/
122
123/* free HCD-private data associated with this URB */
124
125static void urb_free_priv (urb_priv_t * urb)
126{
127 int i;
128 int last;
129 struct td * td;
130
131 last = urb->length - 1;
132 if (last >= 0) {
133 for (i = 0; i <= last; i++) {
134 td = urb->td[i];
135 if (td) {
136 td->usb_dev = NULL;
137 urb->td[i] = NULL;
138 }
139 }
140 }
141}
142
143/*-------------------------------------------------------------------------*/
144
145#ifdef DEBUG
146static int sohci_get_current_frame_number (struct usb_device * dev);
147
148/* debug| print the main components of an URB
149 * small: 0) header + data packets 1) just header */
150
151static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
152 int transfer_len, struct devrequest * setup, char * str, int small)
153{
154 urb_priv_t * purb = &urb_priv;
155
156 dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
157 str,
158 sohci_get_current_frame_number (dev),
159 usb_pipedevice (pipe),
160 usb_pipeendpoint (pipe),
161 usb_pipeout (pipe)? 'O': 'I',
162 usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
163 (usb_pipecontrol (pipe)? "CTRL": "BULK"),
164 purb->actual_length,
165 transfer_len, dev->status);
166#ifdef OHCI_VERBOSE_DEBUG
167 if (!small) {
168 int i, len;
169
170 if (usb_pipecontrol (pipe)) {
171 printf (__FILE__ ": cmd(8):");
172 for (i = 0; i < 8 ; i++)
173 printf (" %02x", ((__u8 *) setup) [i]);
174 printf ("\n");
175 }
176 if (transfer_len > 0 && buffer) {
177 printf (__FILE__ ": data(%d/%d):",
178 purb->actual_length,
179 transfer_len);
180 len = usb_pipeout (pipe)?
181 transfer_len: purb->actual_length;
182 for (i = 0; i < 16 && i < len; i++)
183 printf (" %02x", ((__u8 *) buffer) [i]);
184 printf ("%s\n", i < len? "...": "");
185 }
186 }
187#endif
188}
189
190/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
191void ep_print_int_eds (ohci_t *ohci, char * str) {
192 int i, j;
193 __u32 * ed_p;
194 for (i= 0; i < 32; i++) {
195 j = 5;
196 ed_p = &(ohci->hcca->int_table [i]);
197 if (*ed_p == 0)
198 continue;
199 printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
200 while (*ed_p != 0 && j--) {
201 ed_t *ed = (ed_t *)m32_swap(ed_p);
202 printf (" ed: %4x;", ed->hwINFO);
203 ed_p = &ed->hwNextED;
204 }
205 printf ("\n");
206 }
207}
208
209static void ohci_dump_intr_mask (char *label, __u32 mask)
210{
211 dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
212 label,
213 mask,
214 (mask & OHCI_INTR_MIE) ? " MIE" : "",
215 (mask & OHCI_INTR_OC) ? " OC" : "",
216 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
217 (mask & OHCI_INTR_FNO) ? " FNO" : "",
218 (mask & OHCI_INTR_UE) ? " UE" : "",
219 (mask & OHCI_INTR_RD) ? " RD" : "",
220 (mask & OHCI_INTR_SF) ? " SF" : "",
221 (mask & OHCI_INTR_WDH) ? " WDH" : "",
222 (mask & OHCI_INTR_SO) ? " SO" : ""
223 );
224}
225
226static void maybe_print_eds (char *label, __u32 value)
227{
228 ed_t *edp = (ed_t *)value;
229
230 if (value) {
231 dbg ("%s %08x", label, value);
232 dbg ("%08x", edp->hwINFO);
233 dbg ("%08x", edp->hwTailP);
234 dbg ("%08x", edp->hwHeadP);
235 dbg ("%08x", edp->hwNextED);
236 }
237}
238
239static char * hcfs2string (int state)
240{
241 switch (state) {
242 case OHCI_USB_RESET: return "reset";
243 case OHCI_USB_RESUME: return "resume";
244 case OHCI_USB_OPER: return "operational";
245 case OHCI_USB_SUSPEND: return "suspend";
246 }
247 return "?";
248}
249
250/* dump control and status registers */
251static void ohci_dump_status (ohci_t *controller)
252{
253 struct ohci_regs *regs = controller->regs;
254 __u32 temp;
255
256 temp = readl (&regs->revision) & 0xff;
257 if (temp != 0x10)
258 dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
259
260 temp = readl (&regs->control);
261 dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
262 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
263 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
264 (temp & OHCI_CTRL_IR) ? " IR" : "",
265 hcfs2string (temp & OHCI_CTRL_HCFS),
266 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
267 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
268 (temp & OHCI_CTRL_IE) ? " IE" : "",
269 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
270 temp & OHCI_CTRL_CBSR
271 );
272
273 temp = readl (&regs->cmdstatus);
274 dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
275 (temp & OHCI_SOC) >> 16,
276 (temp & OHCI_OCR) ? " OCR" : "",
277 (temp & OHCI_BLF) ? " BLF" : "",
278 (temp & OHCI_CLF) ? " CLF" : "",
279 (temp & OHCI_HCR) ? " HCR" : ""
280 );
281
282 ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
283 ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
284
285 maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
286
287 maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
288 maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
289
290 maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
291 maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
292
293 maybe_print_eds ("donehead", readl (&regs->donehead));
294}
295
296static void ohci_dump_roothub (ohci_t *controller, int verbose)
297{
298 __u32 temp, ndp, i;
299
300 temp = roothub_a (controller);
301 ndp = (temp & RH_A_NDP);
302
303 if (verbose) {
304 dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
305 ((temp & RH_A_POTPGT) >> 24) & 0xff,
306 (temp & RH_A_NOCP) ? " NOCP" : "",
307 (temp & RH_A_OCPM) ? " OCPM" : "",
308 (temp & RH_A_DT) ? " DT" : "",
309 (temp & RH_A_NPS) ? " NPS" : "",
310 (temp & RH_A_PSM) ? " PSM" : "",
311 ndp
312 );
313 temp = roothub_b (controller);
314 dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
315 temp,
316 (temp & RH_B_PPCM) >> 16,
317 (temp & RH_B_DR)
318 );
319 temp = roothub_status (controller);
320 dbg ("roothub.status: %08x%s%s%s%s%s%s",
321 temp,
322 (temp & RH_HS_CRWE) ? " CRWE" : "",
323 (temp & RH_HS_OCIC) ? " OCIC" : "",
324 (temp & RH_HS_LPSC) ? " LPSC" : "",
325 (temp & RH_HS_DRWE) ? " DRWE" : "",
326 (temp & RH_HS_OCI) ? " OCI" : "",
327 (temp & RH_HS_LPS) ? " LPS" : ""
328 );
329 }
330
331 for (i = 0; i < ndp; i++) {
332 temp = roothub_portstatus (controller, i);
333 dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
334 i,
335 temp,
336 (temp & RH_PS_PRSC) ? " PRSC" : "",
337 (temp & RH_PS_OCIC) ? " OCIC" : "",
338 (temp & RH_PS_PSSC) ? " PSSC" : "",
339 (temp & RH_PS_PESC) ? " PESC" : "",
340 (temp & RH_PS_CSC) ? " CSC" : "",
341
342 (temp & RH_PS_LSDA) ? " LSDA" : "",
343 (temp & RH_PS_PPS) ? " PPS" : "",
344 (temp & RH_PS_PRS) ? " PRS" : "",
345 (temp & RH_PS_POCI) ? " POCI" : "",
346 (temp & RH_PS_PSS) ? " PSS" : "",
347
348 (temp & RH_PS_PES) ? " PES" : "",
349 (temp & RH_PS_CCS) ? " CCS" : ""
350 );
351 }
352}
353
354static void ohci_dump (ohci_t *controller, int verbose)
355{
356 dbg ("OHCI controller usb-%s state", controller->slot_name);
357
358 /* dumps some of the state we know about */
359 ohci_dump_status (controller);
360 if (verbose)
361 ep_print_int_eds (controller, "hcca");
362 dbg ("hcca frame #%04x", controller->hcca->frame_no);
363 ohci_dump_roothub (controller, 1);
364}
365
366
367#endif /* DEBUG */
368
369/*-------------------------------------------------------------------------*
370 * Interface functions (URB)
371 *-------------------------------------------------------------------------*/
372
373/* get a transfer request */
374
375int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
376 int transfer_len, struct devrequest *setup, int interval)
377{
378 ohci_t *ohci;
379 ed_t * ed;
380 urb_priv_t *purb_priv;
381 int i, size = 0;
382
383 ohci = &gohci;
384
385 /* when controller's hung, permit only roothub cleanup attempts
386 * such as powering down ports */
387 if (ohci->disabled) {
388 err("sohci_submit_job: EPIPE");
389 return -1;
390 }
391
392 /* every endpoint has a ed, locate and fill it */
393 if (!(ed = ep_add_ed (dev, pipe))) {
394 err("sohci_submit_job: ENOMEM");
395 return -1;
396 }
397
398 /* for the private part of the URB we need the number of TDs (size) */
399 switch (usb_pipetype (pipe)) {
400 case PIPE_BULK: /* one TD for every 4096 Byte */
401 size = (transfer_len - 1) / 4096 + 1;
402 break;
403 case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
404 size = (transfer_len == 0)? 2:
405 (transfer_len - 1) / 4096 + 3;
406 break;
407 }
408
409 if (size >= (N_URB_TD - 1)) {
410 err("need %d TDs, only have %d", size, N_URB_TD);
411 return -1;
412 }
413 purb_priv = &urb_priv;
414 purb_priv->pipe = pipe;
415
416 /* fill the private part of the URB */
417 purb_priv->length = size;
418 purb_priv->ed = ed;
419 purb_priv->actual_length = 0;
420
421 /* allocate the TDs */
422 /* note that td[0] was allocated in ep_add_ed */
423 for (i = 0; i < size; i++) {
424 purb_priv->td[i] = td_alloc (dev);
425 if (!purb_priv->td[i]) {
426 purb_priv->length = i;
427 urb_free_priv (purb_priv);
428 err("sohci_submit_job: ENOMEM");
429 return -1;
430 }
431 }
432
433 if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
434 urb_free_priv (purb_priv);
435 err("sohci_submit_job: EINVAL");
436 return -1;
437 }
438
439 /* link the ed into a chain if is not already */
440 if (ed->state != ED_OPER)
441 ep_link (ohci, ed);
442
443 /* fill the TDs and link it to the ed */
444 td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
445
446 return 0;
447}
448
449/*-------------------------------------------------------------------------*/
450
451#ifdef DEBUG
452/* tell us the current USB frame number */
453
454static int sohci_get_current_frame_number (struct usb_device *usb_dev)
455{
456 ohci_t *ohci = &gohci;
457
458 return m16_swap (ohci->hcca->frame_no);
459}
460#endif
461
462/*-------------------------------------------------------------------------*
463 * ED handling functions
464 *-------------------------------------------------------------------------*/
465
466/* link an ed into one of the HC chains */
467
468static int ep_link (ohci_t *ohci, ed_t *edi)
469{
470 volatile ed_t *ed = edi;
471
472 ed->state = ED_OPER;
473
474 switch (ed->type) {
475 case PIPE_CONTROL:
476 ed->hwNextED = 0;
477 if (ohci->ed_controltail == NULL) {
478 writel (ed, &ohci->regs->ed_controlhead);
479 } else {
480 ohci->ed_controltail->hwNextED = m32_swap (ed);
481 }
482 ed->ed_prev = ohci->ed_controltail;
483 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
484 !ohci->ed_rm_list[1] && !ohci->sleeping) {
485 ohci->hc_control |= OHCI_CTRL_CLE;
486 writel (ohci->hc_control, &ohci->regs->control);
487 }
488 ohci->ed_controltail = edi;
489 break;
490
491 case PIPE_BULK:
492 ed->hwNextED = 0;
493 if (ohci->ed_bulktail == NULL) {
494 writel (ed, &ohci->regs->ed_bulkhead);
495 } else {
496 ohci->ed_bulktail->hwNextED = m32_swap (ed);
497 }
498 ed->ed_prev = ohci->ed_bulktail;
499 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
500 !ohci->ed_rm_list[1] && !ohci->sleeping) {
501 ohci->hc_control |= OHCI_CTRL_BLE;
502 writel (ohci->hc_control, &ohci->regs->control);
503 }
504 ohci->ed_bulktail = edi;
505 break;
506 }
507 return 0;
508}
509
510/*-------------------------------------------------------------------------*/
511
512/* unlink an ed from one of the HC chains.
513 * just the link to the ed is unlinked.
514 * the link from the ed still points to another operational ed or 0
515 * so the HC can eventually finish the processing of the unlinked ed */
516
517static int ep_unlink (ohci_t *ohci, ed_t *ed)
518{
519 ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
520
521 switch (ed->type) {
522 case PIPE_CONTROL:
523 if (ed->ed_prev == NULL) {
524 if (!ed->hwNextED) {
525 ohci->hc_control &= ~OHCI_CTRL_CLE;
526 writel (ohci->hc_control, &ohci->regs->control);
527 }
528 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
529 } else {
530 ed->ed_prev->hwNextED = ed->hwNextED;
531 }
532 if (ohci->ed_controltail == ed) {
533 ohci->ed_controltail = ed->ed_prev;
534 } else {
535 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
536 }
537 break;
538
539 case PIPE_BULK:
540 if (ed->ed_prev == NULL) {
541 if (!ed->hwNextED) {
542 ohci->hc_control &= ~OHCI_CTRL_BLE;
543 writel (ohci->hc_control, &ohci->regs->control);
544 }
545 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
546 } else {
547 ed->ed_prev->hwNextED = ed->hwNextED;
548 }
549 if (ohci->ed_bulktail == ed) {
550 ohci->ed_bulktail = ed->ed_prev;
551 } else {
552 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
553 }
554 break;
555 }
556 ed->state = ED_UNLINK;
557 return 0;
558}
559
560
561/*-------------------------------------------------------------------------*/
562
563/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
564 * but the USB stack is a little bit stateless so we do it at every transaction
565 * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
566 * in all other cases the state is left unchanged
567 * the ed info fields are setted anyway even though most of them should not change */
568
569static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
570{
571 td_t *td;
572 ed_t *ed_ret;
573 volatile ed_t *ed;
574
575 ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
576 (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
577
578 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
579 err("ep_add_ed: pending delete");
580 /* pending delete request */
581 return NULL;
582 }
583
584 if (ed->state == ED_NEW) {
585 ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
586 /* dummy td; end of td list for ed */
587 td = td_alloc (usb_dev);
588 ed->hwTailP = m32_swap (td);
589 ed->hwHeadP = ed->hwTailP;
590 ed->state = ED_UNLINK;
591 ed->type = usb_pipetype (pipe);
592 ohci_dev.ed_cnt++;
593 }
594
595 ed->hwINFO = m32_swap (usb_pipedevice (pipe)
596 | usb_pipeendpoint (pipe) << 7
597 | (usb_pipeisoc (pipe)? 0x8000: 0)
598 | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
599 | usb_pipeslow (pipe) << 13
600 | usb_maxpacket (usb_dev, pipe) << 16);
601
602 return ed_ret;
603}
604
605/*-------------------------------------------------------------------------*
606 * TD handling functions
607 *-------------------------------------------------------------------------*/
608
609/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
610
611static void td_fill (ohci_t *ohci, unsigned int info,
612 void *data, int len,
613 struct usb_device *dev, int index, urb_priv_t *urb_priv)
614{
615 volatile td_t *td, *td_pt;
616#ifdef OHCI_FILL_TRACE
617 int i;
618#endif
619
620 if (index > urb_priv->length) {
621 err("index > length");
622 return;
623 }
624 /* use this td as the next dummy */
625 td_pt = urb_priv->td [index];
626 td_pt->hwNextTD = 0;
627
628 /* fill the old dummy TD */
629 td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
630
631 td->ed = urb_priv->ed;
632 td->next_dl_td = NULL;
633 td->index = index;
634 td->data = (__u32)data;
635#ifdef OHCI_FILL_TRACE
636 if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
637 for (i = 0; i < len; i++)
638 printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
639 printf("\n");
640 }
641#endif
642 if (!len)
643 data = 0;
644
645 td->hwINFO = m32_swap (info);
646 td->hwCBP = m32_swap (data);
647 if (data)
648 td->hwBE = m32_swap (data + len - 1);
649 else
650 td->hwBE = 0;
651 td->hwNextTD = m32_swap (td_pt);
652 td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
653
654 /* append to queue */
655 td->ed->hwTailP = td->hwNextTD;
656}
657
658/*-------------------------------------------------------------------------*/
659
660/* prepare all TDs of a transfer */
661
662static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
663 int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
664{
665 ohci_t *ohci = &gohci;
666 int data_len = transfer_len;
667 void *data;
668 int cnt = 0;
669 __u32 info = 0;
670 unsigned int toggle = 0;
671
672 /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
673 if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
674 toggle = TD_T_TOGGLE;
675 } else {
676 toggle = TD_T_DATA0;
677 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
678 }
679 urb->td_cnt = 0;
680 if (data_len)
681 data = buffer;
682 else
683 data = 0;
684
685 switch (usb_pipetype (pipe)) {
686 case PIPE_BULK:
687 info = usb_pipeout (pipe)?
688 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
689 while(data_len > 4096) {
690 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
691 data += 4096; data_len -= 4096; cnt++;
692 }
693 info = usb_pipeout (pipe)?
694 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
695 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
696 cnt++;
697
698 if (!ohci->sleeping)
699 writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
700 break;
701
702 case PIPE_CONTROL:
703 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
704 td_fill (ohci, info, setup, 8, dev, cnt++, urb);
705 if (data_len > 0) {
706 info = usb_pipeout (pipe)?
707 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
708 /* NOTE: mishandles transfers >8K, some >4K */
709 td_fill (ohci, info, data, data_len, dev, cnt++, urb);
710 }
711 info = usb_pipeout (pipe)?
712 TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
713 td_fill (ohci, info, data, 0, dev, cnt++, urb);
714 if (!ohci->sleeping)
715 writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
716 break;
717 }
718 if (urb->length != cnt)
719 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
720}
721
722/*-------------------------------------------------------------------------*
723 * Done List handling functions
724 *-------------------------------------------------------------------------*/
725
726
727/* calculate the transfer length and update the urb */
728
729static void dl_transfer_length(td_t * td)
730{
731 __u32 tdINFO, tdBE, tdCBP;
732 urb_priv_t *lurb_priv = &urb_priv;
733
734 tdINFO = m32_swap (td->hwINFO);
735 tdBE = m32_swap (td->hwBE);
736 tdCBP = m32_swap (td->hwCBP);
737
738
739 if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
740 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
741 if (tdBE != 0) {
742 if (td->hwCBP == 0)
743 lurb_priv->actual_length += tdBE - td->data + 1;
744 else
745 lurb_priv->actual_length += tdCBP - td->data;
746 }
747 }
748}
749
750/*-------------------------------------------------------------------------*/
751
752/* replies to the request have to be on a FIFO basis so
753 * we reverse the reversed done-list */
754
755static td_t * dl_reverse_done_list (ohci_t *ohci)
756{
757 __u32 td_list_hc;
758 td_t *td_rev = NULL;
759 td_t *td_list = NULL;
760 urb_priv_t *lurb_priv = NULL;
761
762 td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
763 ohci->hcca->done_head = 0;
764
765 while (td_list_hc) {
766 td_list = (td_t *)td_list_hc;
767
768 if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
769 lurb_priv = &urb_priv;
770 dbg(" USB-error/status: %x : %p",
771 TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
772 if (td_list->ed->hwHeadP & m32_swap (0x1)) {
773 if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
774 td_list->ed->hwHeadP =
775 (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
776 (td_list->ed->hwHeadP & m32_swap (0x2));
777 lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
778 } else
779 td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
780 }
781 }
782
783 td_list->next_dl_td = td_rev;
784 td_rev = td_list;
785 td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
786 }
787 return td_list;
788}
789
790/*-------------------------------------------------------------------------*/
791
792/* td done list */
793static int dl_done_list (ohci_t *ohci, td_t *td_list)
794{
795 td_t *td_list_next = NULL;
796 ed_t *ed;
797 int cc = 0;
798 int stat = 0;
799 /* urb_t *urb; */
800 urb_priv_t *lurb_priv;
801 __u32 tdINFO, edHeadP, edTailP;
802
803 while (td_list) {
804 td_list_next = td_list->next_dl_td;
805
806 lurb_priv = &urb_priv;
807 tdINFO = m32_swap (td_list->hwINFO);
808
809 ed = td_list->ed;
810
811 dl_transfer_length(td_list);
812
813 /* error code of transfer */
814 cc = TD_CC_GET (tdINFO);
815 if (cc != 0) {
816 dbg("ConditionCode %#x", cc);
817 stat = cc_to_error[cc];
818 }
819
820 if (ed->state != ED_NEW) {
821 edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
822 edTailP = m32_swap (ed->hwTailP);
823
824 /* unlink eds if they are not busy */
825 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
826 ep_unlink (ohci, ed);
827 }
828
829 td_list = td_list_next;
830 }
831 return stat;
832}
833
834/*-------------------------------------------------------------------------*
835 * Virtual Root Hub
836 *-------------------------------------------------------------------------*/
837
838/* Device descriptor */
839static __u8 root_hub_dev_des[] =
840{
841 0x12, /* __u8 bLength; */
842 0x01, /* __u8 bDescriptorType; Device */
843 0x10, /* __u16 bcdUSB; v1.1 */
844 0x01,
845 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
846 0x00, /* __u8 bDeviceSubClass; */
847 0x00, /* __u8 bDeviceProtocol; */
848 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
849 0x00, /* __u16 idVendor; */
850 0x00,
851 0x00, /* __u16 idProduct; */
852 0x00,
853 0x00, /* __u16 bcdDevice; */
854 0x00,
855 0x00, /* __u8 iManufacturer; */
856 0x01, /* __u8 iProduct; */
857 0x00, /* __u8 iSerialNumber; */
858 0x01 /* __u8 bNumConfigurations; */
859};
860
861
862/* Configuration descriptor */
863static __u8 root_hub_config_des[] =
864{
865 0x09, /* __u8 bLength; */
866 0x02, /* __u8 bDescriptorType; Configuration */
867 0x19, /* __u16 wTotalLength; */
868 0x00,
869 0x01, /* __u8 bNumInterfaces; */
870 0x01, /* __u8 bConfigurationValue; */
871 0x00, /* __u8 iConfiguration; */
872 0x40, /* __u8 bmAttributes;
873 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
874 0x00, /* __u8 MaxPower; */
875
876 /* interface */
877 0x09, /* __u8 if_bLength; */
878 0x04, /* __u8 if_bDescriptorType; Interface */
879 0x00, /* __u8 if_bInterfaceNumber; */
880 0x00, /* __u8 if_bAlternateSetting; */
881 0x01, /* __u8 if_bNumEndpoints; */
882 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
883 0x00, /* __u8 if_bInterfaceSubClass; */
884 0x00, /* __u8 if_bInterfaceProtocol; */
885 0x00, /* __u8 if_iInterface; */
886
887 /* endpoint */
888 0x07, /* __u8 ep_bLength; */
889 0x05, /* __u8 ep_bDescriptorType; Endpoint */
890 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
891 0x03, /* __u8 ep_bmAttributes; Interrupt */
892 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
893 0x00,
894 0xff /* __u8 ep_bInterval; 255 ms */
895};
896
897static unsigned char root_hub_str_index0[] =
898{
899 0x04, /* __u8 bLength; */
900 0x03, /* __u8 bDescriptorType; String-descriptor */
901 0x09, /* __u8 lang ID */
902 0x04, /* __u8 lang ID */
903};
904
905static unsigned char root_hub_str_index1[] =
906{
907 28, /* __u8 bLength; */
908 0x03, /* __u8 bDescriptorType; String-descriptor */
909 'O', /* __u8 Unicode */
910 0, /* __u8 Unicode */
911 'H', /* __u8 Unicode */
912 0, /* __u8 Unicode */
913 'C', /* __u8 Unicode */
914 0, /* __u8 Unicode */
915 'I', /* __u8 Unicode */
916 0, /* __u8 Unicode */
917 ' ', /* __u8 Unicode */
918 0, /* __u8 Unicode */
919 'R', /* __u8 Unicode */
920 0, /* __u8 Unicode */
921 'o', /* __u8 Unicode */
922 0, /* __u8 Unicode */
923 'o', /* __u8 Unicode */
924 0, /* __u8 Unicode */
925 't', /* __u8 Unicode */
926 0, /* __u8 Unicode */
927 ' ', /* __u8 Unicode */
928 0, /* __u8 Unicode */
929 'H', /* __u8 Unicode */
930 0, /* __u8 Unicode */
931 'u', /* __u8 Unicode */
932 0, /* __u8 Unicode */
933 'b', /* __u8 Unicode */
934 0, /* __u8 Unicode */
935};
936
937/* Hub class-specific descriptor is constructed dynamically */
938
939
940/*-------------------------------------------------------------------------*/
941
942#define OK(x) len = (x); break
943#ifdef DEBUG
944#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
945#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
946#else
947#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
948#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
949#endif
950#define RD_RH_STAT roothub_status(&gohci)
951#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
952
953/* request to virtual root hub */
954
955static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
956 int transfer_len, struct devrequest *cmd)
957{
958 void * data = buffer;
959 int leni = transfer_len;
960 int len = 0;
961 int stat = 0;
962 __u32 datab[4];
963 __u8 *data_buf = (__u8 *)datab;
964 __u16 bmRType_bReq;
965 __u16 wValue;
966 __u16 wIndex;
967 __u16 wLength;
968
969#ifdef DEBUG
970urb_priv.actual_length = 0;
971pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
972#else
973 wait_ms(1);
974#endif
975 if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
976 info("Root-Hub submit IRQ: NOT implemented");
977 return 0;
978 }
979
980 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
981 wValue = m16_swap (cmd->value);
982 wIndex = m16_swap (cmd->index);
983 wLength = m16_swap (cmd->length);
984
985 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
986 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
987
988 switch (bmRType_bReq) {
989 /* Request Destination:
990 without flags: Device,
991 RH_INTERFACE: interface,
992 RH_ENDPOINT: endpoint,
993 RH_CLASS means HUB here,
994 RH_OTHER | RH_CLASS almost ever means HUB_PORT here
995 */
996
997 case RH_GET_STATUS:
998 *(__u16 *) data_buf = m16_swap (1); OK (2);
999 case RH_GET_STATUS | RH_INTERFACE:
1000 *(__u16 *) data_buf = m16_swap (0); OK (2);
1001 case RH_GET_STATUS | RH_ENDPOINT:
1002 *(__u16 *) data_buf = m16_swap (0); OK (2);
1003 case RH_GET_STATUS | RH_CLASS:
1004 *(__u32 *) data_buf = m32_swap (
1005 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
1006 OK (4);
1007 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
1008 *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
1009
1010 case RH_CLEAR_FEATURE | RH_ENDPOINT:
1011 switch (wValue) {
1012 case (RH_ENDPOINT_STALL): OK (0);
1013 }
1014 break;
1015
1016 case RH_CLEAR_FEATURE | RH_CLASS:
1017 switch (wValue) {
1018 case RH_C_HUB_LOCAL_POWER:
1019 OK(0);
1020 case (RH_C_HUB_OVER_CURRENT):
1021 WR_RH_STAT(RH_HS_OCIC); OK (0);
1022 }
1023 break;
1024
1025 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
1026 switch (wValue) {
1027 case (RH_PORT_ENABLE):
1028 WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
1029 case (RH_PORT_SUSPEND):
1030 WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
1031 case (RH_PORT_POWER):
1032 WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
1033 case (RH_C_PORT_CONNECTION):
1034 WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
1035 case (RH_C_PORT_ENABLE):
1036 WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
1037 case (RH_C_PORT_SUSPEND):
1038 WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
1039 case (RH_C_PORT_OVER_CURRENT):
1040 WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
1041 case (RH_C_PORT_RESET):
1042 WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
1043 }
1044 break;
1045
1046 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
1047 switch (wValue) {
1048 case (RH_PORT_SUSPEND):
1049 WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
1050 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
1051 if (RD_RH_PORTSTAT & RH_PS_CCS)
1052 WR_RH_PORTSTAT (RH_PS_PRS);
1053 OK (0);
1054 case (RH_PORT_POWER):
1055 WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
1056 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
1057 if (RD_RH_PORTSTAT & RH_PS_CCS)
1058 WR_RH_PORTSTAT (RH_PS_PES );
1059 OK (0);
1060 }
1061 break;
1062
1063 case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
1064
1065 case RH_GET_DESCRIPTOR:
1066 switch ((wValue & 0xff00) >> 8) {
1067 case (0x01): /* device descriptor */
1068 len = min_t(unsigned int,
1069 leni,
1070 min_t(unsigned int,
1071 sizeof (root_hub_dev_des),
1072 wLength));
1073 data_buf = root_hub_dev_des; OK(len);
1074 case (0x02): /* configuration descriptor */
1075 len = min_t(unsigned int,
1076 leni,
1077 min_t(unsigned int,
1078 sizeof (root_hub_config_des),
1079 wLength));
1080 data_buf = root_hub_config_des; OK(len);
1081 case (0x03): /* string descriptors */
1082 if(wValue==0x0300) {
1083 len = min_t(unsigned int,
1084 leni,
1085 min_t(unsigned int,
1086 sizeof (root_hub_str_index0),
1087 wLength));
1088 data_buf = root_hub_str_index0;
1089 OK(len);
1090 }
1091 if(wValue==0x0301) {
1092 len = min_t(unsigned int,
1093 leni,
1094 min_t(unsigned int,
1095 sizeof (root_hub_str_index1),
1096 wLength));
1097 data_buf = root_hub_str_index1;
1098 OK(len);
1099 }
1100 default:
1101 stat = USB_ST_STALLED;
1102 }
1103 break;
1104
1105 case RH_GET_DESCRIPTOR | RH_CLASS:
1106 {
1107 __u32 temp = roothub_a (&gohci);
1108
1109 data_buf [0] = 9; /* min length; */
1110 data_buf [1] = 0x29;
1111 data_buf [2] = temp & RH_A_NDP;
1112 data_buf [3] = 0;
1113 if (temp & RH_A_PSM) /* per-port power switching? */
1114 data_buf [3] |= 0x1;
1115 if (temp & RH_A_NOCP) /* no overcurrent reporting? */
1116 data_buf [3] |= 0x10;
1117 else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
1118 data_buf [3] |= 0x8;
1119
1120 /* corresponds to data_buf[4-7] */
1121 datab [1] = 0;
1122 data_buf [5] = (temp & RH_A_POTPGT) >> 24;
1123 temp = roothub_b (&gohci);
1124 data_buf [7] = temp & RH_B_DR;
1125 if (data_buf [2] < 7) {
1126 data_buf [8] = 0xff;
1127 } else {
1128 data_buf [0] += 2;
1129 data_buf [8] = (temp & RH_B_DR) >> 8;
1130 data_buf [10] = data_buf [9] = 0xff;
1131 }
1132
1133 len = min_t(unsigned int, leni,
1134 min_t(unsigned int, data_buf [0], wLength));
1135 OK (len);
1136 }
1137
1138 case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
1139
1140 case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
1141
1142 default:
1143 dbg ("unsupported root hub command");
1144 stat = USB_ST_STALLED;
1145 }
1146
1147#ifdef DEBUG
1148 ohci_dump_roothub (&gohci, 1);
1149#else
1150 wait_ms(1);
1151#endif
1152
1153 len = min_t(int, len, leni);
1154 if (data != data_buf)
1155 memcpy (data, data_buf, len);
1156 dev->act_len = len;
1157 dev->status = stat;
1158
1159#ifdef DEBUG
1160 if (transfer_len)
1161 urb_priv.actual_length = transfer_len;
1162 pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
1163#else
1164 wait_ms(1);
1165#endif
1166
1167 return stat;
1168}
1169
1170/*-------------------------------------------------------------------------*/
1171
1172/* common code for handling submit messages - used for all but root hub */
1173/* accesses. */
1174int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1175 int transfer_len, struct devrequest *setup, int interval)
1176{
1177 int stat = 0;
1178 int maxsize = usb_maxpacket(dev, pipe);
1179 int timeout;
1180
1181#ifdef DEBUG
1182 urb_priv.actual_length = 0;
1183 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1184#else
1185 wait_ms(1);
1186#endif
1187 if (!maxsize) {
1188 err("submit_common_message: pipesize for pipe %lx is zero",
1189 pipe);
1190 return -1;
1191 }
1192
1193 if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
1194 err("sohci_submit_job failed");
1195 return -1;
1196 }
1197
1198 wait_ms(10);
1199 /* ohci_dump_status(&gohci); */
a43278a4
WD		 1200
1201 /* allow more time for a BULK device to react - some are slow */
1202#define BULK_TO 2000 /* timeout in milliseconds */
1203 if (usb_pipetype (pipe) == PIPE_BULK)
1204 timeout = BULK_TO;
1205 else
1206 timeout = 100;
1207
149dded2 1208 /* wait for it to complete */
149dded2
WD		 1209 for (;;) {
1210 /* check whether the controller is done */
1211 stat = hc_interrupt();
1212 if (stat < 0) {
1213 stat = 1;
1214 break;
1215 }
1216 if (stat >= 0 && stat != 0xff) {
1217 /* 0xff is returned for an SF-interrupt */
1218 break;
1219 }
1220 if (--timeout) {
1221 wait_ms(1);
1222 } else {
1223 err("CTL:TIMEOUT");
1224 stat = 1;
1225 break;
1226 }
1227 }
1228 dev->status = stat;
1229 dev->act_len = transfer_len;
1230
1231#ifdef DEBUG
1232 pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
1233#else
1234 wait_ms(1);
1235#endif
1236
1237 /* free TDs in urb_priv */
1238 urb_free_priv (&urb_priv);
1239 return 0;
1240}
1241
1242/* submit routines called from usb.c */
1243int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1244 int transfer_len)
1245{
1246 info("submit_bulk_msg");
1247 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
1248}
1249
1250int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1251 int transfer_len, struct devrequest *setup)
1252{
1253 int maxsize = usb_maxpacket(dev, pipe);
1254
1255 info("submit_control_msg");
1256#ifdef DEBUG
1257 urb_priv.actual_length = 0;
1258 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1259#else
1260 wait_ms(1);
1261#endif
1262 if (!maxsize) {
1263 err("submit_control_message: pipesize for pipe %lx is zero",
1264 pipe);
1265 return -1;
1266 }
1267 if (((pipe >> 8) & 0x7f) == gohci.rh.devnum)
1268 /* root hub - redirect */
1269 return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
1270 setup);
1271
1272 return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
1273}
1274
1275int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1276 int transfer_len, int interval)
1277{
1278 info("submit_int_msg");
1279 return -1;
1280}
1281
1282/*-------------------------------------------------------------------------*
1283 * HC functions
1284 *-------------------------------------------------------------------------*/
1285
1286/* reset the HC and BUS */
1287
1288static int hc_reset (ohci_t *ohci)
1289{
1290 int timeout = 30;
1291 int smm_timeout = 50; /* 0,5 sec */
1292
1293 if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
1294 writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
1295 info("USB HC TakeOver from SMM");
1296 while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
1297 wait_ms (10);
1298 if (--smm_timeout == 0) {
1299 err("USB HC TakeOver failed!");
1300 return -1;
1301 }
1302 }
1303 }
1304
1305 /* Disable HC interrupts */
1306 writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
1307
1308 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
1309 ohci->slot_name,
1310 readl (&ohci->regs->control));
1311
1312 /* Reset USB (needed by some controllers) */
1313 writel (0, &ohci->regs->control);
1314
1315 /* HC Reset requires max 10 us delay */
1316 writel (OHCI_HCR, &ohci->regs->cmdstatus);
1317 while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1318 if (--timeout == 0) {
1319 err("USB HC reset timed out!");
1320 return -1;
1321 }
1322 udelay (1);
1323 }
1324 return 0;
1325}
1326
1327/*-------------------------------------------------------------------------*/
1328
1329/* Start an OHCI controller, set the BUS operational
1330 * enable interrupts
1331 * connect the virtual root hub */
1332
1333static int hc_start (ohci_t * ohci)
1334{
1335 __u32 mask;
1336 unsigned int fminterval;
1337
1338 ohci->disabled = 1;
1339
1340 /* Tell the controller where the control and bulk lists are
1341 * The lists are empty now. */
1342
1343 writel (0, &ohci->regs->ed_controlhead);
1344 writel (0, &ohci->regs->ed_bulkhead);
1345
1346 writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
1347
1348 fminterval = 0x2edf;
1349 writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
1350 fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
1351 writel (fminterval, &ohci->regs->fminterval);
1352 writel (0x628, &ohci->regs->lsthresh);
1353
1354 /* start controller operations */
1355 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
1356 ohci->disabled = 0;
1357 writel (ohci->hc_control, &ohci->regs->control);
1358
1359 /* Choose the interrupts we care about now, others later on demand */
1360 mask = OHCI_INTR_MIE | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
1361 writel (mask, &ohci->regs->intrstatus);
1362
1363#ifdef OHCI_USE_NPS
1364 /* required for AMD-756 and some Mac platforms */
1365 writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
1366 &ohci->regs->roothub.a);
1367 writel (RH_HS_LPSC, &ohci->regs->roothub.status);
1368#endif /* OHCI_USE_NPS */
1369
1370#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
1371 /* POTPGT delay is bits 24-31, in 2 ms units. */
1372 mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
1373
1374 /* connect the virtual root hub */
1375 ohci->rh.devnum = 0;
1376
1377 return 0;
1378}
1379
1380/*-------------------------------------------------------------------------*/
1381
1382/* an interrupt happens */
1383
1384static int
1385hc_interrupt (void)
1386{
1387 ohci_t *ohci = &gohci;
1388 struct ohci_regs *regs = ohci->regs;
1389 int ints;
1390 int stat = -1;
1391
1392 if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
1393 ints = OHCI_INTR_WDH;
1394 } else {
1395 ints = readl (&regs->intrstatus);
1396 }
1397
1398 /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
1399
1400 if (ints & OHCI_INTR_UE) {
1401 ohci->disabled++;
1402 err ("OHCI Unrecoverable Error, controller usb-%s disabled",
1403 ohci->slot_name);
1404 /* e.g. due to PCI Master/Target Abort */
1405
1406#ifdef DEBUG
1407 ohci_dump (ohci, 1);
1408#else
1409 wait_ms(1);
1410#endif
1411 /* FIXME: be optimistic, hope that bug won't repeat often. */
1412 /* Make some non-interrupt context restart the controller. */
1413 /* Count and limit the retries though; either hardware or */
1414 /* software errors can go forever... */
1415 hc_reset (ohci);
1416 return -1;
1417 }
1418
1419 if (ints & OHCI_INTR_WDH) {
1420 wait_ms(1);
1421 writel (OHCI_INTR_WDH, &regs->intrdisable);
1422 stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
1423 writel (OHCI_INTR_WDH, &regs->intrenable);
1424 }
1425
1426 if (ints & OHCI_INTR_SO) {
1427 dbg("USB Schedule overrun\n");
1428 writel (OHCI_INTR_SO, &regs->intrenable);
1429 stat = -1;
1430 }
1431
1432 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1433 if (ints & OHCI_INTR_SF) {
1434 unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
1435 wait_ms(1);
1436 writel (OHCI_INTR_SF, &regs->intrdisable);
1437 if (ohci->ed_rm_list[frame] != NULL)
1438 writel (OHCI_INTR_SF, &regs->intrenable);
1439 stat = 0xff;
1440 }
1441
1442 writel (ints, &regs->intrstatus);
1443 return stat;
1444}
1445
1446/*-------------------------------------------------------------------------*/
1447
1448/*-------------------------------------------------------------------------*/
1449
1450/* De-allocate all resources.. */
1451
1452static void hc_release_ohci (ohci_t *ohci)
1453{
1454 dbg ("USB HC release ohci usb-%s", ohci->slot_name);
1455
1456 if (!ohci->disabled)
1457 hc_reset (ohci);
1458}
1459
1460/*-------------------------------------------------------------------------*/
1461
1462/*
1463 * low level initalisation routine, called from usb.c
1464 */
1465static char ohci_inited = 0;
1466
1467int usb_lowlevel_init(void)
1468{
1469 S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
1470 S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
1471
1472 /*
1473 * Set the 48 MHz UPLL clocking. Values are taken from
1474 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
1475 */
1476 clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
1477 gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
1478
1479 /*
1480 * Enable USB host clock.
1481 */
1482 clk_power->CLKCON |= (1 << 4);
1483
1484 memset (&gohci, 0, sizeof (ohci_t));
1485 memset (&urb_priv, 0, sizeof (urb_priv_t));
1486
1487 /* align the storage */
1488 if ((__u32)&ghcca[0] & 0xff) {
1489 err("HCCA not aligned!!");
1490 return -1;
1491 }
1492 phcca = &ghcca[0];
1493 info("aligned ghcca %p", phcca);
1494 memset(&ohci_dev, 0, sizeof(struct ohci_device));
1495 if ((__u32)&ohci_dev.ed[0] & 0x7) {
1496 err("EDs not aligned!!");
1497 return -1;
1498 }
1499 memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
1500 if ((__u32)gtd & 0x7) {
1501 err("TDs not aligned!!");
1502 return -1;
1503 }
1504 ptd = gtd;
1505 gohci.hcca = phcca;
1506 memset (phcca, 0, sizeof (struct ohci_hcca));
1507
1508 gohci.disabled = 1;
1509 gohci.sleeping = 0;
1510 gohci.irq = -1;
1511 gohci.regs = (struct ohci_regs *)S3C24X0_USB_HOST_BASE;
1512
1513 gohci.flags = 0;
1514 gohci.slot_name = "s3c2400";
1515
1516 if (hc_reset (&gohci) < 0) {
1517 hc_release_ohci (&gohci);
1518 /* Initialization failed */
1519 clk_power->CLKCON &= ~(1 << 4);
1520 return -1;
1521 }
1522
1523 /* FIXME this is a second HC reset; why?? */
1524 writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
1525 wait_ms (10);
1526
1527 if (hc_start (&gohci) < 0) {
1528 err ("can't start usb-%s", gohci.slot_name);
1529 hc_release_ohci (&gohci);
1530 /* Initialization failed */
1531 clk_power->CLKCON &= ~(1 << 4);
1532 return -1;
1533 }
1534
1535#ifdef DEBUG
1536 ohci_dump (&gohci, 1);
1537#else
1538 wait_ms(1);
1539#endif
1540 ohci_inited = 1;
1541 return 0;
1542}
1543
1544int usb_lowlevel_stop(void)
1545{
1546 S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
1547
1548 /* this gets called really early - before the controller has */
1549 /* even been initialized! */
1550 if (!ohci_inited)
1551 return 0;
1552 /* TODO release any interrupts, etc. */
1553 /* call hc_release_ohci() here ? */
1554 hc_reset (&gohci);
1555 /* may not want to do this */
1556 clk_power->CLKCON &= ~(1 << 4);
1557 return 0;
1558}
1559
1560#endif /* CONFIG_USB_OHCI */
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