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2e5983d2 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * | |
5 | * (C) Copyright 2002 | |
6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | * Marius Groeger <mgroeger@sysgo.de> | |
8 | * | |
9 | * (C) Copyright 2002 | |
10 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
11 | * Alex Zuepke <azu@sysgo.de> | |
12 | * | |
13 | * (C) Copyright 2002 | |
14 | * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> | |
15 | * | |
16 | * See file CREDITS for list of people who contributed to this | |
17 | * project. | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License as | |
21 | * published by the Free Software Foundation; either version 2 of | |
22 | * the License, or (at your option) any later version. | |
23 | * | |
24 | * This program is distributed in the hope that it will be useful, | |
25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
27 | * GNU General Public License for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License | |
30 | * along with this program; if not, write to the Free Software | |
31 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
32 | * MA 02111-1307 USA | |
33 | */ | |
34 | ||
35 | #include <common.h> | |
36 | #include <arm925t.h> | |
37 | #include <configs/omap1510.h> | |
38 | ||
39 | #include <asm/proc-armv/ptrace.h> | |
40 | ||
41 | extern void reset_cpu(ulong addr); | |
42 | #define TIMER_LOAD_VAL 0xffffffff | |
43 | ||
44 | /* macro to read the 32 bit timer */ | |
45 | #define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8)) | |
46 | ||
47 | #ifdef CONFIG_USE_IRQ | |
48 | /* enable IRQ interrupts */ | |
49 | void enable_interrupts (void) | |
50 | { | |
51 | unsigned long temp; | |
52 | __asm__ __volatile__("mrs %0, cpsr\n" | |
53 | "bic %0, %0, #0x80\n" | |
54 | "msr cpsr_c, %0" | |
55 | : "=r" (temp) | |
56 | : | |
57 | : "memory"); | |
58 | } | |
59 | ||
60 | ||
61 | /* | |
62 | * disable IRQ/FIQ interrupts | |
63 | * returns true if interrupts had been enabled before we disabled them | |
64 | */ | |
65 | int disable_interrupts (void) | |
66 | { | |
67 | unsigned long old,temp; | |
68 | __asm__ __volatile__("mrs %0, cpsr\n" | |
69 | "orr %1, %0, #0xc0\n" | |
70 | "msr cpsr_c, %1" | |
71 | : "=r" (old), "=r" (temp) | |
72 | : | |
73 | : "memory"); | |
74 | return (old & 0x80) == 0; | |
75 | } | |
76 | #else | |
77 | void enable_interrupts (void) | |
78 | { | |
79 | return; | |
80 | } | |
81 | int disable_interrupts (void) | |
82 | { | |
83 | return 0; | |
84 | } | |
85 | #endif | |
86 | ||
87 | ||
88 | ||
89 | void bad_mode (void) | |
90 | { | |
91 | panic ("Resetting CPU ...\n"); | |
92 | reset_cpu (0); | |
93 | } | |
94 | ||
95 | void show_regs (struct pt_regs *regs) | |
96 | { | |
97 | unsigned long flags; | |
98 | const char *processor_modes[] = { | |
99 | "USER_26", "FIQ_26", "IRQ_26", "SVC_26", | |
100 | "UK4_26", "UK5_26", "UK6_26", "UK7_26", | |
101 | "UK8_26", "UK9_26", "UK10_26", "UK11_26", | |
102 | "UK12_26", "UK13_26", "UK14_26", "UK15_26", | |
103 | "USER_32", "FIQ_32", "IRQ_32", "SVC_32", | |
104 | "UK4_32", "UK5_32", "UK6_32", "ABT_32", | |
105 | "UK8_32", "UK9_32", "UK10_32", "UND_32", | |
106 | "UK12_32", "UK13_32", "UK14_32", "SYS_32", | |
107 | }; | |
108 | ||
109 | flags = condition_codes (regs); | |
110 | ||
111 | printf ("pc : [<%08lx>] lr : [<%08lx>]\n" | |
112 | "sp : %08lx ip : %08lx fp : %08lx\n", | |
113 | instruction_pointer (regs), | |
114 | regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); | |
115 | printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", | |
116 | regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); | |
117 | printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", | |
118 | regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); | |
119 | printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", | |
120 | regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); | |
121 | printf ("Flags: %c%c%c%c", | |
122 | flags & CC_N_BIT ? 'N' : 'n', | |
123 | flags & CC_Z_BIT ? 'Z' : 'z', | |
124 | flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); | |
125 | printf (" IRQs %s FIQs %s Mode %s%s\n", | |
126 | interrupts_enabled (regs) ? "on" : "off", | |
127 | fast_interrupts_enabled (regs) ? "on" : "off", | |
128 | processor_modes[processor_mode (regs)], | |
129 | thumb_mode (regs) ? " (T)" : ""); | |
130 | } | |
131 | ||
132 | void do_undefined_instruction (struct pt_regs *pt_regs) | |
133 | { | |
134 | printf ("undefined instruction\n"); | |
135 | show_regs (pt_regs); | |
136 | bad_mode (); | |
137 | } | |
138 | ||
139 | void do_software_interrupt (struct pt_regs *pt_regs) | |
140 | { | |
141 | printf ("software interrupt\n"); | |
142 | show_regs (pt_regs); | |
143 | bad_mode (); | |
144 | } | |
145 | ||
146 | void do_prefetch_abort (struct pt_regs *pt_regs) | |
147 | { | |
148 | printf ("prefetch abort\n"); | |
149 | show_regs (pt_regs); | |
150 | bad_mode (); | |
151 | } | |
152 | ||
153 | void do_data_abort (struct pt_regs *pt_regs) | |
154 | { | |
155 | printf ("data abort\n"); | |
156 | show_regs (pt_regs); | |
157 | bad_mode (); | |
158 | } | |
159 | ||
160 | void do_not_used (struct pt_regs *pt_regs) | |
161 | { | |
162 | printf ("not used\n"); | |
163 | show_regs (pt_regs); | |
164 | bad_mode (); | |
165 | } | |
166 | ||
167 | void do_fiq (struct pt_regs *pt_regs) | |
168 | { | |
169 | printf ("fast interrupt request\n"); | |
170 | show_regs (pt_regs); | |
171 | bad_mode (); | |
172 | } | |
173 | ||
174 | void do_irq (struct pt_regs *pt_regs) | |
175 | { | |
176 | printf ("interrupt request\n"); | |
177 | show_regs (pt_regs); | |
178 | bad_mode (); | |
179 | } | |
180 | ||
181 | static ulong timestamp; | |
182 | static ulong lastdec; | |
183 | ||
184 | /* nothing really to do with interrupts, just starts up a counter. */ | |
185 | int interrupt_init (void) | |
186 | { | |
187 | int32_t val; | |
188 | ||
189 | *((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL; | |
190 | val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT); | |
191 | *((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val; | |
192 | return (0); | |
193 | } | |
194 | ||
195 | /* | |
196 | * timer without interrupts | |
197 | */ | |
198 | ||
199 | void reset_timer (void) | |
200 | { | |
201 | reset_timer_masked (); | |
202 | } | |
203 | ||
204 | ulong get_timer (ulong base) | |
205 | { | |
206 | return get_timer_masked () - base; | |
207 | } | |
208 | ||
209 | void set_timer (ulong t) | |
210 | { | |
211 | timestamp = t; | |
212 | } | |
213 | ||
214 | /* very rough timer... */ | |
215 | void udelay (unsigned long usec) | |
216 | { | |
217 | #ifdef CONFIG_INNOVATOROMAP1510 | |
218 | #define LOOPS_PER_MSEC 60 /* tuned on omap1510 */ | |
219 | volatile int i, time_remaining = LOOPS_PER_MSEC * usec; | |
220 | ||
221 | for (i = time_remaining; i > 0; i--) { | |
222 | } | |
223 | #else | |
224 | ||
225 | ulong tmo; | |
226 | ||
227 | tmo = usec / 1000; | |
228 | tmo *= CFG_HZ; | |
229 | tmo /= 1000; | |
230 | ||
231 | tmo += get_timer (0); | |
232 | ||
233 | while (get_timer_masked () < tmo) | |
234 | /*NOP*/; | |
235 | #endif | |
236 | } | |
237 | ||
238 | void reset_timer_masked (void) | |
239 | { | |
240 | /* reset time */ | |
241 | lastdec = READ_TIMER; | |
242 | timestamp = 0; | |
243 | } | |
244 | ||
245 | ulong get_timer_masked (void) | |
246 | { | |
247 | ulong now = READ_TIMER; /* current tick value */ | |
248 | ||
249 | if (lastdec >= now) { /* did I roll (rem decrementer) */ | |
250 | /* normal mode */ | |
251 | timestamp += lastdec - now; /* record amount of time since last check */ | |
252 | } else { | |
253 | /* we have an overflow ... */ | |
254 | timestamp += lastdec + TIMER_LOAD_VAL - now; | |
255 | } | |
256 | lastdec = now; | |
257 | ||
258 | return timestamp; | |
259 | } | |
260 | ||
261 | void udelay_masked (unsigned long usec) | |
262 | { | |
263 | #ifdef CONFIG_INNOVATOROMAP1510 | |
264 | #define LOOPS_PER_MSEC 60 /* tuned on omap1510 */ | |
265 | volatile int i, time_remaining = LOOPS_PER_MSEC*usec; | |
266 | for (i=time_remaining; i>0; i--) { } | |
267 | #else | |
268 | ||
269 | ulong tmo; | |
270 | ||
271 | tmo = usec / 1000; | |
272 | tmo *= CFG_HZ; | |
273 | tmo /= 1000; | |
274 | ||
275 | reset_timer_masked (); | |
276 | ||
277 | while (get_timer_masked () < tmo) | |
278 | /*NOP*/; | |
279 | #endif | |
280 | } | |
281 | ||
282 | /* | |
283 | * This function is derived from PowerPC code (read timebase as long long). | |
284 | * On ARM it just returns the timer value. | |
285 | */ | |
286 | unsigned long long get_ticks(void) | |
287 | { | |
288 | return get_timer(0); | |
289 | } | |
290 | ||
291 | /* | |
292 | * This function is derived from PowerPC code (timebase clock frequency). | |
293 | * On ARM it returns the number of timer ticks per second. | |
294 | */ | |
295 | ulong get_tbclk (void) | |
296 | { /* poor timer, may need to improve especiall for bootp. */ | |
297 | ulong tbclk; | |
298 | ||
299 | tbclk = CFG_HZ; | |
300 | return tbclk; | |
301 | } |