]>
Commit | Line | Data |
---|---|---|
c74b2108 SK |
1 | /* |
2 | * Low-level board setup code for TI DaVinci SoC based boards. | |
3 | * | |
4 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
5 | * | |
6 | * Partially based on TI sources, original copyrights follow: | |
7 | */ | |
8 | ||
9 | /* | |
10 | * Board specific setup info | |
11 | * | |
12 | * (C) Copyright 2003 | |
13 | * Texas Instruments, <www.ti.com> | |
14 | * Kshitij Gupta <Kshitij@ti.com> | |
15 | * | |
16 | * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 | |
17 | * | |
18 | * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004 | |
19 | * See file CREDITS for list of people who contributed to this | |
20 | * project. | |
21 | * | |
22 | * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005 | |
23 | * See file CREDITS for list of people who contributed to this | |
24 | * project. | |
25 | * | |
26 | * Modified for DV-EVM board by Swaminathan S, Nov 2005 | |
27 | * See file CREDITS for list of people who contributed to this | |
28 | * project. | |
29 | * | |
30 | * This program is free software; you can redistribute it and/or | |
31 | * modify it under the terms of the GNU General Public License as | |
32 | * published by the Free Software Foundation; either version 2 of | |
33 | * the License, or (at your option) any later version. | |
34 | * | |
35 | * This program is distributed in the hope that it will be useful, | |
36 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
37 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
38 | * GNU General Public License for more details. | |
39 | * | |
40 | * You should have received a copy of the GNU General Public License | |
41 | * along with this program; if not, write to the Free Software | |
42 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
43 | * MA 02111-1307 USA | |
44 | */ | |
45 | ||
46 | #include <config.h> | |
47 | ||
48 | .globl lowlevel_init | |
49 | lowlevel_init: | |
50 | ||
51 | /*-------------------------------------------------------* | |
52 | * Mask all IRQs by setting all bits in the EINT default * | |
53 | *-------------------------------------------------------*/ | |
54 | mov r1, $0 | |
55 | ldr r0, =EINT_ENABLE0 | |
56 | str r1, [r0] | |
57 | ldr r0, =EINT_ENABLE1 | |
58 | str r1, [r0] | |
59 | ||
60 | /*------------------------------------------------------* | |
61 | * Put the GEM in reset * | |
62 | *------------------------------------------------------*/ | |
63 | ||
64 | /* Put the GEM in reset */ | |
65 | ldr r8, PSC_GEM_FLAG_CLEAR | |
66 | ldr r6, MDCTL_GEM | |
67 | ldr r7, [r6] | |
68 | and r7, r7, r8 | |
69 | str r7, [r6] | |
70 | ||
71 | /* Enable the Power Domain Transition Command */ | |
72 | ldr r6, PTCMD | |
73 | ldr r7, [r6] | |
74 | orr r7, r7, $0x02 | |
75 | str r7, [r6] | |
76 | ||
77 | /* Check for Transition Complete(PTSTAT) */ | |
78 | checkStatClkStopGem: | |
79 | ldr r6, PTSTAT | |
80 | ldr r7, [r6] | |
81 | ands r7, r7, $0x02 | |
82 | bne checkStatClkStopGem | |
83 | ||
84 | /* Check for GEM Reset Completion */ | |
85 | checkGemStatClkStop: | |
86 | ldr r6, MDSTAT_GEM | |
87 | ldr r7, [r6] | |
88 | ands r7, r7, $0x100 | |
89 | bne checkGemStatClkStop | |
90 | ||
91 | /* Do this for enabling a WDT initiated reset this is a workaround | |
92 | for a chip bug. Not required under normal situations */ | |
93 | ldr r6, P1394 | |
94 | mov r10, $0 | |
95 | str r10, [r6] | |
96 | ||
97 | /*------------------------------------------------------* | |
98 | * Enable L1 & L2 Memories in Fast mode * | |
99 | *------------------------------------------------------*/ | |
100 | ldr r6, DFT_ENABLE | |
101 | mov r10, $0x01 | |
102 | str r10, [r6] | |
103 | ||
104 | ldr r6, MMARG_BRF0 | |
105 | ldr r10, MMARG_BRF0_VAL | |
106 | str r10, [r6] | |
107 | ||
108 | ldr r6, DFT_ENABLE | |
109 | mov r10, $0 | |
110 | str r10, [r6] | |
111 | ||
112 | /*------------------------------------------------------* | |
53677ef1 | 113 | * DDR2 PLL Initialization * |
c74b2108 SK |
114 | *------------------------------------------------------*/ |
115 | ||
116 | /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */ | |
117 | mov r10, $0 | |
118 | ldr r6, PLL2_CTL | |
119 | ldr r7, PLL_CLKSRC_MASK | |
120 | ldr r8, [r6] | |
121 | and r8, r8, r7 | |
122 | mov r9, r10, lsl $8 | |
123 | orr r8, r8, r9 | |
124 | str r8, [r6] | |
125 | ||
126 | /* Select the PLLEN source */ | |
127 | ldr r7, PLL_ENSRC_MASK | |
128 | and r8, r8, r7 | |
129 | str r8, [r6] | |
130 | ||
131 | /* Bypass the PLL */ | |
132 | ldr r7, PLL_BYPASS_MASK | |
133 | and r8, r8, r7 | |
134 | str r8, [r6] | |
135 | ||
136 | /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */ | |
137 | mov r10, $0x20 | |
138 | WaitPPL2Loop: | |
139 | subs r10, r10, $1 | |
140 | bne WaitPPL2Loop | |
141 | ||
142 | /* Reset the PLL */ | |
143 | ldr r7, PLL_RESET_MASK | |
144 | and r8, r8, r7 | |
145 | str r8, [r6] | |
146 | ||
147 | /* Power up the PLL */ | |
148 | ldr r7, PLL_PWRUP_MASK | |
149 | and r8, r8, r7 | |
150 | str r8, [r6] | |
151 | ||
152 | /* Enable the PLL from Disable Mode */ | |
153 | ldr r7, PLL_DISABLE_ENABLE_MASK | |
154 | and r8, r8, r7 | |
155 | str r8, [r6] | |
156 | ||
157 | /* Program the PLL Multiplier */ | |
158 | ldr r6, PLL2_PLLM | |
950a3924 | 159 | mov r2, $0x17 /* 162 MHz */ |
c74b2108 SK |
160 | str r2, [r6] |
161 | ||
162 | /* Program the PLL2 Divisor Value */ | |
163 | ldr r6, PLL2_DIV2 | |
950a3924 | 164 | mov r3, $0x01 |
c74b2108 SK |
165 | str r3, [r6] |
166 | ||
167 | /* Program the PLL2 Divisor Value */ | |
168 | ldr r6, PLL2_DIV1 | |
950a3924 | 169 | mov r4, $0x0b /* 54 MHz */ |
c74b2108 SK |
170 | str r4, [r6] |
171 | ||
172 | /* PLL2 DIV2 MMR */ | |
173 | ldr r8, PLL2_DIV_MASK | |
174 | ldr r6, PLL2_DIV2 | |
175 | ldr r9, [r6] | |
176 | and r8, r8, r9 | |
177 | mov r9, $0x01 | |
178 | mov r9, r9, lsl $15 | |
179 | orr r8, r8, r9 | |
180 | str r8, [r6] | |
181 | ||
182 | /* Program the GOSET bit to take new divider values */ | |
183 | ldr r6, PLL2_PLLCMD | |
184 | ldr r7, [r6] | |
185 | orr r7, r7, $0x01 | |
186 | str r7, [r6] | |
187 | ||
188 | /* Wait for Done */ | |
189 | ldr r6, PLL2_PLLSTAT | |
190 | doneLoop_0: | |
191 | ldr r7, [r6] | |
192 | ands r7, r7, $0x01 | |
193 | bne doneLoop_0 | |
194 | ||
195 | /* PLL2 DIV1 MMR */ | |
196 | ldr r8, PLL2_DIV_MASK | |
197 | ldr r6, PLL2_DIV1 | |
198 | ldr r9, [r6] | |
199 | and r8, r8, r9 | |
200 | mov r9, $0x01 | |
201 | mov r9, r9, lsl $15 | |
202 | orr r8, r8, r9 | |
203 | str r8, [r6] | |
204 | ||
205 | /* Program the GOSET bit to take new divider values */ | |
206 | ldr r6, PLL2_PLLCMD | |
207 | ldr r7, [r6] | |
208 | orr r7, r7, $0x01 | |
209 | str r7, [r6] | |
210 | ||
211 | /* Wait for Done */ | |
212 | ldr r6, PLL2_PLLSTAT | |
213 | doneLoop: | |
214 | ldr r7, [r6] | |
215 | ands r7, r7, $0x01 | |
216 | bne doneLoop | |
217 | ||
218 | /* Wait for PLL to Reset Properly */ | |
219 | mov r10, $0x218 | |
220 | ResetPPL2Loop: | |
221 | subs r10, r10, $1 | |
222 | bne ResetPPL2Loop | |
223 | ||
224 | /* Bring PLL out of Reset */ | |
225 | ldr r6, PLL2_CTL | |
226 | ldr r8, [r6] | |
227 | orr r8, r8, $0x08 | |
228 | str r8, [r6] | |
229 | ||
230 | /* Wait for PLL to Lock */ | |
231 | ldr r10, PLL_LOCK_COUNT | |
232 | PLL2Lock: | |
233 | subs r10, r10, $1 | |
234 | bne PLL2Lock | |
235 | ||
236 | /* Enable the PLL */ | |
237 | ldr r6, PLL2_CTL | |
238 | ldr r8, [r6] | |
239 | orr r8, r8, $0x01 | |
240 | str r8, [r6] | |
241 | ||
242 | /*------------------------------------------------------* | |
243 | * Issue Soft Reset to DDR Module * | |
244 | *------------------------------------------------------*/ | |
245 | ||
246 | /* Shut down the DDR2 LPSC Module */ | |
247 | ldr r8, PSC_FLAG_CLEAR | |
248 | ldr r6, MDCTL_DDR2 | |
249 | ldr r7, [r6] | |
250 | and r7, r7, r8 | |
251 | orr r7, r7, $0x03 | |
252 | str r7, [r6] | |
253 | ||
254 | /* Enable the Power Domain Transition Command */ | |
255 | ldr r6, PTCMD | |
256 | ldr r7, [r6] | |
257 | orr r7, r7, $0x01 | |
258 | str r7, [r6] | |
259 | ||
260 | /* Check for Transition Complete(PTSTAT) */ | |
261 | checkStatClkStop: | |
262 | ldr r6, PTSTAT | |
263 | ldr r7, [r6] | |
264 | ands r7, r7, $0x01 | |
265 | bne checkStatClkStop | |
266 | ||
267 | /* Check for DDR2 Controller Enable Completion */ | |
268 | checkDDRStatClkStop: | |
269 | ldr r6, MDSTAT_DDR2 | |
270 | ldr r7, [r6] | |
271 | and r7, r7, $0x1f | |
272 | cmp r7, $0x03 | |
273 | bne checkDDRStatClkStop | |
274 | ||
275 | /*------------------------------------------------------* | |
950a3924 | 276 | * Program DDR2 MMRs for 162MHz Setting * |
c74b2108 SK |
277 | *------------------------------------------------------*/ |
278 | ||
279 | /* Program PHY Control Register */ | |
280 | ldr r6, DDRCTL | |
281 | ldr r7, DDRCTL_VAL | |
282 | str r7, [r6] | |
283 | ||
284 | /* Program SDRAM Bank Config Register */ | |
285 | ldr r6, SDCFG | |
286 | ldr r7, SDCFG_VAL | |
287 | str r7, [r6] | |
288 | ||
289 | /* Program SDRAM TIM-0 Config Register */ | |
290 | ldr r6, SDTIM0 | |
950a3924 | 291 | ldr r7, SDTIM0_VAL_162MHz |
c74b2108 SK |
292 | str r7, [r6] |
293 | ||
294 | /* Program SDRAM TIM-1 Config Register */ | |
295 | ldr r6, SDTIM1 | |
950a3924 | 296 | ldr r7, SDTIM1_VAL_162MHz |
c74b2108 SK |
297 | str r7, [r6] |
298 | ||
299 | /* Program the SDRAM Bank Config Control Register */ | |
300 | ldr r10, MASK_VAL | |
301 | ldr r8, SDCFG | |
302 | ldr r9, SDCFG_VAL | |
303 | and r9, r9, r10 | |
304 | str r9, [r8] | |
305 | ||
306 | /* Program SDRAM SDREF Config Register */ | |
307 | ldr r6, SDREF | |
308 | ldr r7, SDREF_VAL | |
309 | str r7, [r6] | |
310 | ||
311 | /*------------------------------------------------------* | |
312 | * Issue Soft Reset to DDR Module * | |
313 | *------------------------------------------------------*/ | |
314 | ||
315 | /* Issue a Dummy DDR2 read/write */ | |
316 | ldr r8, DDR2_START_ADDR | |
317 | ldr r7, DUMMY_VAL | |
318 | str r7, [r8] | |
319 | ldr r7, [r8] | |
320 | ||
321 | /* Shut down the DDR2 LPSC Module */ | |
322 | ldr r8, PSC_FLAG_CLEAR | |
323 | ldr r6, MDCTL_DDR2 | |
324 | ldr r7, [r6] | |
325 | and r7, r7, r8 | |
326 | orr r7, r7, $0x01 | |
327 | str r7, [r6] | |
328 | ||
329 | /* Enable the Power Domain Transition Command */ | |
330 | ldr r6, PTCMD | |
331 | ldr r7, [r6] | |
332 | orr r7, r7, $0x01 | |
333 | str r7, [r6] | |
334 | ||
335 | /* Check for Transition Complete(PTSTAT) */ | |
336 | checkStatClkStop2: | |
337 | ldr r6, PTSTAT | |
338 | ldr r7, [r6] | |
339 | ands r7, r7, $0x01 | |
340 | bne checkStatClkStop2 | |
341 | ||
342 | /* Check for DDR2 Controller Enable Completion */ | |
343 | checkDDRStatClkStop2: | |
344 | ldr r6, MDSTAT_DDR2 | |
345 | ldr r7, [r6] | |
346 | and r7, r7, $0x1f | |
347 | cmp r7, $0x01 | |
348 | bne checkDDRStatClkStop2 | |
349 | ||
350 | /*------------------------------------------------------* | |
351 | * Turn DDR2 Controller Clocks On * | |
352 | *------------------------------------------------------*/ | |
353 | ||
354 | /* Enable the DDR2 LPSC Module */ | |
355 | ldr r6, MDCTL_DDR2 | |
356 | ldr r7, [r6] | |
357 | orr r7, r7, $0x03 | |
358 | str r7, [r6] | |
359 | ||
360 | /* Enable the Power Domain Transition Command */ | |
361 | ldr r6, PTCMD | |
362 | ldr r7, [r6] | |
363 | orr r7, r7, $0x01 | |
364 | str r7, [r6] | |
365 | ||
366 | /* Check for Transition Complete(PTSTAT) */ | |
367 | checkStatClkEn2: | |
368 | ldr r6, PTSTAT | |
369 | ldr r7, [r6] | |
370 | ands r7, r7, $0x01 | |
371 | bne checkStatClkEn2 | |
372 | ||
373 | /* Check for DDR2 Controller Enable Completion */ | |
374 | checkDDRStatClkEn2: | |
375 | ldr r6, MDSTAT_DDR2 | |
376 | ldr r7, [r6] | |
377 | and r7, r7, $0x1f | |
378 | cmp r7, $0x03 | |
379 | bne checkDDRStatClkEn2 | |
380 | ||
381 | /* DDR Writes and Reads */ | |
382 | ldr r6, CFGTEST | |
383 | mov r3, $0x01 | |
384 | str r3, [r6] | |
385 | ||
386 | /*------------------------------------------------------* | |
387 | * System PLL Initialization * | |
388 | *------------------------------------------------------*/ | |
389 | ||
390 | /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */ | |
391 | mov r2, $0 | |
392 | ldr r6, PLL1_CTL | |
393 | ldr r7, PLL_CLKSRC_MASK | |
394 | ldr r8, [r6] | |
395 | and r8, r8, r7 | |
396 | mov r9, r2, lsl $8 | |
397 | orr r8, r8, r9 | |
398 | str r8, [r6] | |
399 | ||
400 | /* Select the PLLEN source */ | |
401 | ldr r7, PLL_ENSRC_MASK | |
402 | and r8, r8, r7 | |
403 | str r8, [r6] | |
404 | ||
405 | /* Bypass the PLL */ | |
406 | ldr r7, PLL_BYPASS_MASK | |
407 | and r8, r8, r7 | |
408 | str r8, [r6] | |
409 | ||
410 | /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */ | |
411 | mov r10, $0x20 | |
412 | ||
413 | WaitLoop: | |
414 | subs r10, r10, $1 | |
415 | bne WaitLoop | |
416 | ||
417 | /* Reset the PLL */ | |
418 | ldr r7, PLL_RESET_MASK | |
419 | and r8, r8, r7 | |
420 | str r8, [r6] | |
421 | ||
422 | /* Disable the PLL */ | |
423 | orr r8, r8, $0x10 | |
424 | str r8, [r6] | |
425 | ||
426 | /* Power up the PLL */ | |
427 | ldr r7, PLL_PWRUP_MASK | |
428 | and r8, r8, r7 | |
429 | str r8, [r6] | |
430 | ||
431 | /* Enable the PLL from Disable Mode */ | |
432 | ldr r7, PLL_DISABLE_ENABLE_MASK | |
433 | and r8, r8, r7 | |
434 | str r8, [r6] | |
435 | ||
436 | /* Program the PLL Multiplier */ | |
437 | ldr r6, PLL1_PLLM | |
950a3924 | 438 | mov r3, $0x15 /* For 594MHz */ |
c74b2108 SK |
439 | str r3, [r6] |
440 | ||
441 | /* Wait for PLL to Reset Properly */ | |
442 | mov r10, $0xff | |
443 | ||
444 | ResetLoop: | |
445 | subs r10, r10, $1 | |
446 | bne ResetLoop | |
447 | ||
448 | /* Bring PLL out of Reset */ | |
449 | ldr r6, PLL1_CTL | |
450 | orr r8, r8, $0x08 | |
451 | str r8, [r6] | |
452 | ||
453 | /* Wait for PLL to Lock */ | |
454 | ldr r10, PLL_LOCK_COUNT | |
455 | ||
456 | PLL1Lock: | |
457 | subs r10, r10, $1 | |
458 | bne PLL1Lock | |
459 | ||
460 | /* Enable the PLL */ | |
461 | orr r8, r8, $0x01 | |
462 | str r8, [r6] | |
463 | ||
464 | nop | |
465 | nop | |
466 | nop | |
467 | nop | |
468 | ||
469 | /*------------------------------------------------------* | |
950a3924 | 470 | * AEMIF configuration for NOR Flash (double check) * |
c74b2108 SK |
471 | *------------------------------------------------------*/ |
472 | ldr r0, _PINMUX0 | |
473 | ldr r1, _DEV_SETTING | |
474 | str r1, [r0] | |
475 | ||
476 | ldr r0, WAITCFG | |
477 | ldr r1, WAITCFG_VAL | |
478 | ldr r2, [r0] | |
479 | orr r2, r2, r1 | |
480 | str r2, [r0] | |
481 | ||
482 | ldr r0, ACFG3 | |
483 | ldr r1, ACFG3_VAL | |
484 | ldr r2, [r0] | |
485 | and r1, r2, r1 | |
486 | str r1, [r0] | |
487 | ||
488 | ldr r0, ACFG4 | |
489 | ldr r1, ACFG4_VAL | |
490 | ldr r2, [r0] | |
491 | and r1, r2, r1 | |
492 | str r1, [r0] | |
493 | ||
494 | ldr r0, ACFG5 | |
495 | ldr r1, ACFG5_VAL | |
496 | ldr r2, [r0] | |
497 | and r1, r2, r1 | |
498 | str r1, [r0] | |
499 | ||
500 | /*--------------------------------------* | |
501 | * VTP manual Calibration * | |
502 | *--------------------------------------*/ | |
503 | ldr r0, VTPIOCR | |
504 | ldr r1, VTP_MMR0 | |
505 | str r1, [r0] | |
506 | ||
507 | ldr r0, VTPIOCR | |
508 | ldr r1, VTP_MMR1 | |
509 | str r1, [r0] | |
510 | ||
511 | /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */ | |
512 | ldr r10, VTP_LOCK_COUNT | |
513 | VTPLock: | |
514 | subs r10, r10, $1 | |
515 | bne VTPLock | |
516 | ||
517 | ldr r6, DFT_ENABLE | |
518 | mov r10, $0x01 | |
519 | str r10, [r6] | |
520 | ||
521 | ldr r6, DDRVTPR | |
522 | ldr r7, [r6] | |
523 | and r7, r7, $0x1f | |
524 | and r8, r7, $0x3e0 | |
525 | orr r8, r7, r8 | |
526 | ldr r7, VTP_RECAL | |
527 | orr r8, r7, r8 | |
528 | ldr r7, VTP_EN | |
529 | orr r8, r7, r8 | |
530 | str r8, [r0] | |
531 | ||
532 | ||
533 | /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */ | |
534 | ldr r10, VTP_LOCK_COUNT | |
535 | VTP1Lock: | |
536 | subs r10, r10, $1 | |
537 | bne VTP1Lock | |
538 | ||
539 | ldr r1, [r0] | |
540 | ldr r2, VTP_MASK | |
541 | and r2, r1, r2 | |
542 | str r2, [r0] | |
543 | ||
544 | ldr r6, DFT_ENABLE | |
545 | mov r10, $0 | |
546 | str r10, [r6] | |
547 | ||
c2c0ab4a | 548 | /* |
c74b2108 | 549 | * Call board-specific lowlevel init. |
53677ef1 | 550 | * That MUST be present and THAT returns |
c74b2108 SK |
551 | * back to arch calling code with "mov pc, lr." |
552 | */ | |
553 | b dv_board_init | |
554 | ||
555 | .ltorg | |
556 | ||
557 | _PINMUX0: | |
558 | .word 0x01c40000 /* Device Configuration Registers */ | |
559 | _PINMUX1: | |
560 | .word 0x01c40004 /* Device Configuration Registers */ | |
561 | ||
562 | _DEV_SETTING: | |
950a3924 | 563 | .word 0x00000c1f |
c74b2108 SK |
564 | |
565 | WAITCFG: | |
566 | .word 0x01e00004 | |
567 | WAITCFG_VAL: | |
950a3924 | 568 | .word 0 |
c74b2108 SK |
569 | ACFG3: |
570 | .word 0x01e00014 | |
571 | ACFG3_VAL: | |
950a3924 | 572 | .word 0x3ffffffd |
c74b2108 SK |
573 | ACFG4: |
574 | .word 0x01e00018 | |
575 | ACFG4_VAL: | |
950a3924 | 576 | .word 0x3ffffffd |
c74b2108 SK |
577 | ACFG5: |
578 | .word 0x01e0001c | |
579 | ACFG5_VAL: | |
950a3924 | 580 | .word 0x3ffffffd |
c74b2108 SK |
581 | |
582 | MDCTL_DDR2: | |
583 | .word 0x01c41a34 | |
584 | MDSTAT_DDR2: | |
585 | .word 0x01c41834 | |
586 | ||
587 | PTCMD: | |
588 | .word 0x01c41120 | |
589 | PTSTAT: | |
590 | .word 0x01c41128 | |
591 | ||
592 | EINT_ENABLE0: | |
593 | .word 0x01c48018 | |
594 | EINT_ENABLE1: | |
595 | .word 0x01c4801c | |
596 | ||
597 | PSC_FLAG_CLEAR: | |
598 | .word 0xffffffe0 | |
599 | PSC_GEM_FLAG_CLEAR: | |
600 | .word 0xfffffeff | |
601 | ||
950a3924 | 602 | /* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */ |
c74b2108 SK |
603 | DDRCTL: |
604 | .word 0x200000e4 | |
605 | DDRCTL_VAL: | |
950a3924 | 606 | .word 0x50006405 |
c74b2108 SK |
607 | SDREF: |
608 | .word 0x2000000c | |
609 | SDREF_VAL: | |
950a3924 | 610 | .word 0x000005c3 |
c74b2108 SK |
611 | SDCFG: |
612 | .word 0x20000008 | |
613 | SDCFG_VAL: | |
950a3924 WD |
614 | #ifdef DDR_4BANKS |
615 | .word 0x00178622 | |
616 | #elif defined DDR_8BANKS | |
617 | .word 0x00178632 | |
618 | #else | |
619 | #error "Unknown DDR configuration!!!" | |
620 | #endif | |
c74b2108 SK |
621 | SDTIM0: |
622 | .word 0x20000010 | |
950a3924 WD |
623 | SDTIM0_VAL_162MHz: |
624 | .word 0x28923211 | |
c74b2108 SK |
625 | SDTIM1: |
626 | .word 0x20000014 | |
950a3924 WD |
627 | SDTIM1_VAL_162MHz: |
628 | .word 0x0016c722 | |
c74b2108 SK |
629 | VTPIOCR: |
630 | .word 0x200000f0 /* VTP IO Control register */ | |
631 | DDRVTPR: | |
632 | .word 0x01c42030 /* DDR VPTR MMR */ | |
633 | VTP_MMR0: | |
634 | .word 0x201f | |
635 | VTP_MMR1: | |
636 | .word 0xa01f | |
637 | DFT_ENABLE: | |
638 | .word 0x01c4004c | |
639 | VTP_LOCK_COUNT: | |
640 | .word 0x5b0 | |
641 | VTP_MASK: | |
642 | .word 0xffffdfff | |
643 | VTP_RECAL: | |
644 | .word 0x40000 | |
645 | VTP_EN: | |
646 | .word 0x02000 | |
647 | CFGTEST: | |
648 | .word 0x80010000 | |
649 | MASK_VAL: | |
650 | .word 0x00000fff | |
651 | ||
652 | /* GEM Power Up & LPSC Control Register */ | |
653 | MDCTL_GEM: | |
654 | .word 0x01c41a9c | |
655 | MDSTAT_GEM: | |
656 | .word 0x01c4189c | |
657 | ||
658 | /* For WDT reset chip bug */ | |
659 | P1394: | |
660 | .word 0x01c41a20 | |
661 | ||
662 | PLL_CLKSRC_MASK: | |
663 | .word 0xfffffeff /* Mask the Clock Mode bit */ | |
664 | PLL_ENSRC_MASK: | |
665 | .word 0xffffffdf /* Select the PLLEN source */ | |
666 | PLL_BYPASS_MASK: | |
667 | .word 0xfffffffe /* Put the PLL in BYPASS */ | |
668 | PLL_RESET_MASK: | |
669 | .word 0xfffffff7 /* Put the PLL in Reset Mode */ | |
670 | PLL_PWRUP_MASK: | |
671 | .word 0xfffffffd /* PLL Power up Mask Bit */ | |
672 | PLL_DISABLE_ENABLE_MASK: | |
673 | .word 0xffffffef /* Enable the PLL from Disable */ | |
674 | PLL_LOCK_COUNT: | |
675 | .word 0x2000 | |
676 | ||
677 | /* PLL1-SYSTEM PLL MMRs */ | |
678 | PLL1_CTL: | |
679 | .word 0x01c40900 | |
680 | PLL1_PLLM: | |
681 | .word 0x01c40910 | |
682 | ||
683 | /* PLL2-SYSTEM PLL MMRs */ | |
684 | PLL2_CTL: | |
685 | .word 0x01c40d00 | |
686 | PLL2_PLLM: | |
687 | .word 0x01c40d10 | |
688 | PLL2_DIV1: | |
689 | .word 0x01c40d18 | |
690 | PLL2_DIV2: | |
691 | .word 0x01c40d1c | |
692 | PLL2_PLLCMD: | |
693 | .word 0x01c40d38 | |
694 | PLL2_PLLSTAT: | |
695 | .word 0x01c40d3c | |
696 | PLL2_DIV_MASK: | |
697 | .word 0xffff7fff | |
698 | ||
699 | MMARG_BRF0: | |
700 | .word 0x01c42010 /* BRF margin mode 0 (R/W)*/ | |
701 | MMARG_BRF0_VAL: | |
950a3924 | 702 | .word 0x00444400 |
c74b2108 SK |
703 | |
704 | DDR2_START_ADDR: | |
705 | .word 0x80000000 | |
706 | DUMMY_VAL: | |
707 | .word 0xa55aa55a |