]> git.ipfire.org Git - people/ms/u-boot.git/blame - cpu/arm926ejs/interrupts.c
* Patches by Xianghua Xiao, 15 Oct 2003:
[people/ms/u-boot.git] / cpu / arm926ejs / interrupts.c
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6f21347d
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1/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
9 *
10 * (C) Copyright 2002
11 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
12 *
13 * See file CREDITS for list of people who contributed to this
14 * project.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 */
31
32#include <common.h>
33#include <arm925t.h>
34#include <configs/omap1510.h>
35
36#include <asm/proc-armv/ptrace.h>
37
38extern void reset_cpu(ulong addr);
39#define TIMER_LOAD_VAL 0xffffffff
40
41/* macro to read the 32 bit timer */
42#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
43
44#ifdef CONFIG_USE_IRQ
45/* enable IRQ interrupts */
46void enable_interrupts (void)
47{
48 unsigned long temp;
49 __asm__ __volatile__("mrs %0, cpsr\n"
50 "bic %0, %0, #0x80\n"
51 "msr cpsr_c, %0"
52 : "=r" (temp)
53 : "memory");
54}
55
56/*
57 * disable IRQ/FIQ interrupts
58 * returns true if interrupts had been enabled before we disabled them
59 */
60int disable_interrupts (void)
61{
62 unsigned long old,temp;
63 __asm__ __volatile__("mrs %0, cpsr\n"
64 "orr %1, %0, #0xc0\n"
65 "msr cpsr_c, %1"
66 : "=r" (old), "=r" (temp)
67 : "memory");
68 return (old & 0x80) == 0;
69}
70#else
71void enable_interrupts (void)
72{
73 return;
74}
75int disable_interrupts (void)
76{
77 return 0;
78}
79#endif
80
81
6f21347d
WD
82void bad_mode (void)
83{
84 panic ("Resetting CPU ...\n");
85 reset_cpu (0);
86}
87
88void show_regs (struct pt_regs *regs)
89{
90 unsigned long flags;
91 const char *processor_modes[] = {
92 "USER_26", "FIQ_26", "IRQ_26", "SVC_26",
93 "UK4_26", "UK5_26", "UK6_26", "UK7_26",
94 "UK8_26", "UK9_26", "UK10_26", "UK11_26",
95 "UK12_26", "UK13_26", "UK14_26", "UK15_26",
96 "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
97 "UK4_32", "UK5_32", "UK6_32", "ABT_32",
98 "UK8_32", "UK9_32", "UK10_32", "UND_32",
99 "UK12_32", "UK13_32", "UK14_32", "SYS_32",
100 };
101
102 flags = condition_codes (regs);
103
104 printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
105 "sp : %08lx ip : %08lx fp : %08lx\n",
106 instruction_pointer (regs),
107 regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
108 printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
109 regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
110 printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
111 regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
112 printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
113 regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
114 printf ("Flags: %c%c%c%c",
115 flags & CC_N_BIT ? 'N' : 'n',
116 flags & CC_Z_BIT ? 'Z' : 'z',
117 flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
118 printf (" IRQs %s FIQs %s Mode %s%s\n",
119 interrupts_enabled (regs) ? "on" : "off",
120 fast_interrupts_enabled (regs) ? "on" : "off",
121 processor_modes[processor_mode (regs)],
122 thumb_mode (regs) ? " (T)" : "");
123}
124
125void do_undefined_instruction (struct pt_regs *pt_regs)
126{
127 printf ("undefined instruction\n");
128 show_regs (pt_regs);
129 bad_mode ();
130}
131
132void do_software_interrupt (struct pt_regs *pt_regs)
133{
134 printf ("software interrupt\n");
135 show_regs (pt_regs);
136 bad_mode ();
137}
138
139void do_prefetch_abort (struct pt_regs *pt_regs)
140{
141 printf ("prefetch abort\n");
142 show_regs (pt_regs);
143 bad_mode ();
144}
145
146void do_data_abort (struct pt_regs *pt_regs)
147{
148 printf ("data abort\n");
149 show_regs (pt_regs);
150 bad_mode ();
151}
152
153void do_not_used (struct pt_regs *pt_regs)
154{
155 printf ("not used\n");
156 show_regs (pt_regs);
157 bad_mode ();
158}
159
160void do_fiq (struct pt_regs *pt_regs)
161{
162 printf ("fast interrupt request\n");
163 show_regs (pt_regs);
164 bad_mode ();
165}
166
167void do_irq (struct pt_regs *pt_regs)
168{
169 printf ("interrupt request\n");
170 show_regs (pt_regs);
171 bad_mode ();
172}
173
174static ulong timestamp;
175static ulong lastdec;
176
177/* nothing really to do with interrupts, just starts up a counter. */
178int interrupt_init (void)
179{
180 int32_t val;
181
182 *((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
183 val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE |
184 (CFG_PVT << MPUTIM_PTV_BIT);
185 *((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
186 return (0);
187}
188
189/*
190 * timer without interrupts
191 */
192
193void reset_timer (void)
194{
195 reset_timer_masked ();
196}
197
198ulong get_timer (ulong base)
199{
200 return get_timer_masked () - base;
201}
202
203void set_timer (ulong t)
204{
205 timestamp = t;
206}
207
208/* very rough timer... */
209void udelay (unsigned long usec)
210{
211#ifdef CONFIG_INNOVATOROMAP1610
212#define LOOPS_PER_MSEC 100 /* tuned on omap1610 */
213 volatile int i, time_remaining = LOOPS_PER_MSEC * usec;
214
215 for (i = time_remaining; i > 0; i--) {
216 }
217#else
218
219 ulong tmo;
220 tmo = usec / 1000;
221 tmo *= CFG_HZ;
222 tmo /= 1000;
223 tmo += get_timer (0);
224 while (get_timer_masked () < tmo)
225 /*NOP*/;
226#endif
227}
228
229void reset_timer_masked (void)
230{
231 /* reset time */
232 lastdec = READ_TIMER;
233 timestamp = 0;
234}
235
236ulong get_timer_masked (void)
237{
238 ulong now = READ_TIMER; /* current tick value */
239
240 if (lastdec >= now) { /* did I roll (rem decrementer) */
241 /* normal mode */
242 /* record amount of time since last check */
243 timestamp += lastdec - now;
244 } else {
245 /* we have an overflow ... */
246 timestamp += lastdec + TIMER_LOAD_VAL - now;
247 }
248 lastdec = now;
249
250 return timestamp;
251}
252
253void udelay_masked (unsigned long usec)
254{
255#ifdef CONFIG_INNOVATOROMAP1610
256 #define LOOPS_PER_MSEC 100 /* tuned on omap1610 */
257 volatile int i, time_remaining = LOOPS_PER_MSEC*usec;
258 for (i=time_remaining; i>0; i--) { }
259#else
260
261 ulong tmo;
262
263 tmo = usec / 1000;
264 tmo *= CFG_HZ;
265 tmo /= 1000;
266
267 reset_timer_masked ();
268
269 while (get_timer_masked () < tmo)
270 /*NOP*/;
271#endif
272}
273
274/*
275 * This function is derived from PowerPC code (read timebase as long long).
276 * On ARM it just returns the timer value.
277 */
278unsigned long long get_ticks(void)
279{
280 return get_timer(0);
281}
282
283/*
284 * This function is derived from PowerPC code (timebase clock frequency).
285 * On ARM it returns the number of timer ticks per second.
286 */
287ulong get_tbclk (void)
288{
289 ulong tbclk;
290 tbclk = CFG_HZ;
291 return tbclk;
292}