[people/ms/u-boot.git] / cpu / arm_cortexa8 / cpu.c

/*
 * (C) Copyright 2008 Texas Insturments
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * (C) Copyright 2002
 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * CPU specific code
 */

#include <common.h>
#include <command.h>
#include <asm/arch/sys_proto.h>
#include <asm/system.h>

#ifndef CONFIG_L2_OFF
void l2cache_disable(void);
#endif

static void cache_flush(void);

int cpu_init(void)
{
	return 0;
}

int cleanup_before_linux(void)
{
	unsigned int i;

	/*
	 * this function is called just before we call linux
	 * it prepares the processor for linux
	 *
	 * we turn off caches etc ...
	 */
	disable_interrupts();

	/* turn off I/D-cache */
	icache_disable();
	dcache_disable();

	/* invalidate I-cache */
	cache_flush();

#ifndef CONFIG_L2_OFF
	/* turn off L2 cache */
	l2cache_disable();
	/* invalidate L2 cache also */
	v7_flush_dcache_all(get_device_type());
#endif
	i = 0;
	/* mem barrier to sync up things */
	asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));

#ifndef CONFIG_L2_OFF
	l2cache_enable();
#endif

	return 0;
}

void l2cache_enable()
{
	unsigned long i;
	volatile unsigned int j;

	/* ES2 onwards we can disable/enable L2 ourselves */
	if (get_cpu_rev() >= CPU_3XX_ES20) {
		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
		__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
	} else {
		/* Save r0, r12 and restore them after usage */
		__asm__ __volatile__("mov %0, r12":"=r"(j));
		__asm__ __volatile__("mov %0, r0":"=r"(i));

		/*
		 * GP Device ROM code API usage here
		 * r12 = AUXCR Write function and r0 value
		 */
		__asm__ __volatile__("mov r12, #0x3");
		__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
		__asm__ __volatile__("orr r0, r0, #0x2");
		/* SMI instruction to call ROM Code API */
		__asm__ __volatile__(".word 0xE1600070");
		__asm__ __volatile__("mov r0, %0":"=r"(i));
		__asm__ __volatile__("mov r12, %0":"=r"(j));
	}

}

void l2cache_disable()
{
	unsigned long i;
	volatile unsigned int j;

	/* ES2 onwards we can disable/enable L2 ourselves */
	if (get_cpu_rev() >= CPU_3XX_ES20) {
		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
		__asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
	} else {
		/* Save r0, r12 and restore them after usage */
		__asm__ __volatile__("mov %0, r12":"=r"(j));
		__asm__ __volatile__("mov %0, r0":"=r"(i));

		/*
		 * GP Device ROM code API usage here
		 * r12 = AUXCR Write function and r0 value
		 */
		__asm__ __volatile__("mov r12, #0x3");
		__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
		__asm__ __volatile__("bic r0, r0, #0x2");
		/* SMI instruction to call ROM Code API */
		__asm__ __volatile__(".word 0xE1600070");
		__asm__ __volatile__("mov r0, %0":"=r"(i));
		__asm__ __volatile__("mov r12, %0":"=r"(j));
	}
}

static void cache_flush(void)
{
	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
}
Commit	Line	Data
0b02b184 DB	1	/*
	2	* (C) Copyright 2008 Texas Insturments
	3	*
	4	* (C) Copyright 2002
	5	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	6	* Marius Groeger <mgroeger@sysgo.de>
	7	*
	8	* (C) Copyright 2002
792a09eb	9	* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
0b02b184 DB	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
	30	/*
	31	* CPU specific code
	32	*/
	33
	34	#include <common.h>
	35	#include <command.h>
	36	#include <asm/arch/sys_proto.h>
677e62f4	37	#include <asm/system.h>
0b02b184	38
0b02b184 DB	39	#ifndef CONFIG_L2_OFF
	40	void l2cache_disable(void);
	41	#endif
	42
	43	static void cache_flush(void);
	44
0b02b184 DB	45	int cpu_init(void)
0b02b184 DB	46	{
0b02b184 DB	47	return 0;
	48	}
	49
	50	int cleanup_before_linux(void)
	51	{
	52	unsigned int i;
	53
	54	/*
	55	* this function is called just before we call linux
	56	* it prepares the processor for linux
	57	*
	58	* we turn off caches etc ...
	59	*/
	60	disable_interrupts();
	61
	62	/* turn off I/D-cache */
	63	icache_disable();
	64	dcache_disable();
	65
	66	/* invalidate I-cache */
	67	cache_flush();
	68
	69	#ifndef CONFIG_L2_OFF
	70	/* turn off L2 cache */
	71	l2cache_disable();
	72	/* invalidate L2 cache also */
	73	v7_flush_dcache_all(get_device_type());
	74	#endif
	75	i = 0;
	76	/* mem barrier to sync up things */
	77	asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
	78
	79	#ifndef CONFIG_L2_OFF
	80	l2cache_enable();
	81	#endif
	82
	83	return 0;
	84	}
	85
0b02b184 DB	86	void l2cache_enable()
	87	{
	88	unsigned long i;
	89	volatile unsigned int j;
	90
	91	/* ES2 onwards we can disable/enable L2 ourselves */
cba0b778	92	if (get_cpu_rev() >= CPU_3XX_ES20) {
0b02b184 DB	93	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	94	__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
	95	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
	96	} else {
	97	/* Save r0, r12 and restore them after usage */
	98	__asm__ __volatile__("mov %0, r12":"=r"(j));
	99	__asm__ __volatile__("mov %0, r0":"=r"(i));
	100
	101	/*
	102	* GP Device ROM code API usage here
	103	* r12 = AUXCR Write function and r0 value
	104	*/
	105	__asm__ __volatile__("mov r12, #0x3");
	106	__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
	107	__asm__ __volatile__("orr r0, r0, #0x2");
	108	/* SMI instruction to call ROM Code API */
	109	__asm__ __volatile__(".word 0xE1600070");
	110	__asm__ __volatile__("mov r0, %0":"=r"(i));
	111	__asm__ __volatile__("mov r12, %0":"=r"(j));
	112	}
	113
	114	}
	115
	116	void l2cache_disable()
	117	{
	118	unsigned long i;
	119	volatile unsigned int j;
	120
	121	/* ES2 onwards we can disable/enable L2 ourselves */
cba0b778	122	if (get_cpu_rev() >= CPU_3XX_ES20) {
0b02b184 DB	123	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	124	__asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
	125	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
	126	} else {
	127	/* Save r0, r12 and restore them after usage */
	128	__asm__ __volatile__("mov %0, r12":"=r"(j));
	129	__asm__ __volatile__("mov %0, r0":"=r"(i));
	130
	131	/*
	132	* GP Device ROM code API usage here
	133	* r12 = AUXCR Write function and r0 value
	134	*/
	135	__asm__ __volatile__("mov r12, #0x3");
	136	__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
	137	__asm__ __volatile__("bic r0, r0, #0x2");
	138	/* SMI instruction to call ROM Code API */
	139	__asm__ __volatile__(".word 0xE1600070");
	140	__asm__ __volatile__("mov r0, %0":"=r"(i));
	141	__asm__ __volatile__("mov r12, %0":"=r"(j));
	142	}
	143	}
	144
0b02b184 DB	145	static void cache_flush(void)
	146	{
	147	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
	148	}