[people/ms/u-boot.git] / cpu / at32ap / hsdramc.c

/*
 * Copyright (C) 2005-2006 Atmel Corporation
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <common.h>

#ifdef CONFIG_SYS_HSDRAMC
#include <asm/io.h>
#include <asm/sdram.h>

#include <asm/arch/clk.h>
#include <asm/arch/memory-map.h>

#include "hsdramc1.h"

unsigned long sdram_init(void *sdram_base, const struct sdram_config *config)
{
	unsigned long sdram_size;
	uint32_t cfgreg;
	unsigned int i;

	cfgreg = (HSDRAMC1_BF(NC, config->col_bits - 8)
		       | HSDRAMC1_BF(NR, config->row_bits - 11)
		       | HSDRAMC1_BF(NB, config->bank_bits - 1)
		       | HSDRAMC1_BF(CAS, config->cas)
		       | HSDRAMC1_BF(TWR, config->twr)
		       | HSDRAMC1_BF(TRC, config->trc)
		       | HSDRAMC1_BF(TRP, config->trp)
		       | HSDRAMC1_BF(TRCD, config->trcd)
		       | HSDRAMC1_BF(TRAS, config->tras)
		       | HSDRAMC1_BF(TXSR, config->txsr));

	if (config->data_bits == SDRAM_DATA_16BIT)
		cfgreg |= HSDRAMC1_BIT(DBW);

	hsdramc1_writel(CR, cfgreg);

	/* Send a NOP to turn on the clock (necessary on some chips) */
	hsdramc1_writel(MR, HSDRAMC1_MODE_NOP);
	hsdramc1_readl(MR);
	writel(0, sdram_base);

	/*
	 * Initialization sequence for SDRAM, from the data sheet:
	 *
	 * 1. A minimum pause of 200 us is provided to precede any
	 *    signal toggle.
	 */
	udelay(200);

	/*
	 * 2. A Precharge All command is issued to the SDRAM
	 */
	hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
	hsdramc1_readl(MR);
	writel(0, sdram_base);

	/*
	 * 3. Eight auto-refresh (CBR) cycles are provided
	 */
	hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH);
	hsdramc1_readl(MR);
	for (i = 0; i < 8; i++)
		writel(0, sdram_base);

	/*
	 * 4. A mode register set (MRS) cycle is issued to program
	 *    SDRAM parameters, in particular CAS latency and burst
	 *    length.
	 *
	 * The address will be chosen by the SDRAMC automatically; we
	 * just have to make sure BA[1:0] are set to 0.
	 */
	hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE);
	hsdramc1_readl(MR);
	writel(0, sdram_base);

	/*
	 * 5. The application must go into Normal Mode, setting Mode
	 *    to 0 in the Mode Register and performing a write access
	 *    at any location in the SDRAM.
	 */
	hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL);
	hsdramc1_readl(MR);
	writel(0, sdram_base);

	/*
	 * 6. Write refresh rate into SDRAMC refresh timer count
	 *    register (refresh rate = timing between refresh cycles).
	 */
	hsdramc1_writel(TR, config->refresh_period);

	if (config->data_bits == SDRAM_DATA_16BIT)
		sdram_size = 1 << (config->row_bits + config->col_bits
				   + config->bank_bits + 1);
	else
		sdram_size = 1 << (config->row_bits + config->col_bits
				   + config->bank_bits + 2);

	return sdram_size;
}

#endif /* CONFIG_SYS_HSDRAMC */
Commit	Line	Data
72a087e0 WD	1	/*
	2	* Copyright (C) 2005-2006 Atmel Corporation
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22	#include <common.h>
	23
6d0f6bcf	24	#ifdef CONFIG_SYS_HSDRAMC
72a087e0 WD	25	#include <asm/io.h>
	26	#include <asm/sdram.h>
	27
df548d3c HS	28	#include <asm/arch/clk.h>
df548d3c HS	29	#include <asm/arch/memory-map.h>
72a087e0 WD	30
	31	#include "hsdramc1.h"
	32
a23e277c	33	unsigned long sdram_init(void sdram_base, const struct sdram_config config)
72a087e0	34	{
72a087e0	35	unsigned long sdram_size;
a23e277c	36	uint32_t cfgreg;
72a087e0 WD	37	unsigned int i;
72a087e0 WD	38
a23e277c HS	39	cfgreg = (HSDRAMC1_BF(NC, config->col_bits - 8)
	40	\| HSDRAMC1_BF(NR, config->row_bits - 11)
	41	\| HSDRAMC1_BF(NB, config->bank_bits - 1)
	42	\| HSDRAMC1_BF(CAS, config->cas)
	43	\| HSDRAMC1_BF(TWR, config->twr)
	44	\| HSDRAMC1_BF(TRC, config->trc)
	45	\| HSDRAMC1_BF(TRP, config->trp)
	46	\| HSDRAMC1_BF(TRCD, config->trcd)
	47	\| HSDRAMC1_BF(TRAS, config->tras)
	48	\| HSDRAMC1_BF(TXSR, config->txsr));
	49
	50	if (config->data_bits == SDRAM_DATA_16BIT)
	51	cfgreg \|= HSDRAMC1_BIT(DBW);
	52
	53	hsdramc1_writel(CR, cfgreg);
	54
	55	/* Send a NOP to turn on the clock (necessary on some chips) */
	56	hsdramc1_writel(MR, HSDRAMC1_MODE_NOP);
	57	hsdramc1_readl(MR);
	58	writel(0, sdram_base);
72a087e0 WD	59
	60	/*
	61	* Initialization sequence for SDRAM, from the data sheet:
	62	*
	63	* 1. A minimum pause of 200 us is provided to precede any
	64	* signal toggle.
	65	*/
	66	udelay(200);
	67
	68	/*
	69	* 2. A Precharge All command is issued to the SDRAM
	70	*/
df548d3c HS	71	hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
df548d3c HS	72	hsdramc1_readl(MR);
a23e277c	73	writel(0, sdram_base);
72a087e0 WD	74
	75	/*
	76	* 3. Eight auto-refresh (CBR) cycles are provided
	77	*/
df548d3c HS	78	hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH);
df548d3c HS	79	hsdramc1_readl(MR);
72a087e0	80	for (i = 0; i < 8; i++)
a23e277c	81	writel(0, sdram_base);
72a087e0 WD	82
	83	/*
	84	* 4. A mode register set (MRS) cycle is issued to program
	85	* SDRAM parameters, in particular CAS latency and burst
	86	* length.
	87	*
a23e277c HS	88	* The address will be chosen by the SDRAMC automatically; we
a23e277c HS	89	* just have to make sure BA[1:0] are set to 0.
72a087e0	90	*/
df548d3c HS	91	hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE);
df548d3c HS	92	hsdramc1_readl(MR);
a23e277c	93	writel(0, sdram_base);
72a087e0 WD	94
72a087e0 WD	95	/*
a23e277c HS	96	* 5. The application must go into Normal Mode, setting Mode
	97	* to 0 in the Mode Register and performing a write access
	98	* at any location in the SDRAM.
72a087e0	99	*/
df548d3c HS	100	hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL);
df548d3c HS	101	hsdramc1_readl(MR);
a23e277c	102	writel(0, sdram_base);
72a087e0 WD	103
	104	/*
	105	* 6. Write refresh rate into SDRAMC refresh timer count
	106	* register (refresh rate = timing between refresh cycles).
72a087e0	107	*/
a23e277c HS	108	hsdramc1_writel(TR, config->refresh_period);
	109
	110	if (config->data_bits == SDRAM_DATA_16BIT)
	111	sdram_size = 1 << (config->row_bits + config->col_bits
	112	+ config->bank_bits + 1);
	113	else
	114	sdram_size = 1 << (config->row_bits + config->col_bits
	115	+ config->bank_bits + 2);
72a087e0 WD	116
	117	return sdram_size;
	118	}
	119
6d0f6bcf	120	#endif /* CONFIG_SYS_HSDRAMC */