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bf9e3b38 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Josef Baumgartner <josef.baumgartner@telex.de> | |
4 | * | |
9acb626f HS |
5 | * MCF5282 additionals |
6 | * (C) Copyright 2005 | |
7 | * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de> | |
8 | * | |
a1436a84 TL |
9 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
10 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
11 | * Hayden Fraser (Hayden.Fraser@freescale.com) | |
12 | * | |
f71d9d91 MF |
13 | * MCF5275 additions |
14 | * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) | |
15 | * | |
bf9e3b38 WD |
16 | * See file CREDITS for list of people who contributed to this |
17 | * project. | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License as | |
21 | * published by the Free Software Foundation; either version 2 of | |
22 | * the License, or (at your option) any later version. | |
23 | * | |
24 | * This program is distributed in the hope that it will be useful, | |
25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
977b50f8 | 26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
bf9e3b38 WD |
27 | * GNU General Public License for more details. |
28 | * | |
29 | * You should have received a copy of the GNU General Public License | |
30 | * along with this program; if not, write to the Free Software | |
31 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
32 | * MA 02111-1307 USA | |
33 | */ | |
34 | ||
35 | #include <common.h> | |
36 | #include <watchdog.h> | |
83ec20bc | 37 | #include <asm/immap.h> |
8c725b93 | 38 | |
a1436a84 TL |
39 | #if defined(CONFIG_M5253) |
40 | /* | |
41 | * Breath some life into the CPU... | |
42 | * | |
43 | * Set up the memory map, | |
44 | * initialize a bunch of registers, | |
45 | * initialize the UPM's | |
46 | */ | |
47 | void cpu_init_f(void) | |
48 | { | |
49 | mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */ | |
50 | mbar_writeByte(MCFSIM_SYPCR, 0x00); | |
51 | mbar_writeByte(MCFSIM_SWIVR, 0x0f); | |
52 | mbar_writeByte(MCFSIM_SWSR, 0x00); | |
53 | mbar_writeByte(MCFSIM_SWDICR, 0x00); | |
54 | mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); | |
55 | mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); | |
56 | mbar_writeByte(MCFSIM_I2CICR, 0x00); | |
57 | mbar_writeByte(MCFSIM_UART1ICR, 0x00); | |
58 | mbar_writeByte(MCFSIM_UART2ICR, 0x00); | |
59 | mbar_writeByte(MCFSIM_ICR6, 0x00); | |
60 | mbar_writeByte(MCFSIM_ICR7, 0x00); | |
61 | mbar_writeByte(MCFSIM_ICR8, 0x00); | |
62 | mbar_writeByte(MCFSIM_ICR9, 0x00); | |
63 | mbar_writeByte(MCFSIM_QSPIICR, 0x00); | |
64 | ||
65 | mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); | |
66 | mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ | |
67 | mbar2_writeByte(MCFSIM_SPURVEC, 0x00); | |
68 | ||
8280f6a1 | 69 | /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */ |
a1436a84 TL |
70 | |
71 | /* | |
72 | * Setup chip selects... | |
73 | */ | |
74 | ||
6d0f6bcf JCPV |
75 | mbar_writeShort(MCFSIM_CSAR1, CONFIG_SYS_CSAR1); |
76 | mbar_writeShort(MCFSIM_CSCR1, CONFIG_SYS_CSCR1); | |
77 | mbar_writeLong(MCFSIM_CSMR1, CONFIG_SYS_CSMR1); | |
a1436a84 | 78 | |
6d0f6bcf JCPV |
79 | mbar_writeShort(MCFSIM_CSAR0, CONFIG_SYS_CSAR0); |
80 | mbar_writeShort(MCFSIM_CSCR0, CONFIG_SYS_CSCR0); | |
81 | mbar_writeLong(MCFSIM_CSMR0, CONFIG_SYS_CSMR0); | |
a1436a84 | 82 | |
eec567a6 | 83 | #ifdef CONFIG_FSL_I2C |
6d0f6bcf JCPV |
84 | CONFIG_SYS_I2C_PINMUX_REG = CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR; |
85 | CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; | |
86 | #ifdef CONFIG_SYS_I2C2_OFFSET | |
87 | CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR; | |
88 | CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET; | |
eec567a6 TL |
89 | #endif |
90 | #endif | |
91 | ||
a1436a84 TL |
92 | /* enable instruction cache now */ |
93 | icache_enable(); | |
94 | } | |
95 | ||
96 | /*initialize higher level parts of CPU like timers */ | |
97 | int cpu_init_r(void) | |
98 | { | |
99 | return (0); | |
100 | } | |
101 | ||
102 | void uart_port_conf(void) | |
103 | { | |
104 | /* Setup Ports: */ | |
6d0f6bcf | 105 | switch (CONFIG_SYS_UART_PORT) { |
a1436a84 TL |
106 | case 0: |
107 | break; | |
108 | case 1: | |
109 | break; | |
110 | case 2: | |
111 | break; | |
112 | } | |
113 | } | |
114 | #endif /* #if defined(CONFIG_M5253) */ | |
115 | ||
eacbd317 | 116 | #if defined(CONFIG_M5271) |
83ec20bc | 117 | void cpu_init_f(void) |
eacbd317 ZL |
118 | { |
119 | #ifndef CONFIG_WATCHDOG | |
120 | /* Disable the watchdog if we aren't using it */ | |
121 | mbar_writeShort(MCF_WTM_WCR, 0); | |
122 | #endif | |
123 | ||
124 | /* Set clockspeed to 100MHz */ | |
125 | mbar_writeShort(MCF_FMPLL_SYNCR, | |
126 | MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0)); | |
83ec20bc | 127 | while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ; |
eacbd317 ZL |
128 | } |
129 | ||
130 | /* | |
131 | * initialize higher level parts of CPU like timers | |
132 | */ | |
83ec20bc | 133 | int cpu_init_r(void) |
eacbd317 ZL |
134 | { |
135 | return (0); | |
136 | } | |
83ec20bc TL |
137 | |
138 | void uart_port_conf(void) | |
139 | { | |
140 | /* Setup Ports: */ | |
6d0f6bcf | 141 | switch (CONFIG_SYS_UART_PORT) { |
83ec20bc TL |
142 | case 0: |
143 | mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD | | |
144 | MCF_GPIO_PAR_UART_U0RXD); | |
145 | break; | |
146 | case 1: | |
147 | mbar_writeShort(MCF_GPIO_PAR_UART, | |
148 | MCF_GPIO_PAR_UART_U1RXD_UART1 | | |
149 | MCF_GPIO_PAR_UART_U1TXD_UART1); | |
150 | break; | |
151 | case 2: | |
152 | mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000); | |
153 | break; | |
154 | } | |
155 | } | |
eacbd317 ZL |
156 | #endif |
157 | ||
8c725b93 | 158 | #if defined(CONFIG_M5272) |
bf9e3b38 WD |
159 | /* |
160 | * Breath some life into the CPU... | |
161 | * | |
162 | * Set up the memory map, | |
163 | * initialize a bunch of registers, | |
164 | * initialize the UPM's | |
165 | */ | |
83ec20bc | 166 | void cpu_init_f(void) |
bf9e3b38 WD |
167 | { |
168 | /* if we come from RAM we assume the CPU is | |
169 | * already initialized. | |
170 | */ | |
171 | #ifndef CONFIG_MONITOR_IS_IN_RAM | |
6d0f6bcf | 172 | volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR); |
83ec20bc TL |
173 | volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO); |
174 | volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS); | |
bf9e3b38 | 175 | |
6d0f6bcf JCPV |
176 | sysctrl->sc_scr = CONFIG_SYS_SCR; |
177 | sysctrl->sc_spr = CONFIG_SYS_SPR; | |
bf9e3b38 | 178 | |
977b50f8 | 179 | /* Setup Ports: */ |
6d0f6bcf JCPV |
180 | gpio->gpio_pacnt = CONFIG_SYS_PACNT; |
181 | gpio->gpio_paddr = CONFIG_SYS_PADDR; | |
182 | gpio->gpio_padat = CONFIG_SYS_PADAT; | |
183 | gpio->gpio_pbcnt = CONFIG_SYS_PBCNT; | |
184 | gpio->gpio_pbddr = CONFIG_SYS_PBDDR; | |
185 | gpio->gpio_pbdat = CONFIG_SYS_PBDAT; | |
186 | gpio->gpio_pdcnt = CONFIG_SYS_PDCNT; | |
bf9e3b38 WD |
187 | |
188 | /* Memory Controller: */ | |
6d0f6bcf JCPV |
189 | csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM; |
190 | csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM; | |
bf9e3b38 | 191 | |
6d0f6bcf JCPV |
192 | #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) |
193 | csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM; | |
194 | csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM; | |
bf9e3b38 WD |
195 | #endif |
196 | ||
6d0f6bcf JCPV |
197 | #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) |
198 | csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM; | |
199 | csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM; | |
bf9e3b38 WD |
200 | #endif |
201 | ||
6d0f6bcf JCPV |
202 | #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) |
203 | csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM; | |
204 | csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM; | |
bf9e3b38 WD |
205 | #endif |
206 | ||
6d0f6bcf JCPV |
207 | #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM) |
208 | csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM; | |
209 | csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM; | |
bf9e3b38 WD |
210 | #endif |
211 | ||
6d0f6bcf JCPV |
212 | #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM) |
213 | csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM; | |
214 | csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM; | |
bf9e3b38 WD |
215 | #endif |
216 | ||
6d0f6bcf JCPV |
217 | #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM) |
218 | csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM; | |
219 | csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM; | |
bf9e3b38 WD |
220 | #endif |
221 | ||
6d0f6bcf JCPV |
222 | #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM) |
223 | csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM; | |
224 | csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM; | |
bf9e3b38 WD |
225 | #endif |
226 | ||
83ec20bc | 227 | #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ |
bf9e3b38 | 228 | |
977b50f8 WD |
229 | /* enable instruction cache now */ |
230 | icache_enable(); | |
bf9e3b38 WD |
231 | |
232 | } | |
233 | ||
234 | /* | |
235 | * initialize higher level parts of CPU like timers | |
236 | */ | |
83ec20bc | 237 | int cpu_init_r(void) |
bf9e3b38 WD |
238 | { |
239 | return (0); | |
240 | } | |
bf9e3b38 | 241 | |
83ec20bc TL |
242 | void uart_port_conf(void) |
243 | { | |
244 | volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; | |
245 | ||
246 | /* Setup Ports: */ | |
6d0f6bcf | 247 | switch (CONFIG_SYS_UART_PORT) { |
83ec20bc TL |
248 | case 0: |
249 | gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK); | |
250 | gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD); | |
251 | break; | |
252 | case 1: | |
253 | gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK); | |
254 | gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD); | |
255 | break; | |
256 | } | |
257 | } | |
258 | #endif /* #if defined(CONFIG_M5272) */ | |
bf9e3b38 | 259 | |
f71d9d91 MF |
260 | #if defined(CONFIG_M5275) |
261 | ||
262 | /* | |
263 | * Breathe some life into the CPU... | |
264 | * | |
265 | * Set up the memory map, | |
266 | * initialize a bunch of registers, | |
267 | * initialize the UPM's | |
268 | */ | |
269 | void cpu_init_f(void) | |
270 | { | |
271 | /* if we come from RAM we assume the CPU is | |
272 | * already initialized. | |
273 | */ | |
274 | ||
275 | #ifndef CONFIG_MONITOR_IS_IN_RAM | |
276 | volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG); | |
277 | volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO); | |
278 | volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS); | |
279 | ||
280 | /* Kill watchdog so we can initialize the PLL */ | |
281 | wdog_reg->wcr = 0; | |
282 | ||
283 | /* Memory Controller: */ | |
284 | /* Flash */ | |
6d0f6bcf JCPV |
285 | csctrl_reg->ar0 = CONFIG_SYS_AR0_PRELIM; |
286 | csctrl_reg->cr0 = CONFIG_SYS_CR0_PRELIM; | |
287 | csctrl_reg->mr0 = CONFIG_SYS_MR0_PRELIM; | |
f71d9d91 | 288 | |
6d0f6bcf JCPV |
289 | #if (defined(CONFIG_SYS_AR1_PRELIM) && defined(CONFIG_SYS_CR1_PRELIM) && defined(CONFIG_SYS_MR1_PRELIM)) |
290 | csctrl_reg->ar1 = CONFIG_SYS_AR1_PRELIM; | |
291 | csctrl_reg->cr1 = CONFIG_SYS_CR1_PRELIM; | |
292 | csctrl_reg->mr1 = CONFIG_SYS_MR1_PRELIM; | |
f71d9d91 MF |
293 | #endif |
294 | ||
6d0f6bcf JCPV |
295 | #if (defined(CONFIG_SYS_AR2_PRELIM) && defined(CONFIG_SYS_CR2_PRELIM) && defined(CONFIG_SYS_MR2_PRELIM)) |
296 | csctrl_reg->ar2 = CONFIG_SYS_AR2_PRELIM; | |
297 | csctrl_reg->cr2 = CONFIG_SYS_CR2_PRELIM; | |
298 | csctrl_reg->mr2 = CONFIG_SYS_MR2_PRELIM; | |
f71d9d91 MF |
299 | #endif |
300 | ||
6d0f6bcf JCPV |
301 | #if (defined(CONFIG_SYS_AR3_PRELIM) && defined(CONFIG_SYS_CR3_PRELIM) && defined(CONFIG_SYS_MR3_PRELIM)) |
302 | csctrl_reg->ar3 = CONFIG_SYS_AR3_PRELIM; | |
303 | csctrl_reg->cr3 = CONFIG_SYS_CR3_PRELIM; | |
304 | csctrl_reg->mr3 = CONFIG_SYS_MR3_PRELIM; | |
f71d9d91 MF |
305 | #endif |
306 | ||
6d0f6bcf JCPV |
307 | #if (defined(CONFIG_SYS_AR4_PRELIM) && defined(CONFIG_SYS_CR4_PRELIM) && defined(CONFIG_SYS_MR4_PRELIM)) |
308 | csctrl_reg->ar4 = CONFIG_SYS_AR4_PRELIM; | |
309 | csctrl_reg->cr4 = CONFIG_SYS_CR4_PRELIM; | |
310 | csctrl_reg->mr4 = CONFIG_SYS_MR4_PRELIM; | |
f71d9d91 MF |
311 | #endif |
312 | ||
6d0f6bcf JCPV |
313 | #if (defined(CONFIG_SYS_AR5_PRELIM) && defined(CONFIG_SYS_CR5_PRELIM) && defined(CONFIG_SYS_MR5_PRELIM)) |
314 | csctrl_reg->ar5 = CONFIG_SYS_AR5_PRELIM; | |
315 | csctrl_reg->cr5 = CONFIG_SYS_CR5_PRELIM; | |
316 | csctrl_reg->mr5 = CONFIG_SYS_MR5_PRELIM; | |
f71d9d91 MF |
317 | #endif |
318 | ||
6d0f6bcf JCPV |
319 | #if (defined(CONFIG_SYS_AR6_PRELIM) && defined(CONFIG_SYS_CR6_PRELIM) && defined(CONFIG_SYS_MR6_PRELIM)) |
320 | csctrl_reg->ar6 = CONFIG_SYS_AR6_PRELIM; | |
321 | csctrl_reg->cr6 = CONFIG_SYS_CR6_PRELIM; | |
322 | csctrl_reg->mr6 = CONFIG_SYS_MR6_PRELIM; | |
f71d9d91 MF |
323 | #endif |
324 | ||
6d0f6bcf JCPV |
325 | #if (defined(CONFIG_SYS_AR7_PRELIM) && defined(CONFIG_SYS_CR7_PRELIM) && defined(CONFIG_SYS_MR7_PRELIM)) |
326 | csctrl_reg->ar7 = CONFIG_SYS_AR7_PRELIM; | |
327 | csctrl_reg->cr7 = CONFIG_SYS_CR7_PRELIM; | |
328 | csctrl_reg->mr7 = CONFIG_SYS_MR7_PRELIM; | |
f71d9d91 MF |
329 | #endif |
330 | ||
331 | #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ | |
332 | ||
333 | #ifdef CONFIG_FSL_I2C | |
6d0f6bcf JCPV |
334 | CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; |
335 | CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; | |
f71d9d91 MF |
336 | #endif |
337 | ||
338 | /* enable instruction cache now */ | |
339 | icache_enable(); | |
340 | } | |
341 | ||
342 | /* | |
343 | * initialize higher level parts of CPU like timers | |
344 | */ | |
345 | int cpu_init_r(void) | |
346 | { | |
347 | return (0); | |
348 | } | |
349 | ||
350 | void uart_port_conf(void) | |
351 | { | |
352 | volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO; | |
353 | ||
354 | /* Setup Ports: */ | |
6d0f6bcf | 355 | switch (CONFIG_SYS_UART_PORT) { |
f71d9d91 MF |
356 | case 0: |
357 | gpio->par_uart |= UART0_ENABLE_MASK; | |
358 | break; | |
359 | case 1: | |
360 | gpio->par_uart |= UART1_ENABLE_MASK; | |
361 | break; | |
362 | case 2: | |
363 | gpio->par_uart |= UART2_ENABLE_MASK; | |
364 | break; | |
365 | } | |
366 | } | |
367 | #endif /* #if defined(CONFIG_M5275) */ | |
368 | ||
83ec20bc | 369 | #if defined(CONFIG_M5282) |
bf9e3b38 WD |
370 | /* |
371 | * Breath some life into the CPU... | |
372 | * | |
373 | * Set up the memory map, | |
374 | * initialize a bunch of registers, | |
375 | * initialize the UPM's | |
376 | */ | |
83ec20bc | 377 | void cpu_init_f(void) |
bf9e3b38 | 378 | { |
9acb626f HS |
379 | #ifndef CONFIG_WATCHDOG |
380 | /* disable watchdog if we aren't using it */ | |
381 | MCFWTM_WCR = 0; | |
382 | #endif | |
383 | ||
384 | #ifndef CONFIG_MONITOR_IS_IN_RAM | |
385 | /* Set speed /PLL */ | |
83ec20bc | 386 | MCFCLOCK_SYNCR = |
6d0f6bcf | 387 | MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) | MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD); |
83ec20bc TL |
388 | while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ; |
389 | ||
390 | MCFGPIO_PBCDPAR = 0xc0; | |
9acb626f HS |
391 | |
392 | /* Set up the GPIO ports */ | |
6d0f6bcf JCPV |
393 | #ifdef CONFIG_SYS_PEPAR |
394 | MCFGPIO_PEPAR = CONFIG_SYS_PEPAR; | |
9acb626f | 395 | #endif |
6d0f6bcf JCPV |
396 | #ifdef CONFIG_SYS_PFPAR |
397 | MCFGPIO_PFPAR = CONFIG_SYS_PFPAR; | |
9acb626f | 398 | #endif |
6d0f6bcf JCPV |
399 | #ifdef CONFIG_SYS_PJPAR |
400 | MCFGPIO_PJPAR = CONFIG_SYS_PJPAR; | |
9acb626f | 401 | #endif |
6d0f6bcf JCPV |
402 | #ifdef CONFIG_SYS_PSDPAR |
403 | MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR; | |
9acb626f | 404 | #endif |
6d0f6bcf JCPV |
405 | #ifdef CONFIG_SYS_PASPAR |
406 | MCFGPIO_PASPAR = CONFIG_SYS_PASPAR; | |
9acb626f | 407 | #endif |
6d0f6bcf JCPV |
408 | #ifdef CONFIG_SYS_PEHLPAR |
409 | MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; | |
9acb626f | 410 | #endif |
6d0f6bcf JCPV |
411 | #ifdef CONFIG_SYS_PQSPAR |
412 | MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR; | |
9acb626f | 413 | #endif |
6d0f6bcf JCPV |
414 | #ifdef CONFIG_SYS_PTCPAR |
415 | MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR; | |
9acb626f | 416 | #endif |
6d0f6bcf JCPV |
417 | #ifdef CONFIG_SYS_PTDPAR |
418 | MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR; | |
9acb626f | 419 | #endif |
6d0f6bcf JCPV |
420 | #ifdef CONFIG_SYS_PUAPAR |
421 | MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR; | |
9acb626f HS |
422 | #endif |
423 | ||
6d0f6bcf JCPV |
424 | #ifdef CONFIG_SYS_DDRUA |
425 | MCFGPIO_DDRUA = CONFIG_SYS_DDRUA; | |
9acb626f HS |
426 | #endif |
427 | ||
428 | /* This is probably a bad place to setup chip selects, but everyone | |
429 | else is doing it! */ | |
430 | ||
6d0f6bcf JCPV |
431 | #if defined(CONFIG_SYS_CS0_BASE) & defined(CONFIG_SYS_CS0_SIZE) & \ |
432 | defined(CONFIG_SYS_CS0_WIDTH) & defined(CONFIG_SYS_CS0_WS) | |
9acb626f | 433 | |
6d0f6bcf | 434 | MCFCSM_CSAR0 = (CONFIG_SYS_CS0_BASE >> 16) & 0xFFFF; |
83ec20bc | 435 | |
6d0f6bcf JCPV |
436 | #if (CONFIG_SYS_CS0_WIDTH == 8) |
437 | #define CONFIG_SYS_CS0_PS MCFCSM_CSCR_PS_8 | |
438 | #elif (CONFIG_SYS_CS0_WIDTH == 16) | |
439 | #define CONFIG_SYS_CS0_PS MCFCSM_CSCR_PS_16 | |
440 | #elif (CONFIG_SYS_CS0_WIDTH == 32) | |
441 | #define CONFIG_SYS_CS0_PS MCFCSM_CSCR_PS_32 | |
9acb626f | 442 | #else |
6d0f6bcf | 443 | #error "CONFIG_SYS_CS0_WIDTH: Fault - wrong bus with for CS0" |
83ec20bc | 444 | #endif |
6d0f6bcf JCPV |
445 | MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CONFIG_SYS_CS0_WS) |
446 | | CONFIG_SYS_CS0_PS | MCFCSM_CSCR_AA; | |
83ec20bc | 447 | |
6d0f6bcf JCPV |
448 | #if (CONFIG_SYS_CS0_RO != 0) |
449 | MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS0_SIZE - 1) | |
83ec20bc TL |
450 | | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; |
451 | #else | |
6d0f6bcf | 452 | MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS0_SIZE - 1) | MCFCSM_CSMR_V; |
83ec20bc TL |
453 | #endif |
454 | #else | |
4cb4e654 | 455 | #warning "Chip Select 0 are not initialized/used" |
9acb626f HS |
456 | #endif |
457 | ||
6d0f6bcf JCPV |
458 | #if defined(CONFIG_SYS_CS1_BASE) & defined(CONFIG_SYS_CS1_SIZE) & \ |
459 | defined(CONFIG_SYS_CS1_WIDTH) & defined(CONFIG_SYS_CS1_WS) | |
9acb626f | 460 | |
6d0f6bcf | 461 | MCFCSM_CSAR1 = (CONFIG_SYS_CS1_BASE >> 16) & 0xFFFF; |
9acb626f | 462 | |
6d0f6bcf JCPV |
463 | #if (CONFIG_SYS_CS1_WIDTH == 8) |
464 | #define CONFIG_SYS_CS1_PS MCFCSM_CSCR_PS_8 | |
465 | #elif (CONFIG_SYS_CS1_WIDTH == 16) | |
466 | #define CONFIG_SYS_CS1_PS MCFCSM_CSCR_PS_16 | |
467 | #elif (CONFIG_SYS_CS1_WIDTH == 32) | |
468 | #define CONFIG_SYS_CS1_PS MCFCSM_CSCR_PS_32 | |
83ec20bc | 469 | #else |
6d0f6bcf | 470 | #error "CONFIG_SYS_CS1_WIDTH: Fault - wrong bus with for CS1" |
83ec20bc | 471 | #endif |
6d0f6bcf JCPV |
472 | MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CONFIG_SYS_CS1_WS) |
473 | | CONFIG_SYS_CS1_PS | MCFCSM_CSCR_AA; | |
83ec20bc | 474 | |
6d0f6bcf JCPV |
475 | #if (CONFIG_SYS_CS1_RO != 0) |
476 | MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS1_SIZE - 1) | |
83ec20bc TL |
477 | | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; |
478 | #else | |
6d0f6bcf | 479 | MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS1_SIZE - 1) |
83ec20bc TL |
480 | | MCFCSM_CSMR_V; |
481 | #endif | |
9acb626f | 482 | #else |
83ec20bc | 483 | #warning "Chip Select 1 are not initialized/used" |
9acb626f HS |
484 | #endif |
485 | ||
6d0f6bcf JCPV |
486 | #if defined(CONFIG_SYS_CS2_BASE) & defined(CONFIG_SYS_CS2_SIZE) & \ |
487 | defined(CONFIG_SYS_CS2_WIDTH) & defined(CONFIG_SYS_CS2_WS) | |
9acb626f | 488 | |
6d0f6bcf | 489 | MCFCSM_CSAR2 = (CONFIG_SYS_CS2_BASE >> 16) & 0xFFFF; |
9acb626f | 490 | |
6d0f6bcf JCPV |
491 | #if (CONFIG_SYS_CS2_WIDTH == 8) |
492 | #define CONFIG_SYS_CS2_PS MCFCSM_CSCR_PS_8 | |
493 | #elif (CONFIG_SYS_CS2_WIDTH == 16) | |
494 | #define CONFIG_SYS_CS2_PS MCFCSM_CSCR_PS_16 | |
495 | #elif (CONFIG_SYS_CS2_WIDTH == 32) | |
496 | #define CONFIG_SYS_CS2_PS MCFCSM_CSCR_PS_32 | |
9acb626f | 497 | #else |
6d0f6bcf | 498 | #error "CONFIG_SYS_CS2_WIDTH: Fault - wrong bus with for CS2" |
83ec20bc | 499 | #endif |
6d0f6bcf JCPV |
500 | MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CONFIG_SYS_CS2_WS) |
501 | | CONFIG_SYS_CS2_PS | MCFCSM_CSCR_AA; | |
83ec20bc | 502 | |
6d0f6bcf JCPV |
503 | #if (CONFIG_SYS_CS2_RO != 0) |
504 | MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS2_SIZE - 1) | |
83ec20bc TL |
505 | | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; |
506 | #else | |
6d0f6bcf | 507 | MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS2_SIZE - 1) |
83ec20bc TL |
508 | | MCFCSM_CSMR_V; |
509 | #endif | |
510 | #else | |
511 | #warning "Chip Select 2 are not initialized/used" | |
9acb626f HS |
512 | #endif |
513 | ||
6d0f6bcf JCPV |
514 | #if defined(CONFIG_SYS_CS3_BASE) & defined(CONFIG_SYS_CS3_SIZE) & \ |
515 | defined(CONFIG_SYS_CS3_WIDTH) & defined(CONFIG_SYS_CS3_WS) | |
9acb626f | 516 | |
6d0f6bcf | 517 | MCFCSM_CSAR3 = (CONFIG_SYS_CS3_BASE >> 16) & 0xFFFF; |
9acb626f | 518 | |
6d0f6bcf JCPV |
519 | #if (CONFIG_SYS_CS3_WIDTH == 8) |
520 | #define CONFIG_SYS_CS3_PS MCFCSM_CSCR_PS_8 | |
521 | #elif (CONFIG_SYS_CS3_WIDTH == 16) | |
522 | #define CONFIG_SYS_CS3_PS MCFCSM_CSCR_PS_16 | |
523 | #elif (CONFIG_SYS_CS3_WIDTH == 32) | |
524 | #define CONFIG_SYS_CS3_PS MCFCSM_CSCR_PS_32 | |
83ec20bc | 525 | #else |
6d0f6bcf | 526 | #error "CONFIG_SYS_CS3_WIDTH: Fault - wrong bus with for CS1" |
83ec20bc | 527 | #endif |
6d0f6bcf JCPV |
528 | MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CONFIG_SYS_CS3_WS) |
529 | | CONFIG_SYS_CS3_PS | MCFCSM_CSCR_AA; | |
83ec20bc | 530 | |
6d0f6bcf JCPV |
531 | #if (CONFIG_SYS_CS3_RO != 0) |
532 | MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS3_SIZE - 1) | |
83ec20bc TL |
533 | | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; |
534 | #else | |
6d0f6bcf | 535 | MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS3_SIZE - 1) |
83ec20bc TL |
536 | | MCFCSM_CSMR_V; |
537 | #endif | |
9acb626f | 538 | #else |
83ec20bc | 539 | #warning "Chip Select 3 are not initialized/used" |
9acb626f HS |
540 | #endif |
541 | ||
83ec20bc | 542 | #endif /* CONFIG_MONITOR_IS_IN_RAM */ |
bf9e3b38 | 543 | |
9acb626f HS |
544 | /* defer enabling cache until boot (see do_go) */ |
545 | /* icache_enable(); */ | |
bf9e3b38 WD |
546 | } |
547 | ||
548 | /* | |
549 | * initialize higher level parts of CPU like timers | |
550 | */ | |
83ec20bc | 551 | int cpu_init_r(void) |
bf9e3b38 WD |
552 | { |
553 | return (0); | |
554 | } | |
83ec20bc TL |
555 | |
556 | void uart_port_conf(void) | |
557 | { | |
558 | /* Setup Ports: */ | |
6d0f6bcf | 559 | switch (CONFIG_SYS_UART_PORT) { |
83ec20bc TL |
560 | case 0: |
561 | MCFGPIO_PUAPAR &= 0xFc; | |
562 | MCFGPIO_PUAPAR |= 0x03; | |
563 | break; | |
564 | case 1: | |
565 | MCFGPIO_PUAPAR &= 0xF3; | |
566 | MCFGPIO_PUAPAR |= 0x0C; | |
567 | break; | |
568 | case 2: | |
569 | MCFGPIO_PASPAR &= 0xFF0F; | |
570 | MCFGPIO_PASPAR |= 0x00A0; | |
571 | break; | |
572 | } | |
573 | } | |
bf9e3b38 | 574 | #endif |
8c725b93 SR |
575 | |
576 | #if defined(CONFIG_M5249) | |
577 | /* | |
578 | * Breath some life into the CPU... | |
579 | * | |
580 | * Set up the memory map, | |
581 | * initialize a bunch of registers, | |
582 | * initialize the UPM's | |
583 | */ | |
83ec20bc | 584 | void cpu_init_f(void) |
8c725b93 | 585 | { |
8c725b93 SR |
586 | /* |
587 | * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins | |
83ec20bc TL |
588 | * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins |
589 | * which is their primary function. | |
590 | * ~Jeremy | |
8c725b93 | 591 | */ |
6d0f6bcf JCPV |
592 | mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC); |
593 | mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC); | |
594 | mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN); | |
595 | mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN); | |
596 | mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT); | |
597 | mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT); | |
8c725b93 SR |
598 | |
599 | /* | |
600 | * dBug Compliance: | |
601 | * You can verify these values by using dBug's 'ird' | |
602 | * (Internal Register Display) command | |
603 | * ~Jeremy | |
604 | * | |
977b50f8 | 605 | */ |
83ec20bc | 606 | mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ |
8c725b93 SR |
607 | mbar_writeByte(MCFSIM_SYPCR, 0x00); |
608 | mbar_writeByte(MCFSIM_SWIVR, 0x0f); | |
609 | mbar_writeByte(MCFSIM_SWSR, 0x00); | |
610 | mbar_writeLong(MCFSIM_IMR, 0xfffffbff); | |
611 | mbar_writeByte(MCFSIM_SWDICR, 0x00); | |
612 | mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); | |
613 | mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); | |
614 | mbar_writeByte(MCFSIM_I2CICR, 0x00); | |
615 | mbar_writeByte(MCFSIM_UART1ICR, 0x00); | |
616 | mbar_writeByte(MCFSIM_UART2ICR, 0x00); | |
617 | mbar_writeByte(MCFSIM_ICR6, 0x00); | |
618 | mbar_writeByte(MCFSIM_ICR7, 0x00); | |
619 | mbar_writeByte(MCFSIM_ICR8, 0x00); | |
620 | mbar_writeByte(MCFSIM_ICR9, 0x00); | |
621 | mbar_writeByte(MCFSIM_QSPIICR, 0x00); | |
622 | ||
623 | mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); | |
977b50f8 | 624 | mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ |
8c725b93 | 625 | mbar2_writeByte(MCFSIM_SPURVEC, 0x00); |
83ec20bc | 626 | mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ |
8c725b93 SR |
627 | |
628 | /* Setup interrupt priorities for gpio7 */ | |
629 | /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */ | |
630 | ||
631 | /* IDE Config registers */ | |
632 | mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); | |
633 | mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000); | |
634 | ||
635 | /* | |
636 | * Setup chip selects... | |
637 | */ | |
638 | ||
6d0f6bcf JCPV |
639 | mbar_writeShort(MCFSIM_CSAR1, CONFIG_SYS_CSAR1); |
640 | mbar_writeShort(MCFSIM_CSCR1, CONFIG_SYS_CSCR1); | |
641 | mbar_writeLong(MCFSIM_CSMR1, CONFIG_SYS_CSMR1); | |
8c725b93 | 642 | |
6d0f6bcf JCPV |
643 | mbar_writeShort(MCFSIM_CSAR0, CONFIG_SYS_CSAR0); |
644 | mbar_writeShort(MCFSIM_CSCR0, CONFIG_SYS_CSCR0); | |
645 | mbar_writeLong(MCFSIM_CSMR0, CONFIG_SYS_CSMR0); | |
8c725b93 SR |
646 | |
647 | /* enable instruction cache now */ | |
648 | icache_enable(); | |
649 | } | |
650 | ||
651 | /* | |
652 | * initialize higher level parts of CPU like timers | |
653 | */ | |
83ec20bc | 654 | int cpu_init_r(void) |
8c725b93 SR |
655 | { |
656 | return (0); | |
657 | } | |
83ec20bc TL |
658 | |
659 | void uart_port_conf(void) | |
660 | { | |
661 | /* Setup Ports: */ | |
6d0f6bcf | 662 | switch (CONFIG_SYS_UART_PORT) { |
83ec20bc TL |
663 | case 0: |
664 | break; | |
665 | case 1: | |
666 | break; | |
667 | } | |
668 | } | |
669 | #endif /* #if defined(CONFIG_M5249) */ |