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Add support for multiple PHYs.
[people/ms/u-boot.git] / cpu / mcf52x2 / fec.c
CommitLineData
bf9e3b38
WD		 1/*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <malloc.h>
26#include <asm/fec.h>
27
28#ifdef CONFIG_M5272
29#include <asm/m5272.h>
30#include <asm/immap_5272.h>
31#endif
32
33#ifdef CONFIG_M5282
34#include <asm/m5282.h>
35#include <asm/immap_5282.h>
36#endif
37
38#include <net.h>
39#include <command.h>
40
41#ifdef CONFIG_M5272
42#define FEC_ADDR (CFG_MBAR + 0x840)
43#endif
44#ifdef CONFIG_M5282
45#define FEC_ADDR (CFG_MBAR + 0x1000)
46#endif
47
48#undef ET_DEBUG
49#undef MII_DEBUG
50
51#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
52
53#ifdef CFG_DISCOVER_PHY
54#include <miiphy.h>
55static void mii_discover_phy (void);
56#endif
57
58/* Ethernet Transmit and Receive Buffers */
59#define DBUF_LENGTH 1520
60
61#define TX_BUF_CNT 2
62
63#define TOUT_LOOP 100
64
65#define PKT_MAXBUF_SIZE 1518
66#define PKT_MINBUF_SIZE 64
67#define PKT_MAXBLR_SIZE 1520
68
69
70static char txbuf[DBUF_LENGTH];
71
72static uint rxIdx; /* index of the current RX buffer */
73static uint txIdx; /* index of the current TX buffer */
74
75/*
76 * FEC Ethernet Tx and Rx buffer descriptors allocated at the
77 * immr->udata_bd address on Dual-Port RAM
78 * Provide for Double Buffering
79 */
80
81typedef volatile struct CommonBufferDescriptor {
82 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
83 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
84} RTXBD;
85
86static RTXBD *rtx = NULL;
87
88int eth_send (volatile void *packet, int length)
89{
90 int j, rc;
91 volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
92
93 /* section 16.9.23.3
94 * Wait for ready
95 */
96 j = 0;
97 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
98 && (j < TOUT_LOOP)) {
99 udelay (1);
100 j++;
101 }
102 if (j >= TOUT_LOOP) {
103 printf ("TX not ready\n");
104 }
105
106 rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
107 rtx->txbd[txIdx].cbd_datlen = length;
108 rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
109
110 /* Activate transmit Buffer Descriptor polling */
111 fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
112
113 j = 0;
114 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
115 && (j < TOUT_LOOP)) {
116 udelay (1);
117 j++;
118 }
119 if (j >= TOUT_LOOP) {
120 printf ("TX timeout\n");
121 }
122#ifdef ET_DEBUG
123 printf ("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
124 __FILE__, __LINE__, __FUNCTION__, j, rtx->txbd[txIdx].cbd_sc,
125 (rtx->txbd[txIdx].cbd_sc & 0x003C) >> 2);
126#endif
127
128 /* return only status bits */ ;
129 rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
130
131 txIdx = (txIdx + 1) % TX_BUF_CNT;
132
133 return rc;
134}
135
136int eth_rx (void)
137{
138 int length;
139 volatile fec_t *fecp = (fec_t *) FEC_ADDR;
140
141 for (;;) {
142 /* section 16.9.23.2 */
143 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
144 length = -1;
145 break; /* nothing received - leave for() loop */
146 }
147
148 length = rtx->rxbd[rxIdx].cbd_datlen;
149
150 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
151#ifdef ET_DEBUG
152 printf ("%s[%d] err: %x\n",
153 __FUNCTION__, __LINE__,
154 rtx->rxbd[rxIdx].cbd_sc);
155#endif
156 } else {
157 /* Pass the packet up to the protocol layers. */
158 NetReceive (NetRxPackets[rxIdx], length - 4);
159 }
160
161 /* Give the buffer back to the FEC. */
162 rtx->rxbd[rxIdx].cbd_datlen = 0;
163
164 /* wrap around buffer index when necessary */
165 if ((rxIdx + 1) >= PKTBUFSRX) {
166 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
167 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
168 rxIdx = 0;
169 } else {
170 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
171 rxIdx++;
172 }
173
174 /* Try to fill Buffer Descriptors */
175 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
176 }
177
178 return length;
179}
180
181/**************************************************************
182 *
183 * FEC Ethernet Initialization Routine
184 *
185 *************************************************************/
186#define FEC_ECNTRL_ETHER_EN 0x00000002
187#define FEC_ECNTRL_RESET 0x00000001
188
189#define FEC_RCNTRL_BC_REJ 0x00000010
190#define FEC_RCNTRL_PROM 0x00000008
191#define FEC_RCNTRL_MII_MODE 0x00000004
192#define FEC_RCNTRL_DRT 0x00000002
193#define FEC_RCNTRL_LOOP 0x00000001
194
195#define FEC_TCNTRL_FDEN 0x00000004
196#define FEC_TCNTRL_HBC 0x00000002
197#define FEC_TCNTRL_GTS 0x00000001
198
199#define FEC_RESET_DELAY 50000
200
201int eth_init (bd_t * bd)
202{
203
204 int i;
205 volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
206
207 /* Whack a reset.
208 * A delay is required between a reset of the FEC block and
209 * initialization of other FEC registers because the reset takes
210 * some time to complete. If you don't delay, subsequent writes
211 * to FEC registers might get killed by the reset routine which is
212 * still in progress.
213 */
214 fecp->fec_ecntrl = FEC_ECNTRL_RESET;
215 for (i = 0;
216 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
217 ++i) {
218 udelay (1);
219 }
220 if (i == FEC_RESET_DELAY) {
221 printf ("FEC_RESET_DELAY timeout\n");
222 return 0;
223 }
224
225 /* We use strictly polling mode only
226 */
227 fecp->fec_imask = 0;
228
229 /* Clear any pending interrupt */
230 fecp->fec_ievent = 0xffffffff;
231
232 /* Set station address */
233#define ea bd->bi_enetaddr
234 fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) |
235 (ea[2] << 8) | (ea[3]);
236 fecp->fec_addr_high = (ea[4] << 24) | (ea[5] << 16);
237#ifdef ET_DEBUG
238 printf ("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n",
239 ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]);
240#endif
241#undef ea
242
243 /* Clear multicast address hash table
244 */
245 fecp->fec_hash_table_high = 0;
246 fecp->fec_hash_table_low = 0;
247
248 /* Set maximum receive buffer size.
249 */
250 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
251
252 /*
253 * Setup Buffers and Buffer Desriptors
254 */
255 rxIdx = 0;
256 txIdx = 0;
257
258 if (!rtx) {
259 rtx = (RTXBD *) CFG_ENET_BD_BASE;
260 }
261
262 /*
263 * Setup Receiver Buffer Descriptors (13.14.24.18)
264 * Settings:
265 * Empty, Wrap
266 */
267 for (i = 0; i < PKTBUFSRX; i++) {
268 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
269 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
270 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
271 }
272 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
273
274 /*
275 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
276 * Settings:
277 * Last, Tx CRC
278 */
279 for (i = 0; i < TX_BUF_CNT; i++) {
280 rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
281 rtx->txbd[i].cbd_datlen = 0; /* Reset */
282 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
283 }
284 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
285
286 /* Set receive and transmit descriptor base
287 */
288 fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
289 fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
290
291 /* Enable MII mode
292 */
293#if 0 /* Full duplex mode */
294 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
295 fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
296#else /* Half duplex mode */
297 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
298 fecp->fec_x_cntrl = 0;
299#endif
300 /* Set MII speed */
301 fecp->fec_mii_speed = 0x0e;
302
303 /* Configure port B for MII.
304 */
305 /* port initialization was already made in cpu_init_f() */
306
307 /* Now enable the transmit and receive processing
308 */
309 fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
310
311#ifdef CFG_DISCOVER_PHY
312 /* wait for the PHY to wake up after reset */
313 mii_discover_phy ();
314#endif
315
316 /* And last, try to fill Rx Buffer Descriptors */
317 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
318
319 return 1;
320}
321
322void eth_halt (void)
323{
324 volatile fec_t *fecp = (fec_t *) FEC_ADDR;
325
326 fecp->fec_ecntrl = 0;
327}
328
329
330#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
331
332static int phyaddr = -1; /* didn't find a PHY yet */
333static uint phytype;
334
335/* Make MII read/write commands for the FEC.
336*/
337
338#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
339 (REG & 0x1f) << 18))
340
341#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
342 (REG & 0x1f) << 18) | \
343 (VAL & 0xffff))
344
345/* Interrupt events/masks.
346*/
347#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
348#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
349#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
350#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
351#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
352#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
353#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
354#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
355#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
356#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
357
358/* PHY identification
359 */
360#define PHY_ID_LXT970 0x78100000 /* LXT970 */
361#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
362#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
363#define PHY_ID_QS6612 0x01814400 /* QS6612 */
364#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
365#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
366#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
367
368/* send command to phy using mii, wait for result */
369static uint mii_send (uint mii_cmd)
370{
371 uint mii_reply;
372 volatile fec_t *ep = (fec_t *) (FEC_ADDR);
373
374 ep->fec_mii_data = mii_cmd; /* command to phy */
375
376 /* wait for mii complete */
377 while (!(ep->fec_ievent & FEC_ENET_MII)); /* spin until done */
378 mii_reply = ep->fec_mii_data; /* result from phy */
379 ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
380#ifdef ET_DEBUG
381 printf ("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
382 __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
383#endif
384 return (mii_reply & 0xffff); /* data read from phy */
385}
386#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
387
388#if defined(CFG_DISCOVER_PHY)
389static void mii_discover_phy (void)
390{
391#define MAX_PHY_PASSES 11
392 uint phyno;
393 int pass;
394
395 phyaddr = -1; /* didn't find a PHY yet */
396 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
397 if (pass > 1) {
398 /* PHY may need more time to recover from reset.
399 * The LXT970 needs 50ms typical, no maximum is
400 * specified, so wait 10ms before try again.
401 * With 11 passes this gives it 100ms to wake up.
402 */
403 udelay (10000); /* wait 10ms */
404 }
405 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
406 phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1));
407#ifdef ET_DEBUG
408 printf ("PHY type 0x%x pass %d type ", phytype, pass);
409#endif
410 if (phytype != 0xffff) {
411 phyaddr = phyno;
412 phytype <<= 16;
413 phytype |= mii_send (mk_mii_read (phyno,
414 PHY_PHYIDR2));
415
416#ifdef ET_DEBUG
417 printf ("PHY @ 0x%x pass %d type ", phyno,
418 pass);
419 switch (phytype & 0xfffffff0) {
420 case PHY_ID_LXT970:
421 printf ("LXT970\n");
422 break;
423 case PHY_ID_LXT971:
424 printf ("LXT971\n");
425 break;
426 case PHY_ID_82555:
427 printf ("82555\n");
428 break;
429 case PHY_ID_QS6612:
430 printf ("QS6612\n");
431 break;
432 case PHY_ID_AMD79C784:
433 printf ("AMD79C784\n");
434 break;
435 case PHY_ID_LSI80225B:
436 printf ("LSI L80225/B\n");
437 break;
438 default:
439 printf ("0x%08x\n", phytype);
440 break;
441 }
442#endif
443 }
444 }
445 }
446 if (phyaddr < 0) {
447 printf ("No PHY device found.\n");
448 }
449}
450#endif /* CFG_DISCOVER_PHY */
451
452#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
453
454static int mii_init_done = 0;
455
456/****************************************************************************
457 * mii_init -- Initialize the MII for MII command without ethernet
458 * This function is a subset of eth_init
459 ****************************************************************************
460 */
461void mii_init (void)
462{
463 volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
464
465 int i;
466
467 if (mii_init_done != 0) {
468 return;
469 }
470
471 /* Whack a reset.
472 * A delay is required between a reset of the FEC block and
473 * initialization of other FEC registers because the reset takes
474 * some time to complete. If you don't delay, subsequent writes
475 * to FEC registers might get killed by the reset routine which is
476 * still in progress.
477 */
478
479 fecp->fec_ecntrl = FEC_ECNTRL_RESET;
480 for (i = 0;
481 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
482 ++i) {
483 udelay (1);
484 }
485 if (i == FEC_RESET_DELAY) {
486 printf ("FEC_RESET_DELAY timeout\n");
487 return;
488 }
489
490 /* We use strictly polling mode only
491 */
492 fecp->fec_imask = 0;
493
494 /* Clear any pending interrupt
495 */
496 fecp->fec_ievent = 0xffffffff;
497
498 /* Set MII speed */
499 fecp->fec_mii_speed = 0x0e;
500
501 /* Configure port B for MII.
502 */
503 /* port initialization was already made in cpu_init_f() */
504
505 /* Now enable the transmit and receive processing */
506 fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
507
508 mii_init_done = 1;
509}
510
511/*****************************************************************************
512 * Read and write a MII PHY register, routines used by MII Utilities
513 *
514 * FIXME: These routines are expected to return 0 on success, but mii_send
515 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
516 * no PHY connected...
517 * For now always return 0.
518 * FIXME: These routines only work after calling eth_init() at least once!
519 * Otherwise they hang in mii_send() !!! Sorry!
520 *****************************************************************************/
521
63ff004c
MB		 522int mcf52x2_miiphy_read (char *devname, unsigned char addr,
523 unsigned char reg, unsigned short *value)
bf9e3b38
WD		 524{
525 short rdreg; /* register working value */
526
527#ifdef MII_DEBUG
528 printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
529#endif
530 rdreg = mii_send (mk_mii_read (addr, reg));
531
532 *value = rdreg;
533
534#ifdef MII_DEBUG
535 printf ("0x%04x\n", *value);
536#endif
537
538 return 0;
539}
540
63ff004c
MB		 541int mcf52x2_miiphy_write (char *devname, unsigned char addr,
542 unsigned char reg, unsigned short value)
bf9e3b38
WD		 543{
544 short rdreg; /* register working value */
545
546#ifdef MII_DEBUG
547 printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
548#endif
549
550 rdreg = mii_send (mk_mii_write (addr, reg, value));
551
552#ifdef MII_DEBUG
553 printf ("0x%04x\n", value);
554#endif
555
556 return 0;
557}
558#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) */
bf9e3b38 559#endif /* CFG_CMD_NET, FEC_ENET */
63ff004c
MB		 560
561int mcf52x2_miiphy_initialize(bd_t *bis)
562{
563#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
564#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
565 miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write);
566#endif
567#endif
568 return 0;
569}
570
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