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bf9e3b38 | 1 | /* |
bf9e3b38 WD |
2 | * (C) Copyright 2000-2004 |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
a1436a84 TL |
5 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
6 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
7 | * | |
bf9e3b38 WD |
8 | * See file CREDITS for list of people who contributed to this |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #include <common.h> | |
28 | #include <watchdog.h> | |
29 | #include <asm/processor.h> | |
83ec20bc | 30 | #include <asm/immap.h> |
eacbd317 | 31 | |
bf9e3b38 | 32 | #ifdef CONFIG_M5272 |
83ec20bc | 33 | int interrupt_init(void) |
bf9e3b38 | 34 | { |
83ec20bc | 35 | volatile intctrl_t *intp = (intctrl_t *) (MMAP_INTC); |
bf9e3b38 | 36 | |
83ec20bc TL |
37 | /* disable all external interrupts */ |
38 | intp->int_icr1 = 0x88888888; | |
39 | intp->int_icr2 = 0x88888888; | |
40 | intp->int_icr3 = 0x88888888; | |
41 | intp->int_icr4 = 0x88888888; | |
42 | intp->int_pitr = 0x00000000; | |
43 | /* initialize vector register */ | |
44 | intp->int_pivr = 0x40; | |
bf9e3b38 | 45 | |
83ec20bc | 46 | enable_interrupts(); |
bf9e3b38 | 47 | |
83ec20bc | 48 | return 0; |
bf9e3b38 WD |
49 | } |
50 | ||
83ec20bc TL |
51 | #if defined(CONFIG_MCFTMR) |
52 | void dtimer_intr_setup(void) | |
bf9e3b38 | 53 | { |
83ec20bc | 54 | volatile intctrl_t *intp = (intctrl_t *) (CFG_INTR_BASE); |
bf9e3b38 | 55 | |
83ec20bc TL |
56 | intp->int_icr1 &= ~INT_ICR1_TMR3MASK; |
57 | intp->int_icr1 |= CFG_TMRINTR_PRI; | |
bf9e3b38 | 58 | } |
83ec20bc TL |
59 | #endif /* CONFIG_MCFTMR */ |
60 | #endif /* CONFIG_M5272 */ | |
bf9e3b38 | 61 | |
f71d9d91 | 62 | #if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275) |
83ec20bc | 63 | int interrupt_init(void) |
bf9e3b38 | 64 | { |
83ec20bc | 65 | volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); |
bf9e3b38 | 66 | |
83ec20bc TL |
67 | /* Make sure all interrupts are disabled */ |
68 | intp->imrl0 |= 0x1; | |
bf9e3b38 | 69 | |
83ec20bc TL |
70 | enable_interrupts(); |
71 | return 0; | |
bf9e3b38 WD |
72 | } |
73 | ||
83ec20bc TL |
74 | #if defined(CONFIG_MCFTMR) |
75 | void dtimer_intr_setup(void) | |
bf9e3b38 | 76 | { |
83ec20bc | 77 | volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); |
bf9e3b38 | 78 | |
83ec20bc | 79 | intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; |
c54f9263 | 80 | intp->imrl0 &= 0xFFFFFFFE; |
83ec20bc | 81 | intp->imrl0 &= ~CFG_TMRINTR_MASK; |
bf9e3b38 | 82 | } |
83ec20bc | 83 | #endif /* CONFIG_MCFTMR */ |
f71d9d91 | 84 | #endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */ |
bf9e3b38 | 85 | |
a1436a84 | 86 | #if defined(CONFIG_M5249) || defined(CONFIG_M5253) |
83ec20bc | 87 | int interrupt_init(void) |
bf9e3b38 | 88 | { |
83ec20bc | 89 | enable_interrupts(); |
bf9e3b38 WD |
90 | |
91 | return 0; | |
92 | } | |
bf9e3b38 | 93 | |
83ec20bc TL |
94 | #if defined(CONFIG_MCFTMR) |
95 | void dtimer_intr_setup(void) | |
8c725b93 | 96 | { |
83ec20bc | 97 | mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); |
a1436a84 | 98 | mbar_writeByte(MCFSIM_TIMER2ICR, CFG_TMRINTR_PRI); |
8c725b93 | 99 | } |
83ec20bc | 100 | #endif /* CONFIG_MCFTMR */ |
a1436a84 | 101 | #endif /* CONFIG_M5249 || CONFIG_M5253 */ |