[people/ms/u-boot.git] / cpu / mcf52x2 / start.S

/*
 * Copyright (C) 2003	Josef Baumgartner <josef.baumgartner@telex.de>
 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include "version.h"

#ifndef	 CONFIG_IDENT_STRING
#define	 CONFIG_IDENT_STRING ""
#endif


#define _START	_start
#define _FAULT	_fault


#define SAVE_ALL						\
	move.w	#0x2700,%sr;		/* disable intrs */	\
	subl	#60,%sp;		/* space for 15 regs */ \
	moveml	%d0-%d7/%a0-%a6,%sp@;				\

#define RESTORE_ALL						\
	moveml	%sp@,%d0-%d7/%a0-%a6;				\
	addl	#60,%sp;		/* space for 15 regs */ \
	rte

/* If we come from a pre-loader we don't need an initial exception
 * table.
 */
#if !defined(CONFIG_MONITOR_IS_IN_RAM)

.text
/*
 *	Vector table. This is used for initial platform startup.
 *	These vectors are to catch any un-intended traps.
 */
_vectors:

.long	0x00000000		/* Flash offset is 0 until we setup CS0 */
#if defined(CONFIG_R5200)
.long	0x400
#elif defined(CONFIG_M5282)
.long	_start - TEXT_BASE
#else
.long	_START
#endif

.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT

.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT

.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT

.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT

#endif

	.text


#if defined(CFG_INT_FLASH_BASE) && \
    (defined(CONFIG_M5282) || defined(CONFIG_M5281))
	#if (TEXT_BASE == CFG_INT_FLASH_BASE)
		.long	0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
		.long	0xFFFFFFFF /* all sectors protected */
		.long	0x00000000 /* supervisor/User restriction */
		.long	0x00000000 /* programm/data space restriction */
		.long	0x00000000 /* Flash security */
	#endif
#endif
	.globl	_start
_start:
	nop
	nop
	move.w #0x2700,%sr

#if defined(CONFIG_M5272) || defined(CONFIG_M5249)
	move.l	#(CFG_MBAR + 1), %d0		/* set MBAR address + valid flag */
	move.c	%d0, %MBAR

	/*** The 5249 has MBAR2 as well ***/
#ifdef CFG_MBAR2
	move.l	#(CFG_MBAR2 + 1), %d0	        /* Get MBAR2 address */
	movec	%d0, #0xc0e		        /* Set MBAR2 */
#endif

	move.l	#(CFG_INIT_RAM_ADDR + 1), %d0
	movec	%d0, %RAMBAR0
#endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */

#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
	/* Initialize IPSBAR */
	move.l	#(CFG_MBAR + 1), %d0		/* set IPSBAR address + valid flag */
	move.l	%d0, 0x40000000

#if defined(CONFIG_M5282)
	/* Initialize RAMBAR1: locate SRAM and validate it */
	move.l	#(CFG_INIT_RAM_ADDR + 0x21), %d0
	movec	%d0, %RAMBAR1

#if (TEXT_BASE == CFG_INT_FLASH_BASE)
	/* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */

	move.l #(_flashbar_setup-CFG_INT_FLASH_BASE), %a0
	move.l #(_flashbar_setup_end-CFG_INT_FLASH_BASE), %a1
	move.l #(CFG_INIT_RAM_ADDR), %a2
_copy_flash:
	move.l (%a0)+, (%a2)+
	cmp.l %a0, %a1
	bgt.s _copy_flash
	jmp CFG_INIT_RAM_ADDR

_flashbar_setup:
	/* Initialize FLASHBAR: locate internal Flash and validate it */
	move.l	#(CFG_INT_FLASH_BASE + 0x21), %d0
	movec	%d0, %RAMBAR0
	jmp _after_flashbar_copy.L	/* Force jump to absolute address */
_flashbar_setup_end:
	nop
_after_flashbar_copy:
#else
	/* Setup code to initialize FLASHBAR, if start from external Memory */
	move.l	#(CFG_INT_FLASH_BASE + 0x21), %d0
	movec	%d0, %RAMBAR0
#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */

#endif
#endif
	/* if we come from a pre-loader we have no exception table and
	 * therefore no VBR to set
	 */
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
	move.l	#CFG_FLASH_BASE, %d0
	movec	%d0, %VBR
#endif

#ifdef	CONFIG_R5200
	move.l	#(_flash_setup-CFG_FLASH_BASE), %a0
	move.l	#(_flash_setup_end-CFG_FLASH_BASE), %a1
	move.l	#(CFG_INIT_RAM_ADDR), %a2
_copy_flash:
	move.l	(%a0)+, (%a2)+
	cmp.l	%a0, %a1
	bgt.s	_copy_flash
	jmp	CFG_INIT_RAM_ADDR
_after_flash_copy:
#endif

#if 0
	/* invalidate and disable cache */
	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
	movec	%d0, %CACR			/* Invalidate cache */
	move.l	#0, %d0
	movec	%d0, %ACR0
	movec	%d0, %ACR1
#endif

	/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
	move.l	#(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
	clr.l %sp@-

	move.l #__got_start, %a5		/* put relocation table address to a5 */

	bsr cpu_init_f				/* run low-level CPU init code (from flash) */
	bsr board_init_f			/* run low-level board init code (from flash) */

	/* board_init_f() does not return */

/*------------------------------------------------------------------------------*/

#ifdef	CONFIG_R5200
_flash_setup:
	/* CSAR0 */
	move.l	#((CFG_FLASH_BASE & 0xffff0000) >> 16), %d0
	move.w	%d0, 0x40000080

	/* CSCR0 */
	move.l	#0x2180, %d0		/* 8 wait states, 16bit port, auto ack,  */
	move.w	%d0, 0x4000008A

	/* CSMR0 */
	move.l	#0x001f0001, %d0	/* 2 MB, valid */
	move.l	%d0, 0x40000084

	jmp	_after_flash_copy.L
_flash_setup_end:
#endif

/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 * r3 = dest
 * r4 = src
 * r5 = length in bytes
 * r6 = cachelinesize
 */
	.globl	relocate_code
relocate_code:
	link.w %a6,#0
	move.l 8(%a6), %sp		/* set new stack pointer */

	move.l 12(%a6), %d0		/* Save copy of Global Data pointer */
	move.l 16(%a6), %a0		/* Save copy of Destination Address */

	move.l #CFG_MONITOR_BASE, %a1
	move.l #__init_end, %a2
	move.l %a0, %a3
	/* copy the code to RAM */
1:
	move.l (%a1)+, (%a3)+
	cmp.l  %a1,%a2
	bgt.s	 1b

/*
 * We are done. Do not return, instead branch to second part of board
 * initialization, now running from RAM.
 */
 	move.l	%a0, %a1
	add.l	#(in_ram - CFG_MONITOR_BASE), %a1
	jmp	(%a1)

in_ram:

clear_bss:
 	/*
	 * Now clear BSS segment
	 */
	move.l	%a0, %a1
	add.l	#(_sbss - CFG_MONITOR_BASE),%a1
	move.l	%a0, %d1
	add.l	#(_ebss - CFG_MONITOR_BASE),%d1
6:
	clr.l	(%a1)+
	cmp.l	%a1,%d1
	bgt.s	6b

	/*
	 * fix got table in RAM
	 */
	move.l	%a0, %a1
	add.l	#(__got_start - CFG_MONITOR_BASE),%a1
	move.l	%a1,%a5		/* * fix got pointer register a5 */

	move.l	%a0, %a2
	add.l	#(__got_end - CFG_MONITOR_BASE),%a2

7:
	move.l	(%a1),%d1
	sub.l	#_start,%d1
	add.l	%a0,%d1
	move.l	%d1,(%a1)+
	cmp.l	%a2, %a1
	bne	7b

#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
	/* patch the 3 accesspoints to 3 ichache_state */
	/* quick and dirty */

	move.l	%a0,%d1
	add.l	#(icache_state - CFG_MONITOR_BASE),%d1
	move.l	%a0,%a1
	add.l	#(icache_state_access_1+2 - CFG_MONITOR_BASE),%a1
	move.l  %d1,(%a1)
	move.l	%a0,%a1
	add.l	#(icache_state_access_2+2 - CFG_MONITOR_BASE),%a1
	move.l  %d1,(%a1)
	move.l	%a0,%a1
	add.l	#(icache_state_access_3+2 - CFG_MONITOR_BASE),%a1
	move.l  %d1,(%a1)
#endif

	/* calculate relative jump to board_init_r in ram */
	move.l %a0, %a1
	add.l #(board_init_r - CFG_MONITOR_BASE), %a1

	/* set parameters for board_init_r */
	move.l %a0,-(%sp)		/* dest_addr */
	move.l %d0,-(%sp)		/* gd */
	#if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \
	    defined(CFG_HALT_BEFOR_RAM_JUMP)
 		halt
	#endif
	jsr	(%a1)

/*------------------------------------------------------------------------------*/
/* exception code */
	.globl _fault
_fault:
	jmp _fault

	.globl	_exc_handler
_exc_handler:
	SAVE_ALL
	movel	%sp,%sp@-
	bsr exc_handler
	addql	#4,%sp
	RESTORE_ALL

	.globl	_int_handler
_int_handler:
	SAVE_ALL
	movel	%sp,%sp@-
	bsr int_handler
	addql	#4,%sp
	RESTORE_ALL

/*------------------------------------------------------------------------------*/
/* cache functions */
#ifdef	CONFIG_M5272
	.globl	icache_enable
icache_enable:
	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
	movec	%d0, %CACR			/* Invalidate cache */
	move.l	#0x0000c000, %d0		/* Setup cache mask */
	movec	%d0, %ACR0			/* Enable cache */
	move.l	#0xff00c000, %d0		/* Setup cache mask */
	movec	%d0, %ACR1			/* Enable cache */
	move.l	#0x80000100, %d0		/* Setup cache mask */
	movec	%d0, %CACR			/* Enable cache */
	moveq	#1, %d0
	move.l	%d0, icache_state
	rts
#endif

#ifdef CONFIG_M5282
	.globl	icache_enable
icache_enable:
	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
	movec	%d0, %CACR			/* Invalidate cache */
	move.l	#0x0000c000, %d0		/* Setup cache mask */
	movec	%d0, %ACR0			/* Enable cache */
	move.l	#0xff00c000, %d0		/* Setup cache mask */
	movec	%d0, %ACR1			/* Enable cache */
	move.l	#0x80400100, %d0		/* Setup cache mask, data cache disabel*/
	movec	%d0, %CACR			/* Enable cache */
	moveq	#1, %d0
icache_state_access_1:
	move.l	%d0, icache_state
	rts
#endif

#ifdef CONFIG_M5249
	.globl	icache_enable
icache_enable:
	/*
	 *  Note: The 5249 Documentation doesn't give a bit position for CINV!
	 *  From the 5272 and the 5307 documentation, I have deduced that it is
	 *  probably CACR[24]. Should someone say something to Motorola?
	 *  	~Jeremy
	 */
	move.l	#0x01000000, %d0		/* Invalidate whole cache */
	move.c	%d0,%CACR
	move.l	#0xff00c000, %d0		/* Set FLASH cachable: always match (SM=0b10) */
	move.c	%d0, %ACR0
	move.l	#0x0000c000, %d0		/* Set SDRAM cachable: always match (SM=0b10) */
	move.c	%d0, %ACR1
	move.l	#0x90000200, %d0		/* Set cache enable cmd */
	move.c	%d0,%CACR
	moveq	#1, %d0
	move.l	%d0, icache_state
	rts
#endif

	.globl	icache_disable
icache_disable:
	move.l	#0x00000100, %d0		/* Setup cache mask */
	movec	%d0, %CACR			/* Enable cache */
	clr.l	%d0				/* Setup cache mask */
	movec	%d0, %ACR0			/* Enable cache */
	movec	%d0, %ACR1			/* Enable cache */
	moveq	#0, %d0
icache_state_access_2:
	move.l	%d0, icache_state
	rts

	.globl	icache_status
icache_status:
icache_state_access_3:
	move.l	icache_state, %d0
	rts

	.data
icache_state:
	.long	0	/* cache is diabled on inirialization */

/*------------------------------------------------------------------------------*/

	.globl	version_string
version_string:
	.ascii U_BOOT_VERSION
	.ascii " (", __DATE__, " - ", __TIME__, ")"
	.ascii CONFIG_IDENT_STRING, "\0"
Commit	Line	Data
bf9e3b38 WD	1	/*
	2	* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
	3	* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <config.h>
	25	#include "version.h"
	26
	27	#ifndef CONFIG_IDENT_STRING
	28	#define CONFIG_IDENT_STRING ""
	29	#endif
	30
	31
	32	#define _START _start
	33	#define _FAULT _fault
	34
	35
	36	#define SAVE_ALL \
	37	move.w #0x2700,%sr; /* disable intrs */ \
	38	subl #60,%sp; /* space for 15 regs */ \
	39	moveml %d0-%d7/%a0-%a6,%sp@; \
	40
	41	#define RESTORE_ALL \
	42	moveml %sp@,%d0-%d7/%a0-%a6; \
	43	addl #60,%sp; /* space for 15 regs */ \
	44	rte
	45
	46	/* If we come from a pre-loader we don't need an initial exception
	47	* table.
	48	*/
	49	#if !defined(CONFIG_MONITOR_IS_IN_RAM)
	50
	51	.text
	52	/*
	53	* Vector table. This is used for initial platform startup.
	54	* These vectors are to catch any un-intended traps.
	55	*/
	56	_vectors:
	57
4176c799 WD	58	.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
	59	#if defined(CONFIG_R5200)
	60	.long 0x400
	61	#elif defined(CONFIG_M5282)
9acb626f	62	.long _start - TEXT_BASE
eacbd317	63	#else
4176c799	64	.long _START
eacbd317	65	#endif
4176c799	66
bf9e3b38 WD	67	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	68	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	69	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	70	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	71	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	72	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	73	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	74	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	75
	76	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	77	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	78	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	79	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	80	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	81	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	82	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	83	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	84
	85	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	86	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	87	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	88	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	89	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	90	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	91	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	92	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	93
	94	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	95	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	96	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	97	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	98	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	99	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	100	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	101	.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
	102
	103	#endif
	104
	105	.text
	106
9acb626f HS	107
	108	#if defined(CFG_INT_FLASH_BASE) && \
	109	(defined(CONFIG_M5282) \|\| defined(CONFIG_M5281))
	110	#if (TEXT_BASE == CFG_INT_FLASH_BASE)
	111	.long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
	112	.long 0xFFFFFFFF /* all sectors protected */
	113	.long 0x00000000 /* supervisor/User restriction */
	114	.long 0x00000000 /* programm/data space restriction */
	115	.long 0x00000000 /* Flash security */
	116	#endif
	117	#endif
bf9e3b38 WD	118	.globl _start
	119	_start:
	120	nop
	121	nop
	122	move.w #0x2700,%sr
	123
8c725b93	124	#if defined(CONFIG_M5272) \|\| defined(CONFIG_M5249)
bf9e3b38 WD	125	move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */
	126	move.c %d0, %MBAR
	127
8c725b93 SR	128	/* The 5249 has MBAR2 as well */
	129	#ifdef CFG_MBAR2
	130	move.l #(CFG_MBAR2 + 1), %d0 /* Get MBAR2 address */
	131	movec %d0, #0xc0e /* Set MBAR2 */
	132	#endif
	133
bf9e3b38 WD	134	move.l #(CFG_INIT_RAM_ADDR + 1), %d0
bf9e3b38 WD	135	movec %d0, %RAMBAR0
8c725b93	136	#endif /* #if defined(CONFIG_M5272) \|\| defined(CONFIG_M5249) */
bf9e3b38	137
4176c799	138	#if defined(CONFIG_M5282) \|\| defined(CONFIG_M5271)
bf9e3b38 WD	139	/* Initialize IPSBAR */
	140	move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
	141	move.l %d0, 0x40000000
	142
6741ae92	143	#if defined(CONFIG_M5282)
9acb626f HS	144	/* Initialize RAMBAR1: locate SRAM and validate it */
	145	move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
	146	movec %d0, %RAMBAR1
	147
	148	#if (TEXT_BASE == CFG_INT_FLASH_BASE)
	149	/* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
	150
	151	move.l #(_flashbar_setup-CFG_INT_FLASH_BASE), %a0
	152	move.l #(_flashbar_setup_end-CFG_INT_FLASH_BASE), %a1
	153	move.l #(CFG_INIT_RAM_ADDR), %a2
	154	_copy_flash:
	155	move.l (%a0)+, (%a2)+
	156	cmp.l %a0, %a1
	157	bgt.s _copy_flash
	158	jmp CFG_INIT_RAM_ADDR
	159
	160	_flashbar_setup:
bf9e3b38 WD	161	/* Initialize FLASHBAR: locate internal Flash and validate it */
	162	move.l #(CFG_INT_FLASH_BASE + 0x21), %d0
	163	movec %d0, %RAMBAR0
9acb626f HS	164	jmp _after_flashbar_copy.L /* Force jump to absolute address */
	165	_flashbar_setup_end:
	166	nop
	167	_after_flashbar_copy:
	168	#else
	169	/* Setup code to initialize FLASHBAR, if start from external Memory */
	170	move.l #(CFG_INT_FLASH_BASE + 0x21), %d0
	171	movec %d0, %RAMBAR0
	172	#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
bf9e3b38	173
6741ae92	174	#endif
9acb626f HS	175	#endif
	176	/* if we come from a pre-loader we have no exception table and
	177	* therefore no VBR to set
	178	*/
	179	#if !defined(CONFIG_MONITOR_IS_IN_RAM)
	180	move.l #CFG_FLASH_BASE, %d0
	181	movec %d0, %VBR
6f5155a9 MB	182	#endif
	183
	184	#ifdef CONFIG_R5200
eacbd317 ZL	185	move.l #(_flash_setup-CFG_FLASH_BASE), %a0
	186	move.l #(_flash_setup_end-CFG_FLASH_BASE), %a1
	187	move.l #(CFG_INIT_RAM_ADDR), %a2
	188	_copy_flash:
	189	move.l (%a0)+, (%a2)+
	190	cmp.l %a0, %a1
	191	bgt.s _copy_flash
eacbd317 ZL	192	jmp CFG_INIT_RAM_ADDR
eacbd317 ZL	193	_after_flash_copy:
bf9e3b38 WD	194	#endif
bf9e3b38 WD	195
eacbd317	196	#if 0
bf9e3b38 WD	197	/* invalidate and disable cache */
	198	move.l #0x01000000, %d0 /* Invalidate cache cmd */
	199	movec %d0, %CACR /* Invalidate cache */
	200	move.l #0, %d0
	201	movec %d0, %ACR0
	202	movec %d0, %ACR1
eacbd317	203	#endif
bf9e3b38 WD	204
	205	/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
	206	move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
	207	clr.l %sp@-
	208
	209	move.l #__got_start, %a5 /* put relocation table address to a5 */
	210
	211	bsr cpu_init_f /* run low-level CPU init code (from flash) */
	212	bsr board_init_f /* run low-level board init code (from flash) */
	213
6f5155a9	214	/* board_init_f() does not return */
bf9e3b38 WD	215
	216	/------------------------------------------------------------------------------/
	217
6f5155a9	218	#ifdef CONFIG_R5200
eacbd317	219	_flash_setup:
6f5155a9 MB	220	/* CSAR0 */
6f5155a9 MB	221	move.l #((CFG_FLASH_BASE & 0xffff0000) >> 16), %d0
eacbd317	222	move.w %d0, 0x40000080
6f5155a9 MB	223
	224	/* CSCR0 */
	225	move.l #0x2180, %d0 /* 8 wait states, 16bit port, auto ack, */
eacbd317	226	move.w %d0, 0x4000008A
6f5155a9 MB	227
	228	/* CSMR0 */
	229	move.l #0x001f0001, %d0 /* 2 MB, valid */
eacbd317	230	move.l %d0, 0x40000084
6f5155a9	231
eacbd317 ZL	232	jmp _after_flash_copy.L
	233	_flash_setup_end:
	234	#endif
	235
bf9e3b38 WD	236	/*
	237	* void relocate_code (addr_sp, gd, addr_moni)
	238	*
	239	* This "function" does not return, instead it continues in RAM
	240	* after relocating the monitor code.
	241	*
	242	* r3 = dest
	243	* r4 = src
	244	* r5 = length in bytes
	245	* r6 = cachelinesize
	246	*/
	247	.globl relocate_code
	248	relocate_code:
	249	link.w %a6,#0
	250	move.l 8(%a6), %sp /* set new stack pointer */
	251
	252	move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
	253	move.l 16(%a6), %a0 /* Save copy of Destination Address */
	254
	255	move.l #CFG_MONITOR_BASE, %a1
	256	move.l #__init_end, %a2
	257	move.l %a0, %a3
bf9e3b38 WD	258	/* copy the code to RAM */
	259	1:
	260	move.l (%a1)+, (%a3)+
	261	cmp.l %a1,%a2
	262	bgt.s 1b
	263
	264	/*
	265	* We are done. Do not return, instead branch to second part of board
	266	* initialization, now running from RAM.
	267	*/
9acb626f	268	move.l %a0, %a1
bf9e3b38 WD	269	add.l #(in_ram - CFG_MONITOR_BASE), %a1
	270	jmp (%a1)
	271
	272	in_ram:
	273
	274	clear_bss:
9acb626f	275	/*
bf9e3b38 WD	276	* Now clear BSS segment
	277	*/
	278	move.l %a0, %a1
	279	add.l #(_sbss - CFG_MONITOR_BASE),%a1
	280	move.l %a0, %d1
	281	add.l #(_ebss - CFG_MONITOR_BASE),%d1
	282	6:
	283	clr.l (%a1)+
	284	cmp.l %a1,%d1
	285	bgt.s 6b
	286
	287	/*
	288	* fix got table in RAM
	289	*/
	290	move.l %a0, %a1
	291	add.l #(__got_start - CFG_MONITOR_BASE),%a1
	292	move.l %a1,%a5 /* * fix got pointer register a5 */
	293
	294	move.l %a0, %a2
	295	add.l #(__got_end - CFG_MONITOR_BASE),%a2
	296
	297	7:
	298	move.l (%a1),%d1
	299	sub.l #_start,%d1
	300	add.l %a0,%d1
	301	move.l %d1,(%a1)+
	302	cmp.l %a2, %a1
	303	bne 7b
	304
9acb626f HS	305	#if defined(CONFIG_M5281) \|\| defined(CONFIG_M5282)
	306	/* patch the 3 accesspoints to 3 ichache_state */
	307	/* quick and dirty */
	308
	309	move.l %a0,%d1
	310	add.l #(icache_state - CFG_MONITOR_BASE),%d1
	311	move.l %a0,%a1
	312	add.l #(icache_state_access_1+2 - CFG_MONITOR_BASE),%a1
	313	move.l %d1,(%a1)
	314	move.l %a0,%a1
	315	add.l #(icache_state_access_2+2 - CFG_MONITOR_BASE),%a1
	316	move.l %d1,(%a1)
	317	move.l %a0,%a1
	318	add.l #(icache_state_access_3+2 - CFG_MONITOR_BASE),%a1
	319	move.l %d1,(%a1)
	320	#endif
	321
bf9e3b38 WD	322	/* calculate relative jump to board_init_r in ram */
	323	move.l %a0, %a1
	324	add.l #(board_init_r - CFG_MONITOR_BASE), %a1
	325
	326	/* set parameters for board_init_r */
	327	move.l %a0,-(%sp) /* dest_addr */
	328	move.l %d0,-(%sp) /* gd */
9acb626f HS	329	#if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \
	330	defined(CFG_HALT_BEFOR_RAM_JUMP)
	331	halt
	332	#endif
bf9e3b38 WD	333	jsr (%a1)
	334
	335	/------------------------------------------------------------------------------/
	336	/* exception code */
	337	.globl _fault
	338	_fault:
	339	jmp _fault
	340
	341	.globl _exc_handler
	342	_exc_handler:
	343	SAVE_ALL
	344	movel %sp,%sp@-
	345	bsr exc_handler
	346	addql #4,%sp
	347	RESTORE_ALL
	348
	349	.globl _int_handler
	350	_int_handler:
	351	SAVE_ALL
	352	movel %sp,%sp@-
	353	bsr int_handler
	354	addql #4,%sp
	355	RESTORE_ALL
	356
	357	/------------------------------------------------------------------------------/
	358	/* cache functions */
	359	#ifdef CONFIG_M5272
	360	.globl icache_enable
	361	icache_enable:
	362	move.l #0x01000000, %d0 /* Invalidate cache cmd */
	363	movec %d0, %CACR /* Invalidate cache */
	364	move.l #0x0000c000, %d0 /* Setup cache mask */
	365	movec %d0, %ACR0 /* Enable cache */
	366	move.l #0xff00c000, %d0 /* Setup cache mask */
	367	movec %d0, %ACR1 /* Enable cache */
	368	move.l #0x80000100, %d0 /* Setup cache mask */
	369	movec %d0, %CACR /* Enable cache */
	370	moveq #1, %d0
	371	move.l %d0, icache_state
	372	rts
	373	#endif
	374
	375	#ifdef CONFIG_M5282
	376	.globl icache_enable
	377	icache_enable:
	378	move.l #0x01000000, %d0 /* Invalidate cache cmd */
	379	movec %d0, %CACR /* Invalidate cache */
	380	move.l #0x0000c000, %d0 /* Setup cache mask */
	381	movec %d0, %ACR0 /* Enable cache */
	382	move.l #0xff00c000, %d0 /* Setup cache mask */
	383	movec %d0, %ACR1 /* Enable cache */
	384	move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/
	385	movec %d0, %CACR /* Enable cache */
	386	moveq #1, %d0
9acb626f	387	icache_state_access_1:
bf9e3b38 WD	388	move.l %d0, icache_state
	389	rts
	390	#endif
	391
8c725b93 SR	392	#ifdef CONFIG_M5249
	393	.globl icache_enable
	394	icache_enable:
	395	/*
	396	* Note: The 5249 Documentation doesn't give a bit position for CINV!
	397	* From the 5272 and the 5307 documentation, I have deduced that it is
	398	* probably CACR[24]. Should someone say something to Motorola?
	399	* ~Jeremy
	400	*/
	401	move.l #0x01000000, %d0 /* Invalidate whole cache */
	402	move.c %d0,%CACR
	403	move.l #0xff00c000, %d0 /* Set FLASH cachable: always match (SM=0b10) */
	404	move.c %d0, %ACR0
	405	move.l #0x0000c000, %d0 /* Set SDRAM cachable: always match (SM=0b10) */
	406	move.c %d0, %ACR1
	407	move.l #0x90000200, %d0 /* Set cache enable cmd */
	408	move.c %d0,%CACR
	409	moveq #1, %d0
	410	move.l %d0, icache_state
	411	rts
	412	#endif
	413
bf9e3b38 WD	414	.globl icache_disable
	415	icache_disable:
	416	move.l #0x00000100, %d0 /* Setup cache mask */
	417	movec %d0, %CACR /* Enable cache */
	418	clr.l %d0 /* Setup cache mask */
	419	movec %d0, %ACR0 /* Enable cache */
	420	movec %d0, %ACR1 /* Enable cache */
	421	moveq #0, %d0
9acb626f	422	icache_state_access_2:
bf9e3b38 WD	423	move.l %d0, icache_state
	424	rts
	425
	426	.globl icache_status
	427	icache_status:
9acb626f	428	icache_state_access_3:
bf9e3b38 WD	429	move.l icache_state, %d0
	430	rts
	431
	432	.data
	433	icache_state:
9acb626f	434	.long 0 /* cache is diabled on inirialization */
8c725b93	435
bf9e3b38 WD	436	/------------------------------------------------------------------------------/
	437
	438	.globl version_string
	439	version_string:
	440	.ascii U_BOOT_VERSION
	441	.ascii " (", __DATE__, " - ", __TIME__, ")"
	442	.ascii CONFIG_IDENT_STRING, "\0"