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8ae158cd TL |
1 | /* |
2 | * | |
3 | * (C) Copyright 2000-2003 | |
4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
5 | * | |
6 | * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. | |
7 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #include <common.h> | |
29 | #include <watchdog.h> | |
30 | ||
31 | #include <asm/immap.h> | |
32 | #include <asm/rtc.h> | |
33 | ||
34 | /* | |
35 | * Breath some life into the CPU... | |
36 | * | |
37 | * Set up the memory map, | |
38 | * initialize a bunch of registers, | |
39 | * initialize the UPM's | |
40 | */ | |
41 | void cpu_init_f(void) | |
42 | { | |
43 | volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; | |
44 | volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; | |
45 | volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; | |
46 | ||
47 | scm1->mpr = 0x77777777; | |
48 | scm1->pacra = 0; | |
49 | scm1->pacrb = 0; | |
50 | scm1->pacrc = 0; | |
51 | scm1->pacrd = 0; | |
52 | scm1->pacre = 0; | |
53 | scm1->pacrf = 0; | |
54 | scm1->pacrg = 0; | |
55 | ||
56 | /* FlexBus */ | |
57 | gpio->par_be = | |
58 | GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 | | |
59 | GPIO_PAR_BE_BE0_BE0; | |
60 | gpio->par_fbctl = | |
61 | GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW | | |
62 | GPIO_PAR_FBCTL_TS_TS; | |
63 | ||
9f751551 | 64 | #if !defined(CONFIG_CF_SBF) |
6d0f6bcf JCPV |
65 | #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) |
66 | fbcs->csar0 = CONFIG_SYS_CS0_BASE; | |
67 | fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; | |
68 | fbcs->csmr0 = CONFIG_SYS_CS0_MASK; | |
8ae158cd | 69 | #endif |
9f751551 | 70 | #endif |
8ae158cd | 71 | |
6d0f6bcf | 72 | #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) |
8ae158cd | 73 | /* Latch chipselect */ |
6d0f6bcf JCPV |
74 | fbcs->csar1 = CONFIG_SYS_CS1_BASE; |
75 | fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; | |
76 | fbcs->csmr1 = CONFIG_SYS_CS1_MASK; | |
8ae158cd TL |
77 | #endif |
78 | ||
6d0f6bcf JCPV |
79 | #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) |
80 | fbcs->csar2 = CONFIG_SYS_CS2_BASE; | |
81 | fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; | |
82 | fbcs->csmr2 = CONFIG_SYS_CS2_MASK; | |
8ae158cd TL |
83 | #endif |
84 | ||
6d0f6bcf JCPV |
85 | #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) |
86 | fbcs->csar3 = CONFIG_SYS_CS3_BASE; | |
87 | fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; | |
88 | fbcs->csmr3 = CONFIG_SYS_CS3_MASK; | |
8ae158cd TL |
89 | #endif |
90 | ||
6d0f6bcf JCPV |
91 | #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) |
92 | fbcs->csar4 = CONFIG_SYS_CS4_BASE; | |
93 | fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; | |
94 | fbcs->csmr4 = CONFIG_SYS_CS4_MASK; | |
8ae158cd TL |
95 | #endif |
96 | ||
6d0f6bcf JCPV |
97 | #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) |
98 | fbcs->csar5 = CONFIG_SYS_CS5_BASE; | |
99 | fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; | |
100 | fbcs->csmr5 = CONFIG_SYS_CS5_MASK; | |
8ae158cd TL |
101 | #endif |
102 | ||
103 | #ifdef CONFIG_FSL_I2C | |
104 | gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA; | |
105 | #endif | |
106 | ||
107 | icache_enable(); | |
108 | } | |
109 | ||
110 | /* | |
111 | * initialize higher level parts of CPU like timers | |
112 | */ | |
113 | int cpu_init_r(void) | |
114 | { | |
bc3ccb13 | 115 | #ifdef CONFIG_MCFRTC |
6d0f6bcf | 116 | volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE); |
8ae158cd | 117 | volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended; |
8ae158cd | 118 | |
6d0f6bcf JCPV |
119 | rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF; |
120 | rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF; | |
8ae158cd TL |
121 | #endif |
122 | ||
123 | return (0); | |
124 | } | |
125 | ||
126 | void uart_port_conf(void) | |
127 | { | |
128 | volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; | |
129 | ||
130 | /* Setup Ports: */ | |
6d0f6bcf | 131 | switch (CONFIG_SYS_UART_PORT) { |
8ae158cd TL |
132 | case 0: |
133 | gpio->par_uart = | |
134 | (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); | |
135 | break; | |
136 | case 1: | |
137 | gpio->par_uart = | |
138 | (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); | |
139 | break; | |
140 | } | |
141 | } |