[people/ms/u-boot.git] / cpu / mcf5445x / pci.c

/*
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * PCI Configuration space access support
 */
#include <common.h>
#include <pci.h>
#include <asm/io.h>
#include <asm/immap.h>

#if defined(CONFIG_PCI)
/* System RAM mapped over PCI */
#define CONFIG_SYS_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)

#define cfg_read(val, addr, type, op)		*val = op((type)(addr));
#define cfg_write(val, addr, type, op)		op((type *)(addr), (val));

#define PCI_OP(rw, size, type, op, mask)				\
int pci_##rw##_cfg_##size(struct pci_controller *hose,			\
	pci_dev_t dev, int offset, type val)				\
{									\
	u32 addr = 0;							\
	u16 cfg_type = 0;						\
	addr = ((offset & 0xfc) | cfg_type | (dev)  | 0x80000000);	\
	out_be32(hose->cfg_addr, addr);					\
	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	\
	out_be32(hose->cfg_addr, addr & 0x7fffffff);			\
	return 0;							\
}

PCI_OP(read, byte, u8 *, in_8, 3)
PCI_OP(read, word, u16 *, in_le16, 2)
PCI_OP(read, dword, u32 *, in_le32, 0)
PCI_OP(write, byte, u8, out_8, 3)
PCI_OP(write, word, u16, out_le16, 2)
PCI_OP(write, dword, u32, out_le32, 0)

void pci_mcf5445x_init(struct pci_controller *hose)
{
	volatile pci_t *pci = (volatile pci_t *)MMAP_PCI;
	volatile pciarb_t *pciarb = (volatile pciarb_t *)MMAP_PCIARB;
	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
	u32 barEn = 0;

	pciarb->acr = 0x001F001F;

	/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
	   PCIREQ2, PCIGNT2 */
	gpio->par_pci =
	    GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | GPIO_PAR_PCI_GNT1 |
	    GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
	    GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0;

	/* Assert reset bit */
	pci->gscr |= PCI_GSCR_PR;

	pci->tcr1 |= PCI_TCR1_P;

	/* Initiator windows */
	pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16);
	pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16);
	pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16);

	pci->iwcr =
	    PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
	    PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;

	pci->icr = 0;

	/* Enable bus master and mem access */
	pci->scr = PCI_SCR_B | PCI_SCR_M;

	/* Cache line size and master latency */
	pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
	pci->cr2 = 0;

#ifdef CONFIG_SYS_PCI_BAR0
	pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0);
	pci->tbatr0 = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN;
	barEn |= PCI_TCR2_B0E;
#endif
#ifdef CONFIG_SYS_PCI_BAR1
	pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1);
	pci->tbatr1 = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN;
	barEn |= PCI_TCR2_B1E;
#endif
#ifdef CONFIG_SYS_PCI_BAR2
	pci->bar2 = PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2);
	pci->tbatr2 = CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN;
	barEn |= PCI_TCR2_B2E;
#endif
#ifdef CONFIG_SYS_PCI_BAR3
	pci->bar3 = PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3);
	pci->tbatr3 = CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN;
	barEn |= PCI_TCR2_B3E;
#endif
#ifdef CONFIG_SYS_PCI_BAR4
	pci->bar4 = PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4);
	pci->tbatr4 = CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN;
	barEn |= PCI_TCR2_B4E;
#endif
#ifdef CONFIG_SYS_PCI_BAR5
	pci->bar5 = PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5);
	pci->tbatr5 = CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN;
	barEn |= PCI_TCR2_B5E;
#endif

	pci->tcr2 = barEn;

	/* Deassert reset bit */
	pci->gscr &= ~PCI_GSCR_PR;
	udelay(1000);

	/* Enable PCI bus master support */
	hose->first_busno = 0;
	hose->last_busno = 0xff;

	pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
		       CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);

	pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
		       CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);

	pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
		       CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
		       PCI_REGION_MEM | PCI_REGION_MEMORY);

	hose->region_count = 3;

	hose->cfg_addr = &(pci->car);
	hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;

	pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
		    pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
		    pci_write_cfg_dword);

	/* Hose scan */
	pci_register_hose(hose);
	hose->last_busno = pci_hose_scan(hose);
}
#endif				/* CONFIG_PCI */
Commit	Line	Data
8ae158cd TL	1	/*
	2	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	3	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* PCI Configuration space access support
	26	*/
	27	#include <common.h>
	28	#include <pci.h>
	29	#include <asm/io.h>
	30	#include <asm/immap.h>
	31
	32	#if defined(CONFIG_PCI)
	33	/* System RAM mapped over PCI */
6d0f6bcf JCPV	34	#define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
	35	#define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
	36	#define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
8ae158cd TL	37
	38	#define cfg_read(val, addr, type, op) *val = op((type)(addr));
	39	#define cfg_write(val, addr, type, op) op((type *)(addr), (val));
	40
	41	#define PCI_OP(rw, size, type, op, mask) \
	42	int pci_##rw##_cfg_##size(struct pci_controller *hose, \
	43	pci_dev_t dev, int offset, type val) \
	44	{ \
	45	u32 addr = 0; \
	46	u16 cfg_type = 0; \
	47	addr = ((offset & 0xfc) \| cfg_type \| (dev) \| 0x80000000); \
	48	out_be32(hose->cfg_addr, addr); \
8ae158cd TL	49	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
8ae158cd TL	50	out_be32(hose->cfg_addr, addr & 0x7fffffff); \
8ae158cd TL	51	return 0; \
	52	}
	53
	54	PCI_OP(read, byte, u8 *, in_8, 3)
	55	PCI_OP(read, word, u16 *, in_le16, 2)
2e72ad06	56	PCI_OP(read, dword, u32 *, in_le32, 0)
8ae158cd TL	57	PCI_OP(write, byte, u8, out_8, 3)
	58	PCI_OP(write, word, u16, out_le16, 2)
	59	PCI_OP(write, dword, u32, out_le32, 0)
	60
8ae158cd TL	61	void pci_mcf5445x_init(struct pci_controller *hose)
	62	{
	63	volatile pci_t pci = (volatile pci_t )MMAP_PCI;
	64	volatile pciarb_t pciarb = (volatile pciarb_t )MMAP_PCIARB;
	65	volatile gpio_t gpio = (gpio_t ) MMAP_GPIO;
	66	u32 barEn = 0;
	67
2e72ad06	68	pciarb->acr = 0x001F001F;
8ae158cd TL	69
	70	/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
	71	PCIREQ2, PCIGNT2 */
	72	gpio->par_pci =
	73	GPIO_PAR_PCI_GNT3_GNT3 \| GPIO_PAR_PCI_GNT2 \| GPIO_PAR_PCI_GNT1 \|
	74	GPIO_PAR_PCI_GNT0 \| GPIO_PAR_PCI_REQ3_REQ3 \| GPIO_PAR_PCI_REQ2 \|
	75	GPIO_PAR_PCI_REQ1 \| GPIO_PAR_PCI_REQ0;
	76
2e72ad06 TL	77	/* Assert reset bit */
	78	pci->gscr \|= PCI_GSCR_PR;
	79
8ae158cd TL	80	pci->tcr1 \|= PCI_TCR1_P;
	81
	82	/* Initiator windows */
6d0f6bcf JCPV	83	pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS \| (CONFIG_SYS_PCI_MEM_PHYS >> 16);
	84	pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS \| (CONFIG_SYS_PCI_IO_PHYS >> 16);
	85	pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS \| (CONFIG_SYS_PCI_CFG_PHYS >> 16);
8ae158cd TL	86
	87	pci->iwcr =
	88	PCI_IWCR_W0C_EN \| PCI_IWCR_W1C_EN \| PCI_IWCR_W1C_IO \|
	89	PCI_IWCR_W2C_EN \| PCI_IWCR_W2C_IO;
	90
2e72ad06 TL	91	pci->icr = 0;
2e72ad06 TL	92
8ae158cd	93	/* Enable bus master and mem access */
2e72ad06	94	pci->scr = PCI_SCR_B \| PCI_SCR_M;
8ae158cd TL	95
8ae158cd TL	96	/* Cache line size and master latency */
2e72ad06	97	pci->cr1 = PCI_CR1_CLS(8) \| PCI_CR1_LTMR(0xF8);
8ae158cd TL	98	pci->cr2 = 0;
8ae158cd TL	99
6d0f6bcf JCPV	100	#ifdef CONFIG_SYS_PCI_BAR0
	101	pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0);
	102	pci->tbatr0 = CONFIG_SYS_PCI_TBATR0 \| PCI_TBATR_EN;
2e72ad06	103	barEn \|= PCI_TCR2_B0E;
8ae158cd	104	#endif
6d0f6bcf JCPV	105	#ifdef CONFIG_SYS_PCI_BAR1
	106	pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1);
	107	pci->tbatr1 = CONFIG_SYS_PCI_TBATR1 \| PCI_TBATR_EN;
2e72ad06	108	barEn \|= PCI_TCR2_B1E;
8ae158cd	109	#endif
6d0f6bcf JCPV	110	#ifdef CONFIG_SYS_PCI_BAR2
	111	pci->bar2 = PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2);
	112	pci->tbatr2 = CONFIG_SYS_PCI_TBATR2 \| PCI_TBATR_EN;
2e72ad06	113	barEn \|= PCI_TCR2_B2E;
8ae158cd	114	#endif
6d0f6bcf JCPV	115	#ifdef CONFIG_SYS_PCI_BAR3
	116	pci->bar3 = PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3);
	117	pci->tbatr3 = CONFIG_SYS_PCI_TBATR3 \| PCI_TBATR_EN;
2e72ad06	118	barEn \|= PCI_TCR2_B3E;
8ae158cd	119	#endif
6d0f6bcf JCPV	120	#ifdef CONFIG_SYS_PCI_BAR4
	121	pci->bar4 = PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4);
	122	pci->tbatr4 = CONFIG_SYS_PCI_TBATR4 \| PCI_TBATR_EN;
2e72ad06	123	barEn \|= PCI_TCR2_B4E;
8ae158cd	124	#endif
6d0f6bcf JCPV	125	#ifdef CONFIG_SYS_PCI_BAR5
	126	pci->bar5 = PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5);
	127	pci->tbatr5 = CONFIG_SYS_PCI_TBATR5 \| PCI_TBATR_EN;
2e72ad06	128	barEn \|= PCI_TCR2_B5E;
8ae158cd TL	129	#endif
	130
	131	pci->tcr2 = barEn;
	132
	133	/* Deassert reset bit */
	134	pci->gscr &= ~PCI_GSCR_PR;
	135	udelay(1000);
	136
	137	/* Enable PCI bus master support */
	138	hose->first_busno = 0;
	139	hose->last_busno = 0xff;
	140
6d0f6bcf JCPV	141	pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
6d0f6bcf JCPV	142	CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
8ae158cd	143
6d0f6bcf JCPV	144	pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
6d0f6bcf JCPV	145	CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
8ae158cd	146
6d0f6bcf JCPV	147	pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
6d0f6bcf JCPV	148	CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
8ae158cd TL	149	PCI_REGION_MEM \| PCI_REGION_MEMORY);
	150
	151	hose->region_count = 3;
	152
	153	hose->cfg_addr = &(pci->car);
6d0f6bcf	154	hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
8ae158cd TL	155
	156	pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
	157	pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
	158	pci_write_cfg_dword);
	159
	160	/* Hose scan */
	161	pci_register_hose(hose);
	162	hose->last_busno = pci_hose_scan(hose);
	163	}
	164	#endif /* CONFIG_PCI */