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570c0186 TL |
1 | /* |
2 | * | |
3 | * (C) Copyright 2000-2003 | |
4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
5 | * | |
6 | * (C) Copyright 2007 Freescale Semiconductor, Inc. | |
7 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #include <common.h> | |
29 | #include <MCD_dma.h> | |
30 | #include <asm/immap.h> | |
31 | ||
32 | /* | |
33 | * Breath some life into the CPU... | |
34 | * | |
35 | * Set up the memory map, | |
36 | * initialize a bunch of registers, | |
37 | * initialize the UPM's | |
38 | */ | |
39 | void cpu_init_f(void) | |
40 | { | |
41 | volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; | |
42 | volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; | |
43 | volatile xlbarb_t *xlbarb = (volatile xlbarb_t *) MMAP_XARB; | |
44 | ||
45 | xlbarb->adrto = 0x2000; | |
46 | xlbarb->datto = 0x2000; | |
47 | xlbarb->busto = 0x3000; | |
48 | ||
49 | xlbarb->cfg = XARB_SR_AT | XARB_SR_DT; | |
50 | ||
51 | /* Master Priority Enable */ | |
52 | xlbarb->pri = 0; | |
53 | xlbarb->prien = 0xff; | |
54 | ||
6d0f6bcf JCPV |
55 | #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) |
56 | fbcs->csar0 = CONFIG_SYS_CS0_BASE; | |
57 | fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; | |
58 | fbcs->csmr0 = CONFIG_SYS_CS0_MASK; | |
570c0186 TL |
59 | #endif |
60 | ||
6d0f6bcf JCPV |
61 | #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) |
62 | fbcs->csar1 = CONFIG_SYS_CS1_BASE; | |
63 | fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; | |
64 | fbcs->csmr1 = CONFIG_SYS_CS1_MASK; | |
570c0186 TL |
65 | #endif |
66 | ||
6d0f6bcf JCPV |
67 | #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) |
68 | fbcs->csar2 = CONFIG_SYS_CS2_BASE; | |
69 | fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; | |
70 | fbcs->csmr2 = CONFIG_SYS_CS2_MASK; | |
570c0186 TL |
71 | #endif |
72 | ||
6d0f6bcf JCPV |
73 | #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) |
74 | fbcs->csar3 = CONFIG_SYS_CS3_BASE; | |
75 | fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; | |
76 | fbcs->csmr3 = CONFIG_SYS_CS3_MASK; | |
570c0186 TL |
77 | #endif |
78 | ||
6d0f6bcf JCPV |
79 | #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) |
80 | fbcs->csar4 = CONFIG_SYS_CS4_BASE; | |
81 | fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; | |
82 | fbcs->csmr4 = CONFIG_SYS_CS4_MASK; | |
570c0186 TL |
83 | #endif |
84 | ||
6d0f6bcf JCPV |
85 | #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) |
86 | fbcs->csar5 = CONFIG_SYS_CS5_BASE; | |
87 | fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; | |
88 | fbcs->csmr5 = CONFIG_SYS_CS5_MASK; | |
570c0186 TL |
89 | #endif |
90 | ||
91 | #ifdef CONFIG_FSL_I2C | |
92 | gpio->par_feci2cirq = GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA; | |
93 | #endif | |
94 | ||
95 | icache_enable(); | |
96 | } | |
97 | ||
98 | /* | |
99 | * initialize higher level parts of CPU like timers | |
100 | */ | |
101 | int cpu_init_r(void) | |
102 | { | |
103 | #if defined(CONFIG_CMD_NET) && defined(CONFIG_FSLDMAFEC) | |
104 | MCD_initDma((dmaRegs *) (MMAP_MCDMA), (void *)(MMAP_SRAM + 512), | |
105 | MCD_RELOC_TASKS); | |
106 | #endif | |
107 | return (0); | |
108 | } | |
109 | ||
110 | void uart_port_conf(void) | |
111 | { | |
112 | volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; | |
6d0f6bcf | 113 | volatile u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40); |
570c0186 TL |
114 | |
115 | /* Setup Ports: */ | |
6d0f6bcf | 116 | switch (CONFIG_SYS_UART_PORT) { |
570c0186 TL |
117 | case 0: |
118 | gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0); | |
119 | break; | |
120 | case 1: | |
121 | gpio->par_psc1 = (GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1); | |
122 | break; | |
123 | case 2: | |
124 | gpio->par_psc2 = (GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2); | |
125 | break; | |
126 | case 3: | |
127 | gpio->par_psc3 = (GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3); | |
128 | break; | |
129 | } | |
130 | ||
131 | *pscsicr &= 0xF8; | |
132 | } |