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570c0186 TL |
1 | /* |
2 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
3 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * PCI Configuration space access support | |
26 | */ | |
27 | #include <common.h> | |
28 | #include <pci.h> | |
29 | #include <asm/io.h> | |
30 | #include <asm/immap.h> | |
31 | ||
32 | #if defined(CONFIG_PCI) | |
33 | /* System RAM mapped over PCI */ | |
6d0f6bcf JCPV |
34 | #define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE |
35 | #define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE | |
36 | #define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) | |
570c0186 TL |
37 | |
38 | #define cfg_read(val, addr, type, op) *val = op((type)(addr)); | |
39 | #define cfg_write(val, addr, type, op) op((type *)(addr), (val)); | |
40 | ||
41 | #define PCI_OP(rw, size, type, op, mask) \ | |
42 | int pci_##rw##_cfg_##size(struct pci_controller *hose, \ | |
43 | pci_dev_t dev, int offset, type val) \ | |
44 | { \ | |
45 | u32 addr = 0; \ | |
46 | u16 cfg_type = 0; \ | |
47 | addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \ | |
48 | out_be32(hose->cfg_addr, addr); \ | |
49 | cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ | |
50 | __asm__ __volatile__("nop"); \ | |
51 | __asm__ __volatile__("nop"); \ | |
52 | out_be32(hose->cfg_addr, addr & 0x7fffffff); \ | |
53 | return 0; \ | |
54 | } | |
55 | ||
56 | PCI_OP(read, byte, u8 *, in_8, 3) | |
57 | PCI_OP(read, word, u16 *, in_le16, 2) | |
58 | PCI_OP(write, byte, u8, out_8, 3) | |
59 | PCI_OP(write, word, u16, out_le16, 2) | |
60 | PCI_OP(write, dword, u32, out_le32, 0) | |
61 | ||
62 | int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev, | |
63 | int offset, u32 * val) | |
64 | { | |
65 | u32 addr; | |
66 | u32 tmpv; | |
67 | u32 mask = 2; /* word access */ | |
68 | /* Read lower 16 bits */ | |
69 | addr = ((offset & 0xfc) | (dev) | 0x80000000); | |
70 | out_be32(hose->cfg_addr, addr); | |
71 | *val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); | |
72 | __asm__ __volatile__("nop"); | |
73 | out_be32(hose->cfg_addr, addr & 0x7fffffff); | |
74 | ||
75 | /* Read upper 16 bits */ | |
76 | offset += 2; | |
77 | addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000); | |
78 | out_be32(hose->cfg_addr, addr); | |
79 | tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); | |
80 | __asm__ __volatile__("nop"); | |
81 | out_be32(hose->cfg_addr, addr & 0x7fffffff); | |
82 | ||
83 | /* combine results into dword value */ | |
84 | *val = (tmpv << 16) | *val; | |
85 | ||
86 | return 0; | |
87 | } | |
88 | ||
89 | void pci_mcf547x_8x_init(struct pci_controller *hose) | |
90 | { | |
91 | volatile pci_t *pci = (volatile pci_t *) MMAP_PCI; | |
92 | volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; | |
93 | ||
94 | /* Port configuration */ | |
95 | gpio->par_pcibg = | |
96 | GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) | | |
97 | GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) | | |
98 | GPIO_PAR_PCIBG_PCIBG4(3); | |
99 | gpio->par_pcibr = | |
100 | GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) | | |
101 | GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) | | |
102 | GPIO_PAR_PCIBR_PCIBR4(3); | |
103 | ||
104 | /* Assert reset bit */ | |
105 | pci->gscr |= PCI_GSCR_PR; | |
106 | ||
107 | pci->tcr1 = PCI_TCR1_P; | |
108 | ||
109 | /* Initiator windows */ | |
6d0f6bcf JCPV |
110 | pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16); |
111 | pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16); | |
112 | pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16); | |
570c0186 TL |
113 | |
114 | pci->iwcr = | |
115 | PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | | |
116 | PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO; | |
117 | ||
118 | pci->icr = 0; | |
119 | ||
120 | /* Enable bus master and mem access */ | |
121 | pci->scr = PCI_SCR_B | PCI_SCR_M; | |
122 | ||
123 | /* Cache line size and master latency */ | |
124 | pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8); | |
125 | pci->cr2 = 0; | |
126 | ||
6d0f6bcf JCPV |
127 | #ifdef CONFIG_SYS_PCI_BAR0 |
128 | pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0); | |
129 | pci->tbatr0a = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN; | |
570c0186 | 130 | #endif |
6d0f6bcf JCPV |
131 | #ifdef CONFIG_SYS_PCI_BAR1 |
132 | pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1); | |
133 | pci->tbatr1a = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN; | |
570c0186 TL |
134 | #endif |
135 | ||
136 | /* Deassert reset bit */ | |
137 | pci->gscr &= ~PCI_GSCR_PR; | |
138 | udelay(1000); | |
139 | ||
140 | /* Enable PCI bus master support */ | |
141 | hose->first_busno = 0; | |
142 | hose->last_busno = 0xff; | |
143 | ||
6d0f6bcf JCPV |
144 | pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS, |
145 | CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM); | |
570c0186 | 146 | |
6d0f6bcf JCPV |
147 | pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS, |
148 | CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); | |
570c0186 | 149 | |
6d0f6bcf JCPV |
150 | pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS, |
151 | CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE, | |
570c0186 TL |
152 | PCI_REGION_MEM | PCI_REGION_MEMORY); |
153 | ||
154 | hose->region_count = 3; | |
155 | ||
156 | hose->cfg_addr = &(pci->car); | |
6d0f6bcf | 157 | hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS; |
570c0186 TL |
158 | |
159 | pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word, | |
160 | pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word, | |
161 | pci_write_cfg_dword); | |
162 | ||
163 | /* Hose scan */ | |
164 | pci_register_hose(hose); | |
165 | hose->last_busno = pci_hose_scan(hose); | |
166 | } | |
167 | #endif /* CONFIG_PCI */ |