[people/ms/u-boot.git] / cpu / mips / au1x00_eth.c

/* Only eth0 supported for now
 *
 * (C) Copyright 2003
 * Thomas.Lange@corelatus.se
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <config.h>

#if defined(CONFIG_SYS_DISCOVER_PHY)
#error "PHY not supported yet"
/* We just assume that we are running 100FD for now */
/* We all use switches, right? ;-) */
#endif

/* I assume ethernet behaves like au1000 */

#ifdef CONFIG_SOC_AU1000
/* Base address differ between cpu:s */
#define ETH0_BASE AU1000_ETH0_BASE
#define MAC0_ENABLE AU1000_MAC0_ENABLE
#else
#ifdef CONFIG_SOC_AU1100
#define ETH0_BASE AU1100_ETH0_BASE
#define MAC0_ENABLE AU1100_MAC0_ENABLE
#else
#ifdef CONFIG_SOC_AU1500
#define ETH0_BASE AU1500_ETH0_BASE
#define MAC0_ENABLE AU1500_MAC0_ENABLE
#else
#ifdef CONFIG_SOC_AU1550
#define ETH0_BASE AU1550_ETH0_BASE
#define MAC0_ENABLE AU1550_MAC0_ENABLE
#else
#error "No valid cpu set"
#endif
#endif
#endif
#endif

#include <common.h>
#include <malloc.h>
#include <net.h>
#include <command.h>
#include <asm/io.h>
#include <asm/au1x00.h>

#if defined(CONFIG_CMD_MII)
#include <miiphy.h>
#endif

/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH  1520
#define PKT_MAXBUF_SIZE		1518

static char txbuf[DBUF_LENGTH];

static int next_tx;
static int next_rx;

/* 4 rx and 4 tx fifos */
#define NO_OF_FIFOS 4

typedef struct{
	u32 status;
	u32 addr;
	u32 len; /* Only used for tx */
	u32 not_used;
} mac_fifo_t;

mac_fifo_t mac_fifo[NO_OF_FIFOS];

#define MAX_WAIT 1000

#if defined(CONFIG_CMD_MII)
int  au1x00_miiphy_read(char *devname, unsigned char addr,
		unsigned char reg, unsigned short * value)
{
	volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
	volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
	u32 mii_control;
	unsigned int timedout = 20;

	while (*mii_control_reg & MAC_MII_BUSY) {
		udelay(1000);
		if (--timedout == 0) {
			printf("au1x00_eth: miiphy_read busy timeout!!\n");
			return -1;
		}
	}

	mii_control = MAC_SET_MII_SELECT_REG(reg) |
		MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;

	*mii_control_reg = mii_control;

	timedout = 20;
	while (*mii_control_reg & MAC_MII_BUSY) {
		udelay(1000);
		if (--timedout == 0) {
			printf("au1x00_eth: miiphy_read busy timeout!!\n");
			return -1;
		}
	}
	*value = *mii_data_reg;
	return 0;
}

int  au1x00_miiphy_write(char *devname, unsigned char addr,
		unsigned char reg, unsigned short value)
{
	volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
	volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
	u32 mii_control;
	unsigned int timedout = 20;

	while (*mii_control_reg & MAC_MII_BUSY) {
		udelay(1000);
		if (--timedout == 0) {
			printf("au1x00_eth: miiphy_write busy timeout!!\n");
			return -1;
		}
	}

	mii_control = MAC_SET_MII_SELECT_REG(reg) |
		MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;

	*mii_data_reg = value;
	*mii_control_reg = mii_control;
	return 0;
}
#endif

static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
	volatile mac_fifo_t *fifo_tx =
		(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
	int i;
	int res;

	/* tx fifo should always be idle */
	fifo_tx[next_tx].len = length;
	fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
	au_sync();

	udelay(1);
	i=0;
	while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
		if(i>MAX_WAIT){
			printf("TX timeout\n");
			break;
		}
		udelay(1);
		i++;
	}

	/* Clear done bit */
	fifo_tx[next_tx].addr = 0;
	fifo_tx[next_tx].len = 0;
	au_sync();

	res = fifo_tx[next_tx].status;

	next_tx++;
	if(next_tx>=NO_OF_FIFOS){
		next_tx=0;
	}
	return(res);
}

static int au1x00_recv(struct eth_device* dev){
	volatile mac_fifo_t *fifo_rx =
		(volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);

	int length;
	u32 status;

	for(;;){
		if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
			/* Nothing has been received */
			return(-1);
		}

		status = fifo_rx[next_rx].status;

		length = status&0x3FFF;

		if(status&RX_ERROR){
			printf("Rx error 0x%x\n", status);
		}
		else{
			/* Pass the packet up to the protocol layers. */
			NetReceive(NetRxPackets[next_rx], length - 4);
		}

		fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE;

		next_rx++;
		if(next_rx>=NO_OF_FIFOS){
			next_rx=0;
		}
	} /* for */

	return(0); /* Does anyone use this? */
}

static int au1x00_init(struct eth_device* dev, bd_t * bd){

	volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
	volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
	volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
	volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
	volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
	volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
	volatile mac_fifo_t *fifo_tx =
		(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
	volatile mac_fifo_t *fifo_rx =
		(volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
	int i;

	next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
	next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);

	/* We have to enable clocks before releasing reset */
	*macen = MAC_EN_CLOCK_ENABLE;
	udelay(10);

	/* Enable MAC0 */
	/* We have to release reset before accessing registers */
	*macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
		MAC_EN_RESET1|MAC_EN_RESET2;
	udelay(10);

	for(i=0;i<NO_OF_FIFOS;i++){
		fifo_tx[i].len = 0;
		fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
		fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))|RX_DMA_ENABLE;
	}

	/* Put mac addr in little endian */
#define ea eth_get_dev()->enetaddr
	*mac_addr_high	=	(ea[5] <<  8) | (ea[4]	    ) ;
	*mac_addr_low	=	(ea[3] << 24) | (ea[2] << 16) |
		(ea[1] <<  8) | (ea[0]	    ) ;
#undef ea
	*mac_mcast_low = 0;
	*mac_mcast_high = 0;

	/* Make sure the MAC buffer is in the correct endian mode */
#ifdef __LITTLE_ENDIAN
	*mac_ctrl = MAC_FULL_DUPLEX;
	udelay(1);
	*mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
#else
	*mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
	udelay(1);
	*mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
#endif

	return(1);
}

static void au1x00_halt(struct eth_device* dev){
}

int au1x00_enet_initialize(bd_t *bis){
	struct eth_device* dev;

	if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
		puts ("malloc failed\n");
		return 0;
	}

	memset(dev, 0, sizeof *dev);

	sprintf(dev->name, "Au1X00 ethernet");
	dev->iobase = 0;
	dev->priv   = 0;
	dev->init   = au1x00_init;
	dev->halt   = au1x00_halt;
	dev->send   = au1x00_send;
	dev->recv   = au1x00_recv;

	eth_register(dev);

#if defined(CONFIG_CMD_MII)
	miiphy_register(dev->name,
		au1x00_miiphy_read, au1x00_miiphy_write);
#endif

	return 1;
}
Commit	Line	Data
5da627a4 WD	1	/* Only eth0 supported for now
	2	*
	3	* (C) Copyright 2003
	4	* Thomas.Lange@corelatus.se
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
265817c7	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5da627a4 WD	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24	#include <config.h>
	25
6d0f6bcf	26	#if defined(CONFIG_SYS_DISCOVER_PHY)
265817c7	27	#error "PHY not supported yet"
5da627a4 WD	28	/* We just assume that we are running 100FD for now */
	29	/* We all use switches, right? ;-) */
	30	#endif
	31
a2663ea4 WD	32	/* I assume ethernet behaves like au1000 */
a2663ea4 WD	33
8bde63eb	34	#ifdef CONFIG_SOC_AU1000
5da627a4 WD	35	/* Base address differ between cpu:s */
	36	#define ETH0_BASE AU1000_ETH0_BASE
	37	#define MAC0_ENABLE AU1000_MAC0_ENABLE
	38	#else
8bde63eb	39	#ifdef CONFIG_SOC_AU1100
a2663ea4 WD	40	#define ETH0_BASE AU1100_ETH0_BASE
	41	#define MAC0_ENABLE AU1100_MAC0_ENABLE
	42	#else
8bde63eb	43	#ifdef CONFIG_SOC_AU1500
a2663ea4 WD	44	#define ETH0_BASE AU1500_ETH0_BASE
	45	#define MAC0_ENABLE AU1500_MAC0_ENABLE
	46	#else
8bde63eb	47	#ifdef CONFIG_SOC_AU1550
ff36fd85 WD	48	#define ETH0_BASE AU1550_ETH0_BASE
	49	#define MAC0_ENABLE AU1550_MAC0_ENABLE
	50	#else
a2663ea4 WD	51	#error "No valid cpu set"
	52	#endif
	53	#endif
5da627a4	54	#endif
ff36fd85	55	#endif
5da627a4 WD	56
	57	#include <common.h>
	58	#include <malloc.h>
	59	#include <net.h>
	60	#include <command.h>
	61	#include <asm/io.h>
	62	#include <asm/au1x00.h>
	63
4431283c	64	#if defined(CONFIG_CMD_MII)
63ff004c MB	65	#include <miiphy.h>
	66	#endif
	67
5da627a4 WD	68	/* Ethernet Transmit and Receive Buffers */
	69	#define DBUF_LENGTH 1520
	70	#define PKT_MAXBUF_SIZE 1518
	71
	72	static char txbuf[DBUF_LENGTH];
	73
	74	static int next_tx;
	75	static int next_rx;
	76
	77	/* 4 rx and 4 tx fifos */
	78	#define NO_OF_FIFOS 4
	79
	80	typedef struct{
	81	u32 status;
	82	u32 addr;
	83	u32 len; /* Only used for tx */
	84	u32 not_used;
	85	} mac_fifo_t;
	86
	87	mac_fifo_t mac_fifo[NO_OF_FIFOS];
	88
	89	#define MAX_WAIT 1000
	90
f0132045 SK	91	#if defined(CONFIG_CMD_MII)
	92	int au1x00_miiphy_read(char *devname, unsigned char addr,
	93	unsigned char reg, unsigned short * value)
	94	{
	95	volatile u32 mii_control_reg = (volatile u32)(ETH0_BASE+MAC_MII_CNTRL);
	96	volatile u32 mii_data_reg = (volatile u32)(ETH0_BASE+MAC_MII_DATA);
	97	u32 mii_control;
	98	unsigned int timedout = 20;
	99
	100	while (*mii_control_reg & MAC_MII_BUSY) {
	101	udelay(1000);
	102	if (--timedout == 0) {
	103	printf("au1x00_eth: miiphy_read busy timeout!!\n");
	104	return -1;
	105	}
	106	}
	107
	108	mii_control = MAC_SET_MII_SELECT_REG(reg) \|
	109	MAC_SET_MII_SELECT_PHY(addr) \| MAC_MII_READ;
	110
	111	*mii_control_reg = mii_control;
	112
	113	timedout = 20;
	114	while (*mii_control_reg & MAC_MII_BUSY) {
	115	udelay(1000);
	116	if (--timedout == 0) {
	117	printf("au1x00_eth: miiphy_read busy timeout!!\n");
	118	return -1;
	119	}
	120	}
	121	value = mii_data_reg;
	122	return 0;
	123	}
	124
	125	int au1x00_miiphy_write(char *devname, unsigned char addr,
	126	unsigned char reg, unsigned short value)
	127	{
	128	volatile u32 mii_control_reg = (volatile u32)(ETH0_BASE+MAC_MII_CNTRL);
	129	volatile u32 mii_data_reg = (volatile u32)(ETH0_BASE+MAC_MII_DATA);
	130	u32 mii_control;
	131	unsigned int timedout = 20;
	132
	133	while (*mii_control_reg & MAC_MII_BUSY) {
	134	udelay(1000);
	135	if (--timedout == 0) {
	136	printf("au1x00_eth: miiphy_write busy timeout!!\n");
4fbd0741	137	return -1;
f0132045 SK	138	}
	139	}
	140
	141	mii_control = MAC_SET_MII_SELECT_REG(reg) \|
	142	MAC_SET_MII_SELECT_PHY(addr) \| MAC_MII_WRITE;
	143
	144	*mii_data_reg = value;
	145	*mii_control_reg = mii_control;
	146	return 0;
	147	}
	148	#endif
	149
5da627a4 WD	150	static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
	151	volatile mac_fifo_t *fifo_tx =
	152	(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
	153	int i;
	154	int res;
	155
	156	/* tx fifo should always be idle */
	157	fifo_tx[next_tx].len = length;
	158	fifo_tx[next_tx].addr = (virt_to_phys(packet))\|TX_DMA_ENABLE;
	159	au_sync();
	160
	161	udelay(1);
	162	i=0;
	163	while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
	164	if(i>MAX_WAIT){
	165	printf("TX timeout\n");
	166	break;
	167	}
	168	udelay(1);
	169	i++;
	170	}
	171
	172	/* Clear done bit */
	173	fifo_tx[next_tx].addr = 0;
	174	fifo_tx[next_tx].len = 0;
	175	au_sync();
	176
	177	res = fifo_tx[next_tx].status;
	178
	179	next_tx++;
	180	if(next_tx>=NO_OF_FIFOS){
	181	next_tx=0;
	182	}
	183	return(res);
	184	}
	185
	186	static int au1x00_recv(struct eth_device* dev){
	187	volatile mac_fifo_t *fifo_rx =
	188	(volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
	189
	190	int length;
	191	u32 status;
	192
	193	for(;;){
	194	if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
	195	/* Nothing has been received */
	196	return(-1);
	197	}
	198
	199	status = fifo_rx[next_rx].status;
	200
	201	length = status&0x3FFF;
	202
	203	if(status&RX_ERROR){
	204	printf("Rx error 0x%x\n", status);
	205	}
	206	else{
	207	/* Pass the packet up to the protocol layers. */
	208	NetReceive(NetRxPackets[next_rx], length - 4);
	209	}
	210
	211	fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))\|RX_DMA_ENABLE;
	212
	213	next_rx++;
214	if(next_rx>=NO_OF_FIFOS){
215	next_rx=0;
216	}
217	} /* for */
218
219	return(0); /* Does anyone use this? */
220	}
221
222	static int au1x00_init(struct eth_device* dev, bd_t * bd){
223
224	volatile u32 macen = (volatile u32)MAC0_ENABLE;
225	volatile u32 mac_ctrl = (volatile u32)(ETH0_BASE+MAC_CONTROL);
226	volatile u32 mac_addr_high = (volatile u32)(ETH0_BASE+MAC_ADDRESS_HIGH);
227	volatile u32 mac_addr_low = (volatile u32)(ETH0_BASE+MAC_ADDRESS_LOW);
228	volatile u32 mac_mcast_high = (volatile u32)(ETH0_BASE+MAC_MCAST_HIGH);
229	volatile u32 mac_mcast_low = (volatile u32)(ETH0_BASE+MAC_MCAST_LOW);
230	volatile mac_fifo_t *fifo_tx =
231	(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
232	volatile mac_fifo_t *fifo_rx =
233	(volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
234	int i;
235
4bc12f1c WD	236	next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
4bc12f1c WD	237	next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);
5da627a4 WD	238
	239	/* We have to enable clocks before releasing reset */
	240	*macen = MAC_EN_CLOCK_ENABLE;
	241	udelay(10);
	242
	243	/* Enable MAC0 */
	244	/* We have to release reset before accessing registers */
	245	*macen = MAC_EN_CLOCK_ENABLE\|MAC_EN_RESET0\|
	246	MAC_EN_RESET1\|MAC_EN_RESET2;
	247	udelay(10);
	248
	249	for(i=0;i<NO_OF_FIFOS;i++){
	250	fifo_tx[i].len = 0;
	251	fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
	252	fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))\|RX_DMA_ENABLE;
	253	}
	254
	255	/* Put mac addr in little endian */
	256	#define ea eth_get_dev()->enetaddr
265817c7 WD	257	*mac_addr_high = (ea[5] << 8) \| (ea[4] ) ;
	258	*mac_addr_low = (ea[3] << 24) \| (ea[2] << 16) \|
	259	(ea[1] << 8) \| (ea[0] ) ;
5da627a4	260	#undef ea
5da627a4 WD	261	*mac_mcast_low = 0;
	262	*mac_mcast_high = 0;
	263
63f34912 WD	264	/* Make sure the MAC buffer is in the correct endian mode */
	265	#ifdef __LITTLE_ENDIAN
	266	*mac_ctrl = MAC_FULL_DUPLEX;
	267	udelay(1);
	268	*mac_ctrl = MAC_FULL_DUPLEX\|MAC_RX_ENABLE\|MAC_TX_ENABLE;
	269	#else
5da627a4 WD	270	*mac_ctrl = MAC_BIG_ENDIAN\|MAC_FULL_DUPLEX;
	271	udelay(1);
	272	*mac_ctrl = MAC_BIG_ENDIAN\|MAC_FULL_DUPLEX\|MAC_RX_ENABLE\|MAC_TX_ENABLE;
63f34912	273	#endif
5da627a4 WD	274
	275	return(1);
	276	}
	277
	278	static void au1x00_halt(struct eth_device* dev){
	279	}
	280
	281	int au1x00_enet_initialize(bd_t *bis){
	282	struct eth_device* dev;
	283
95515306 WD	284	if ((dev = (struct eth_device)malloc(sizeof dev)) == NULL) {
	285	puts ("malloc failed\n");
	286	return 0;
	287	}
	288
5da627a4 WD	289	memset(dev, 0, sizeof *dev);
5da627a4 WD	290
95515306	291	sprintf(dev->name, "Au1X00 ethernet");
5da627a4 WD	292	dev->iobase = 0;
	293	dev->priv = 0;
	294	dev->init = au1x00_init;
	295	dev->halt = au1x00_halt;
	296	dev->send = au1x00_send;
	297	dev->recv = au1x00_recv;
	298
	299	eth_register(dev);
	300
4431283c	301	#if defined(CONFIG_CMD_MII)
63ff004c MB	302	miiphy_register(dev->name,
	303	au1x00_miiphy_read, au1x00_miiphy_write);
	304	#endif
	305
5da627a4 WD	306	return 1;
5da627a4 WD	307	}