[people/ms/u-boot.git] / cpu / mips / start.S

/*
 *  Startup Code for MIPS32 CPU-core
 *
 *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>

	/*
	 * For the moment disable interrupts, mark the kernel mode and
	 * set ST0_KX so that the CPU does not spit fire when using
	 * 64-bit addresses.
	 */
	.macro	setup_c0_status set clr
	.set	push
	mfc0	t0, CP0_STATUS
	or	t0, ST0_CU0 | \set | 0x1f | \clr
	xor	t0, 0x1f | \clr
	mtc0	t0, CP0_STATUS
	.set	noreorder
	sll	zero, 3				# ehb
	.set	pop
	.endm

	.macro	setup_c0_status_reset
#ifdef CONFIG_64BIT
	setup_c0_status ST0_KX 0
#else
	setup_c0_status 0 0
#endif
	.endm

#define RVECENT(f,n) \
   b f; nop
#define XVECENT(f,bev) \
   b f     ;           \
   li k0,bev

	.set noreorder

	.globl _start
	.text
_start:
	RVECENT(reset,0)	/* U-boot entry point */
	RVECENT(reset,1)	/* software reboot */
#if defined(CONFIG_INCA_IP)
	.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
	.word 0x00000000           /* phase of the flash                    */
#elif defined(CONFIG_PURPLE)
	.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
	.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
#else
	RVECENT(romReserved,2)
#endif
	RVECENT(romReserved,3)
	RVECENT(romReserved,4)
	RVECENT(romReserved,5)
	RVECENT(romReserved,6)
	RVECENT(romReserved,7)
	RVECENT(romReserved,8)
	RVECENT(romReserved,9)
	RVECENT(romReserved,10)
	RVECENT(romReserved,11)
	RVECENT(romReserved,12)
	RVECENT(romReserved,13)
	RVECENT(romReserved,14)
	RVECENT(romReserved,15)
	RVECENT(romReserved,16)
	RVECENT(romReserved,17)
	RVECENT(romReserved,18)
	RVECENT(romReserved,19)
	RVECENT(romReserved,20)
	RVECENT(romReserved,21)
	RVECENT(romReserved,22)
	RVECENT(romReserved,23)
	RVECENT(romReserved,24)
	RVECENT(romReserved,25)
	RVECENT(romReserved,26)
	RVECENT(romReserved,27)
	RVECENT(romReserved,28)
	RVECENT(romReserved,29)
	RVECENT(romReserved,30)
	RVECENT(romReserved,31)
	RVECENT(romReserved,32)
	RVECENT(romReserved,33)
	RVECENT(romReserved,34)
	RVECENT(romReserved,35)
	RVECENT(romReserved,36)
	RVECENT(romReserved,37)
	RVECENT(romReserved,38)
	RVECENT(romReserved,39)
	RVECENT(romReserved,40)
	RVECENT(romReserved,41)
	RVECENT(romReserved,42)
	RVECENT(romReserved,43)
	RVECENT(romReserved,44)
	RVECENT(romReserved,45)
	RVECENT(romReserved,46)
	RVECENT(romReserved,47)
	RVECENT(romReserved,48)
	RVECENT(romReserved,49)
	RVECENT(romReserved,50)
	RVECENT(romReserved,51)
	RVECENT(romReserved,52)
	RVECENT(romReserved,53)
	RVECENT(romReserved,54)
	RVECENT(romReserved,55)
	RVECENT(romReserved,56)
	RVECENT(romReserved,57)
	RVECENT(romReserved,58)
	RVECENT(romReserved,59)
	RVECENT(romReserved,60)
	RVECENT(romReserved,61)
	RVECENT(romReserved,62)
	RVECENT(romReserved,63)
	XVECENT(romExcHandle,0x200)	/* bfc00200: R4000 tlbmiss vector */
	RVECENT(romReserved,65)
	RVECENT(romReserved,66)
	RVECENT(romReserved,67)
	RVECENT(romReserved,68)
	RVECENT(romReserved,69)
	RVECENT(romReserved,70)
	RVECENT(romReserved,71)
	RVECENT(romReserved,72)
	RVECENT(romReserved,73)
	RVECENT(romReserved,74)
	RVECENT(romReserved,75)
	RVECENT(romReserved,76)
	RVECENT(romReserved,77)
	RVECENT(romReserved,78)
	RVECENT(romReserved,79)
	XVECENT(romExcHandle,0x280)	/* bfc00280: R4000 xtlbmiss vector */
	RVECENT(romReserved,81)
	RVECENT(romReserved,82)
	RVECENT(romReserved,83)
	RVECENT(romReserved,84)
	RVECENT(romReserved,85)
	RVECENT(romReserved,86)
	RVECENT(romReserved,87)
	RVECENT(romReserved,88)
	RVECENT(romReserved,89)
	RVECENT(romReserved,90)
	RVECENT(romReserved,91)
	RVECENT(romReserved,92)
	RVECENT(romReserved,93)
	RVECENT(romReserved,94)
	RVECENT(romReserved,95)
	XVECENT(romExcHandle,0x300)	/* bfc00300: R4000 cache vector */
	RVECENT(romReserved,97)
	RVECENT(romReserved,98)
	RVECENT(romReserved,99)
	RVECENT(romReserved,100)
	RVECENT(romReserved,101)
	RVECENT(romReserved,102)
	RVECENT(romReserved,103)
	RVECENT(romReserved,104)
	RVECENT(romReserved,105)
	RVECENT(romReserved,106)
	RVECENT(romReserved,107)
	RVECENT(romReserved,108)
	RVECENT(romReserved,109)
	RVECENT(romReserved,110)
	RVECENT(romReserved,111)
	XVECENT(romExcHandle,0x380)	/* bfc00380: R4000 general vector */
	RVECENT(romReserved,113)
	RVECENT(romReserved,114)
	RVECENT(romReserved,115)
	RVECENT(romReserved,116)
	RVECENT(romReserved,116)
	RVECENT(romReserved,118)
	RVECENT(romReserved,119)
	RVECENT(romReserved,120)
	RVECENT(romReserved,121)
	RVECENT(romReserved,122)
	RVECENT(romReserved,123)
	RVECENT(romReserved,124)
	RVECENT(romReserved,125)
	RVECENT(romReserved,126)
	RVECENT(romReserved,127)

	/* We hope there are no more reserved vectors!
	 * 128 * 8 == 1024 == 0x400
	 * so this is address R_VEC+0x400 == 0xbfc00400
	 */
#ifdef CONFIG_PURPLE
/* 0xbfc00400 */
	.word	0xdc870000
	.word	0xfca70000
	.word	0x20840008
	.word	0x20a50008
	.word	0x20c6ffff
	.word	0x14c0fffa
	.word	0x00000000
	.word	0x03e00008
	.word	0x00000000
	.word	0x00000000
/* 0xbfc00428 */
	.word	0xdc870000
	.word	0xfca70000
	.word	0x20840008
	.word	0x20a50008
	.word	0x20c6ffff
	.word	0x14c0fffa
	.word	0x00000000
	.word	0x03e00008
	.word	0x00000000
	.word	0x00000000
#endif /* CONFIG_PURPLE */
	.align 4
reset:

	/* Clear watch registers.
	 */
	mtc0	zero, CP0_WATCHLO
	mtc0	zero, CP0_WATCHHI

	/* WP(Watch Pending), SW0/1 should be cleared. */
	mtc0	zero, CP0_CAUSE

	setup_c0_status_reset

	/* Init Timer */
	mtc0	zero, CP0_COUNT
	mtc0	zero, CP0_COMPARE

	/* CONFIG0 register */
	li	t0, CONF_CM_UNCACHED
	mtc0	t0, CP0_CONFIG

	/* Initialize $gp.
	 */
	bal	1f
	nop
	.word	_gp
1:
	lw	gp, 0(ra)

	/* Initialize any external memory.
	 */
	la	t9, lowlevel_init
	jalr	t9
	nop

	/* Initialize caches...
	 */
	la	t9, mips_cache_reset
	jalr	t9
	nop

	/* ... and enable them.
	 */
	li	t0, CONF_CM_CACHABLE_NONCOHERENT
	mtc0	t0, CP0_CONFIG

	/* Set up temporary stack.
	 */
#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
	li	a0, CONFIG_SYS_INIT_SP_OFFSET
	la	t9, mips_cache_lock
	jalr	t9
	nop
#endif

	li	t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
	la	sp, 0(t0)

	la	t9, board_init_f
	jr	t9
	nop

/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 * a0 = addr_sp
 * a1 = gd
 * a2 = destination address
 */
	.globl	relocate_code
	.ent	relocate_code
relocate_code:
	move	sp, a0		/* Set new stack pointer	*/

	li	t0, CONFIG_SYS_MONITOR_BASE
	la	t3, in_ram
	lw	t2, -12(t3)	/* t2 <-- uboot_end_data	*/
	move	t1, a2

	/*
	 * Fix $gp:
	 *
	 * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
	 */
	move	t6, gp
	sub	gp, CONFIG_SYS_MONITOR_BASE
	add	gp, a2		/* gp now adjusted		*/
	sub	t6, gp, t6	/* t6 <-- relocation offset	*/

	/*
	 * t0 = source address
	 * t1 = target address
	 * t2 = source end address
	 */
	/* On the purple board we copy the code earlier in a special way
	 * in order to solve flash problems
	 */
#ifndef CONFIG_PURPLE
1:
	lw	t3, 0(t0)
	sw	t3, 0(t1)
	addu	t0, 4
	ble	t0, t2, 1b
	addu	t1, 4		/* delay slot			*/
#endif

	/* If caches were enabled, we would have to flush them here.
	 */

	/* Jump to where we've relocated ourselves.
	 */
	addi	t0, a2, in_ram - _start
	jr	t0
	nop

	.word	_gp
	.word	_GLOBAL_OFFSET_TABLE_
	.word	uboot_end_data
	.word	uboot_end
	.word	num_got_entries

in_ram:
	/*
	 * Now we want to update GOT.
	 *
	 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
	 * generated by GNU ld. Skip these reserved entries from relocation.
	 */
	lw	t3, -4(t0)	/* t3 <-- num_got_entries	*/
	lw	t4, -16(t0)	/* t4 <-- _GLOBAL_OFFSET_TABLE_	*/
	lw	t5, -20(t0)	/* t5 <-- _gp	*/
	sub	t4, t5		/* compute offset*/
	add	t4, t4, gp	/* t4 now holds relocated _GLOBAL_OFFSET_TABLE_	*/
	addi	t4, t4, 8	/* Skipping first two entries.	*/
	li	t2, 2
1:
	lw	t1, 0(t4)
	beqz	t1, 2f
	add	t1, t6
	sw	t1, 0(t4)
2:
	addi	t2, 1
	blt	t2, t3, 1b
	addi	t4, 4		/* delay slot			*/

	/* Clear BSS.
	 */
	lw	t1, -12(t0)	/* t1 <-- uboot_end_data	*/
	lw	t2, -8(t0)	/* t2 <-- uboot_end		*/
	add	t1, t6		/* adjust pointers		*/
	add	t2, t6

	sub	t1, 4
1:
	addi	t1, 4
	bltl	t1, t2, 1b
	sw	zero, 0(t1)	/* delay slot			*/

	move	a0, a1
	la	t9, board_init_r
	jr	t9
	move	a1, a2		/* delay slot			*/

	.end	relocate_code

	/* Exception handlers.
	 */
romReserved:
	b	romReserved

romExcHandle:
	b	romExcHandle
Commit	Line	Data
c021880a WD	1	/*
	2	* Startup Code for MIPS32 CPU-core
	3	*
	4	* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
c021880a	25	#include <config.h>
c021880a WD	26	#include <asm/regdef.h>
	27	#include <asm/mipsregs.h>
	28
decaba6f SK	29	/*
	30	* For the moment disable interrupts, mark the kernel mode and
	31	* set ST0_KX so that the CPU does not spit fire when using
	32	* 64-bit addresses.
	33	*/
	34	.macro setup_c0_status set clr
	35	.set push
	36	mfc0 t0, CP0_STATUS
	37	or t0, ST0_CU0 \| \set \| 0x1f \| \clr
	38	xor t0, 0x1f \| \clr
	39	mtc0 t0, CP0_STATUS
	40	.set noreorder
	41	sll zero, 3 # ehb
	42	.set pop
	43	.endm
	44
	45	.macro setup_c0_status_reset
	46	#ifdef CONFIG_64BIT
	47	setup_c0_status ST0_KX 0
	48	#else
	49	setup_c0_status 0 0
	50	#endif
	51	.endm
	52
c021880a WD	53	#define RVECENT(f,n) \
	54	b f; nop
	55	#define XVECENT(f,bev) \
	56	b f ; \
	57	li k0,bev
	58
	59	.set noreorder
	60
	61	.globl _start
	62	.text
	63	_start:
	64	RVECENT(reset,0) /* U-boot entry point */
	65	RVECENT(reset,1) /* software reboot */
3e38691e WD	66	#if defined(CONFIG_INCA_IP)
	67	.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
	68	.word 0x00000000 /* phase of the flash */
	69	#elif defined(CONFIG_PURPLE)
	70	.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
	71	.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
c021880a WD	72	#else
	73	RVECENT(romReserved,2)
	74	#endif
	75	RVECENT(romReserved,3)
	76	RVECENT(romReserved,4)
	77	RVECENT(romReserved,5)
	78	RVECENT(romReserved,6)
	79	RVECENT(romReserved,7)
	80	RVECENT(romReserved,8)
	81	RVECENT(romReserved,9)
	82	RVECENT(romReserved,10)
	83	RVECENT(romReserved,11)
	84	RVECENT(romReserved,12)
	85	RVECENT(romReserved,13)
	86	RVECENT(romReserved,14)
	87	RVECENT(romReserved,15)
	88	RVECENT(romReserved,16)
8bde7f77	89	RVECENT(romReserved,17)
c021880a WD	90	RVECENT(romReserved,18)
	91	RVECENT(romReserved,19)
	92	RVECENT(romReserved,20)
	93	RVECENT(romReserved,21)
	94	RVECENT(romReserved,22)
	95	RVECENT(romReserved,23)
	96	RVECENT(romReserved,24)
	97	RVECENT(romReserved,25)
	98	RVECENT(romReserved,26)
	99	RVECENT(romReserved,27)
	100	RVECENT(romReserved,28)
	101	RVECENT(romReserved,29)
	102	RVECENT(romReserved,30)
	103	RVECENT(romReserved,31)
	104	RVECENT(romReserved,32)
	105	RVECENT(romReserved,33)
	106	RVECENT(romReserved,34)
	107	RVECENT(romReserved,35)
	108	RVECENT(romReserved,36)
	109	RVECENT(romReserved,37)
	110	RVECENT(romReserved,38)
	111	RVECENT(romReserved,39)
	112	RVECENT(romReserved,40)
	113	RVECENT(romReserved,41)
	114	RVECENT(romReserved,42)
	115	RVECENT(romReserved,43)
	116	RVECENT(romReserved,44)
	117	RVECENT(romReserved,45)
	118	RVECENT(romReserved,46)
	119	RVECENT(romReserved,47)
	120	RVECENT(romReserved,48)
	121	RVECENT(romReserved,49)
	122	RVECENT(romReserved,50)
	123	RVECENT(romReserved,51)
	124	RVECENT(romReserved,52)
	125	RVECENT(romReserved,53)
	126	RVECENT(romReserved,54)
	127	RVECENT(romReserved,55)
	128	RVECENT(romReserved,56)
	129	RVECENT(romReserved,57)
	130	RVECENT(romReserved,58)
	131	RVECENT(romReserved,59)
	132	RVECENT(romReserved,60)
	133	RVECENT(romReserved,61)
	134	RVECENT(romReserved,62)
8bde7f77	135	RVECENT(romReserved,63)
c021880a WD	136	XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */
	137	RVECENT(romReserved,65)
	138	RVECENT(romReserved,66)
	139	RVECENT(romReserved,67)
	140	RVECENT(romReserved,68)
	141	RVECENT(romReserved,69)
	142	RVECENT(romReserved,70)
	143	RVECENT(romReserved,71)
	144	RVECENT(romReserved,72)
	145	RVECENT(romReserved,73)
	146	RVECENT(romReserved,74)
	147	RVECENT(romReserved,75)
	148	RVECENT(romReserved,76)
	149	RVECENT(romReserved,77)
	150	RVECENT(romReserved,78)
8bde7f77	151	RVECENT(romReserved,79)
c021880a WD	152	XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */
	153	RVECENT(romReserved,81)
	154	RVECENT(romReserved,82)
	155	RVECENT(romReserved,83)
	156	RVECENT(romReserved,84)
	157	RVECENT(romReserved,85)
	158	RVECENT(romReserved,86)
	159	RVECENT(romReserved,87)
	160	RVECENT(romReserved,88)
	161	RVECENT(romReserved,89)
	162	RVECENT(romReserved,90)
	163	RVECENT(romReserved,91)
	164	RVECENT(romReserved,92)
	165	RVECENT(romReserved,93)
	166	RVECENT(romReserved,94)
8bde7f77	167	RVECENT(romReserved,95)
c021880a WD	168	XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */
	169	RVECENT(romReserved,97)
	170	RVECENT(romReserved,98)
	171	RVECENT(romReserved,99)
	172	RVECENT(romReserved,100)
	173	RVECENT(romReserved,101)
	174	RVECENT(romReserved,102)
	175	RVECENT(romReserved,103)
	176	RVECENT(romReserved,104)
	177	RVECENT(romReserved,105)
	178	RVECENT(romReserved,106)
	179	RVECENT(romReserved,107)
	180	RVECENT(romReserved,108)
	181	RVECENT(romReserved,109)
	182	RVECENT(romReserved,110)
	183	RVECENT(romReserved,111)
	184	XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */
	185	RVECENT(romReserved,113)
	186	RVECENT(romReserved,114)
	187	RVECENT(romReserved,115)
	188	RVECENT(romReserved,116)
	189	RVECENT(romReserved,116)
	190	RVECENT(romReserved,118)
	191	RVECENT(romReserved,119)
	192	RVECENT(romReserved,120)
	193	RVECENT(romReserved,121)
	194	RVECENT(romReserved,122)
	195	RVECENT(romReserved,123)
	196	RVECENT(romReserved,124)
	197	RVECENT(romReserved,125)
	198	RVECENT(romReserved,126)
	199	RVECENT(romReserved,127)
8bde7f77	200
c021880a WD	201	/* We hope there are no more reserved vectors!
	202	* 128 * 8 == 1024 == 0x400
	203	* so this is address R_VEC+0x400 == 0xbfc00400
	204	*/
3e38691e WD	205	#ifdef CONFIG_PURPLE
	206	/* 0xbfc00400 */
	207	.word 0xdc870000
	208	.word 0xfca70000
	209	.word 0x20840008
	210	.word 0x20a50008
	211	.word 0x20c6ffff
	212	.word 0x14c0fffa
	213	.word 0x00000000
	214	.word 0x03e00008
	215	.word 0x00000000
03c031d5	216	.word 0x00000000
3e38691e WD	217	/* 0xbfc00428 */
	218	.word 0xdc870000
	219	.word 0xfca70000
	220	.word 0x20840008
	221	.word 0x20a50008
	222	.word 0x20c6ffff
	223	.word 0x14c0fffa
	224	.word 0x00000000
	225	.word 0x03e00008
	226	.word 0x00000000
03c031d5	227	.word 0x00000000
3e38691e	228	#endif /* CONFIG_PURPLE */
c021880a WD	229	.align 4
	230	reset:
	231
	232	/* Clear watch registers.
	233	*/
	234	mtc0 zero, CP0_WATCHLO
	235	mtc0 zero, CP0_WATCHHI
	236
d43d43ef SK	237	/* WP(Watch Pending), SW0/1 should be cleared. */
	238	mtc0 zero, CP0_CAUSE
	239
decaba6f	240	setup_c0_status_reset
c021880a	241
c021880a WD	242	/* Init Timer */
	243	mtc0 zero, CP0_COUNT
	244	mtc0 zero, CP0_COMPARE
	245
	246	/* CONFIG0 register */
	247	li t0, CONF_CM_UNCACHED
	248	mtc0 t0, CP0_CONFIG
	249
22069215	250	/* Initialize $gp.
03c031d5 SK	251	*/
03c031d5 SK	252	bal 1f
c75eba3b	253	nop
22069215	254	.word _gp
03c031d5	255	1:
16664f72	256	lw gp, 0(ra)
c75eba3b	257
8bde7f77	258	/* Initialize any external memory.
c021880a	259	*/
03c031d5 SK	260	la t9, lowlevel_init
03c031d5 SK	261	jalr t9
c021880a WD	262	nop
	263
	264	/* Initialize caches...
	265	*/
03c031d5 SK	266	la t9, mips_cache_reset
03c031d5 SK	267	jalr t9
c021880a WD	268	nop
	269
	270	/* ... and enable them.
	271	*/
	272	li t0, CONF_CM_CACHABLE_NONCOHERENT
	273	mtc0 t0, CP0_CONFIG
	274
c021880a WD	275	/* Set up temporary stack.
c021880a WD	276	*/
6d0f6bcf JCPV	277	#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
6d0f6bcf JCPV	278	li a0, CONFIG_SYS_INIT_SP_OFFSET
03c031d5 SK	279	la t9, mips_cache_lock
03c031d5 SK	280	jalr t9
c021880a	281	nop
e1390801	282	#endif
c021880a	283
6d0f6bcf	284	li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
c021880a WD	285	la sp, 0(t0)
c021880a WD	286
c021880a	287	la t9, board_init_f
43c50925	288	jr t9
c021880a WD	289	nop
c021880a WD	290
c021880a WD	291	/*
	292	* void relocate_code (addr_sp, gd, addr_moni)
	293	*
	294	* This "function" does not return, instead it continues in RAM
	295	* after relocating the monitor code.
	296	*
	297	* a0 = addr_sp
	298	* a1 = gd
	299	* a2 = destination address
	300	*/
	301	.globl relocate_code
	302	.ent relocate_code
	303	relocate_code:
03c031d5	304	move sp, a0 /* Set new stack pointer */
c021880a	305
6d0f6bcf	306	li t0, CONFIG_SYS_MONITOR_BASE
27b207fd WD	307	la t3, in_ram
	308	lw t2, -12(t3) /* t2 <-- uboot_end_data */
	309	move t1, a2
	310
c021880a	311	/*
22069215	312	* Fix $gp:
c021880a	313	*
6d0f6bcf	314	* New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
c021880a WD	315	*/
c021880a WD	316	move t6, gp
6d0f6bcf	317	sub gp, CONFIG_SYS_MONITOR_BASE
03c031d5 SK	318	add gp, a2 /* gp now adjusted */
03c031d5 SK	319	sub t6, gp, t6 /* t6 <-- relocation offset */
8bde7f77	320
c021880a WD	321	/*
	322	* t0 = source address
	323	* t1 = target address
	324	* t2 = source end address
	325	*/
3e38691e WD	326	/* On the purple board we copy the code earlier in a special way
	327	* in order to solve flash problems
	328	*/
	329	#ifndef CONFIG_PURPLE
c021880a WD	330	1:
	331	lw t3, 0(t0)
	332	sw t3, 0(t1)
	333	addu t0, 4
	334	ble t0, t2, 1b
03c031d5	335	addu t1, 4 /* delay slot */
3e38691e	336	#endif
c021880a WD	337
	338	/* If caches were enabled, we would have to flush them here.
	339	*/
	340
	341	/* Jump to where we've relocated ourselves.
	342	*/
	343	addi t0, a2, in_ram - _start
43c50925	344	jr t0
c021880a WD	345	nop
c021880a WD	346
53677ef1	347	.word _gp
0f8c62a1	348	.word _GLOBAL_OFFSET_TABLE_
c021880a WD	349	.word uboot_end_data
	350	.word uboot_end
	351	.word num_got_entries
	352
	353	in_ram:
22069215 SK	354	/*
	355	* Now we want to update GOT.
	356	*
	357	* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
	358	* generated by GNU ld. Skip these reserved entries from relocation.
c021880a WD	359	*/
c021880a WD	360	lw t3, -4(t0) /* t3 <-- num_got_entries */
0f8c62a1 VL	361	lw t4, -16(t0) /* t4 <-- _GLOBAL_OFFSET_TABLE_ */
	362	lw t5, -20(t0) /* t5 <-- _gp */
	363	sub t4, t5 /* compute offset*/
	364	add t4, t4, gp /* t4 now holds relocated _GLOBAL_OFFSET_TABLE_ */
22069215	365	addi t4, t4, 8 /* Skipping first two entries. */
c021880a WD	366	li t2, 2
	367	1:
	368	lw t1, 0(t4)
	369	beqz t1, 2f
	370	add t1, t6
	371	sw t1, 0(t4)
	372	2:
	373	addi t2, 1
	374	blt t2, t3, 1b
	375	addi t4, 4 /* delay slot */
	376
	377	/* Clear BSS.
	378	*/
	379	lw t1, -12(t0) /* t1 <-- uboot_end_data */
	380	lw t2, -8(t0) /* t2 <-- uboot_end */
	381	add t1, t6 /* adjust pointers */
	382	add t2, t6
	383
	384	sub t1, 4
03c031d5 SK	385	1:
03c031d5 SK	386	addi t1, 4
c021880a WD	387	bltl t1, t2, 1b
c021880a WD	388	sw zero, 0(t1) /* delay slot */
8bde7f77	389
c021880a WD	390	move a0, a1
c021880a WD	391	la t9, board_init_r
43c50925	392	jr t9
c021880a WD	393	move a1, a2 /* delay slot */
	394
	395	.end relocate_code
c021880a	396
c021880a WD	397	/* Exception handlers.
	398	*/
	399	romReserved:
03c031d5	400	b romReserved
c021880a WD	401
c021880a WD	402	romExcHandle:
03c031d5	403	b romExcHandle