]>
Commit | Line | Data |
---|---|---|
0db5bca8 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Martin Winistoerfer, martinwinistoerfer@gmx.ch. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
8bde7f77 | 20 | * Foundation, |
0db5bca8 WD |
21 | */ |
22 | ||
23 | /* | |
24 | * File: cpu.c | |
8bde7f77 WD |
25 | * |
26 | * Discription: Some cpu specific function for watchdog, | |
0db5bca8 | 27 | * cpu version test, clock setting ... |
8bde7f77 | 28 | * |
0db5bca8 WD |
29 | */ |
30 | ||
31 | ||
32 | #include <common.h> | |
33 | #include <watchdog.h> | |
34 | #include <command.h> | |
35 | #include <mpc5xx.h> | |
36 | ||
d87080b7 | 37 | DECLARE_GLOBAL_DATA_PTR; |
0db5bca8 WD |
38 | |
39 | #if (defined(CONFIG_MPC555)) | |
40 | # define ID_STR "MPC555/556" | |
41 | ||
42 | /* | |
43 | * Check version of cpu with Processor Version Register (PVR) | |
44 | */ | |
45 | static int check_cpu_version (long clock, uint pvr, uint immr) | |
46 | { | |
47 | char buf[32]; | |
48 | /* The highest 16 bits should be 0x0002 for a MPC555/556 */ | |
49 | if ((pvr >> 16) == 0x0002) { | |
50 | printf (" " ID_STR " Version %x", (pvr >> 16)); | |
51 | printf (" at %s MHz:", strmhz (buf, clock)); | |
52 | } else { | |
53 | printf ("Not supported cpu version"); | |
54 | return -1; | |
55 | } | |
56 | return 0; | |
57 | } | |
58 | #endif /* CONFIG_MPC555 */ | |
59 | ||
60 | ||
61 | /* | |
62 | * Check version of mpc5xx | |
63 | */ | |
64 | int checkcpu (void) | |
65 | { | |
0db5bca8 WD |
66 | ulong clock = gd->cpu_clk; |
67 | uint immr = get_immr (0); /* Return full IMMR contents */ | |
68 | uint pvr = get_pvr (); /* Retrieve PVR register */ | |
69 | ||
70 | puts ("CPU: "); | |
71 | ||
72 | return check_cpu_version (clock, pvr, immr); | |
73 | } | |
74 | ||
75 | /* | |
8bde7f77 | 76 | * Called by macro WATCHDOG_RESET |
0db5bca8 WD |
77 | */ |
78 | #if defined(CONFIG_WATCHDOG) | |
79 | void watchdog_reset (void) | |
80 | { | |
81 | int re_enable = disable_interrupts (); | |
82 | ||
6d0f6bcf | 83 | reset_5xx_watchdog ((immap_t *) CONFIG_SYS_IMMR); |
0db5bca8 WD |
84 | if (re_enable) |
85 | enable_interrupts (); | |
86 | } | |
87 | ||
88 | /* | |
89 | * Will clear software reset | |
90 | */ | |
91 | void reset_5xx_watchdog (volatile immap_t * immr) | |
92 | { | |
93 | /* Use the MPC5xx Internal Watchdog */ | |
94 | immr->im_siu_conf.sc_swsr = 0x556c; /* Prevent SW time-out */ | |
8bde7f77 | 95 | immr->im_siu_conf.sc_swsr = 0xaa39; |
0db5bca8 WD |
96 | } |
97 | ||
98 | #endif /* CONFIG_WATCHDOG */ | |
99 | ||
100 | ||
101 | /* | |
102 | * Get timebase clock frequency | |
103 | */ | |
104 | unsigned long get_tbclk (void) | |
105 | { | |
6d0f6bcf | 106 | volatile immap_t *immr = (volatile immap_t *) CONFIG_SYS_IMMR; |
0db5bca8 WD |
107 | ulong oscclk, factor; |
108 | ||
109 | if (immr->im_clkrst.car_sccr & SCCR_TBS) { | |
110 | return (gd->cpu_clk / 16); | |
111 | } | |
112 | ||
6d0f6bcf | 113 | factor = (((CONFIG_SYS_PLPRCR) & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT) + 1; |
0db5bca8 WD |
114 | |
115 | oscclk = gd->cpu_clk / factor; | |
116 | ||
117 | if ((immr->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) { | |
118 | return (oscclk / 4); | |
119 | } | |
120 | return (oscclk / 16); | |
121 | } | |
122 | ||
b6e4c403 WD |
123 | void dcache_enable (void) |
124 | { | |
125 | return; | |
126 | } | |
127 | ||
128 | void dcache_disable (void) | |
129 | { | |
130 | return; | |
131 | } | |
132 | ||
133 | int dcache_status (void) | |
134 | { | |
135 | return 0; /* always off */ | |
136 | } | |
0db5bca8 WD |
137 | |
138 | /* | |
8bde7f77 | 139 | * Reset board |
0db5bca8 WD |
140 | */ |
141 | int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) | |
142 | { | |
b6e4c403 | 143 | #if defined(CONFIG_PATI) |
6d0f6bcf | 144 | volatile ulong *addr = (ulong *) CONFIG_SYS_RESET_ADDRESS; |
b6e4c403 WD |
145 | *addr = 1; |
146 | #else | |
0db5bca8 | 147 | ulong addr; |
8bde7f77 | 148 | |
0db5bca8 | 149 | /* Interrupts off, enable reset */ |
8bde7f77 | 150 | __asm__ volatile (" mtspr 81, %r0 \n\t" |
cceb871f WD |
151 | " mfmsr %r3 \n\t" |
152 | " rlwinm %r31,%r3,0,25,23\n\t" | |
153 | " mtmsr %r31 \n\t"); | |
8bde7f77 WD |
154 | /* |
155 | * Trying to execute the next instruction at a non-existing address | |
156 | * should cause a machine check, resulting in reset | |
157 | */ | |
6d0f6bcf JCPV |
158 | #ifdef CONFIG_SYS_RESET_ADDRESS |
159 | addr = CONFIG_SYS_RESET_ADDRESS; | |
0db5bca8 | 160 | #else |
8bde7f77 | 161 | /* |
6d0f6bcf JCPV |
162 | * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE * - sizeof (ulong) is usually a valid address. Better pick an address |
163 | * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS. | |
8bde7f77 WD |
164 | * "(ulong)-1" used to be a good choice for many systems... |
165 | */ | |
6d0f6bcf | 166 | addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); |
0db5bca8 WD |
167 | #endif |
168 | ((void (*) (void)) addr) (); | |
b6e4c403 | 169 | #endif /* #if defined(CONFIG_PATI) */ |
0db5bca8 WD |
170 | return 1; |
171 | } |