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945af8d7 WD |
1 | /* |
2 | * (C) Copyright 2000-2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <mpc5xxx.h> | |
26 | ||
d87080b7 WD |
27 | DECLARE_GLOBAL_DATA_PTR; |
28 | ||
945af8d7 WD |
29 | /* |
30 | * Breath some life into the CPU... | |
31 | * | |
32 | * Set up the memory map, | |
33 | * initialize a bunch of registers. | |
34 | */ | |
35 | void cpu_init_f (void) | |
36 | { | |
945af8d7 | 37 | unsigned long addecr = (1 << 25); /* Boot_CS */ |
6d0f6bcf | 38 | #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_MGT5100) |
945af8d7 WD |
39 | addecr |= (1 << 22); /* SDRAM enable */ |
40 | #endif | |
41 | /* Pointer is writable since we allocated a register for it */ | |
6d0f6bcf | 42 | gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); |
945af8d7 WD |
43 | |
44 | /* Clear initial global data */ | |
45 | memset ((void *) gd, 0, sizeof (gd_t)); | |
46 | ||
47 | /* | |
48 | * Memory Controller: configure chip selects and enable them | |
49 | */ | |
6d0f6bcf JCPV |
50 | #if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE) |
51 | *(vu_long *)MPC5XXX_BOOTCS_START = START_REG(CONFIG_SYS_BOOTCS_START); | |
52 | *(vu_long *)MPC5XXX_BOOTCS_STOP = STOP_REG(CONFIG_SYS_BOOTCS_START, | |
53 | CONFIG_SYS_BOOTCS_SIZE); | |
945af8d7 | 54 | #endif |
6d0f6bcf JCPV |
55 | #if defined(CONFIG_SYS_BOOTCS_CFG) |
56 | *(vu_long *)MPC5XXX_BOOTCS_CFG = CONFIG_SYS_BOOTCS_CFG; | |
945af8d7 WD |
57 | #endif |
58 | ||
6d0f6bcf JCPV |
59 | #if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE) |
60 | *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_CS0_START); | |
61 | *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_CS0_START, CONFIG_SYS_CS0_SIZE); | |
945af8d7 WD |
62 | /* CS0 and BOOT_CS cannot be enabled at once. */ |
63 | /* addecr |= (1 << 16); */ | |
64 | #endif | |
6d0f6bcf JCPV |
65 | #if defined(CONFIG_SYS_CS0_CFG) |
66 | *(vu_long *)MPC5XXX_CS0_CFG = CONFIG_SYS_CS0_CFG; | |
945af8d7 WD |
67 | #endif |
68 | ||
6d0f6bcf JCPV |
69 | #if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE) |
70 | *(vu_long *)MPC5XXX_CS1_START = START_REG(CONFIG_SYS_CS1_START); | |
71 | *(vu_long *)MPC5XXX_CS1_STOP = STOP_REG(CONFIG_SYS_CS1_START, CONFIG_SYS_CS1_SIZE); | |
945af8d7 WD |
72 | addecr |= (1 << 17); |
73 | #endif | |
6d0f6bcf JCPV |
74 | #if defined(CONFIG_SYS_CS1_CFG) |
75 | *(vu_long *)MPC5XXX_CS1_CFG = CONFIG_SYS_CS1_CFG; | |
945af8d7 WD |
76 | #endif |
77 | ||
6d0f6bcf JCPV |
78 | #if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE) |
79 | *(vu_long *)MPC5XXX_CS2_START = START_REG(CONFIG_SYS_CS2_START); | |
80 | *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START, CONFIG_SYS_CS2_SIZE); | |
945af8d7 WD |
81 | addecr |= (1 << 18); |
82 | #endif | |
6d0f6bcf JCPV |
83 | #if defined(CONFIG_SYS_CS2_CFG) |
84 | *(vu_long *)MPC5XXX_CS2_CFG = CONFIG_SYS_CS2_CFG; | |
945af8d7 WD |
85 | #endif |
86 | ||
6d0f6bcf JCPV |
87 | #if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE) |
88 | *(vu_long *)MPC5XXX_CS3_START = START_REG(CONFIG_SYS_CS3_START); | |
89 | *(vu_long *)MPC5XXX_CS3_STOP = STOP_REG(CONFIG_SYS_CS3_START, CONFIG_SYS_CS3_SIZE); | |
945af8d7 WD |
90 | addecr |= (1 << 19); |
91 | #endif | |
6d0f6bcf JCPV |
92 | #if defined(CONFIG_SYS_CS3_CFG) |
93 | *(vu_long *)MPC5XXX_CS3_CFG = CONFIG_SYS_CS3_CFG; | |
945af8d7 WD |
94 | #endif |
95 | ||
6d0f6bcf JCPV |
96 | #if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE) |
97 | *(vu_long *)MPC5XXX_CS4_START = START_REG(CONFIG_SYS_CS4_START); | |
98 | *(vu_long *)MPC5XXX_CS4_STOP = STOP_REG(CONFIG_SYS_CS4_START, CONFIG_SYS_CS4_SIZE); | |
945af8d7 WD |
99 | addecr |= (1 << 20); |
100 | #endif | |
6d0f6bcf JCPV |
101 | #if defined(CONFIG_SYS_CS4_CFG) |
102 | *(vu_long *)MPC5XXX_CS4_CFG = CONFIG_SYS_CS4_CFG; | |
945af8d7 WD |
103 | #endif |
104 | ||
6d0f6bcf JCPV |
105 | #if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE) |
106 | *(vu_long *)MPC5XXX_CS5_START = START_REG(CONFIG_SYS_CS5_START); | |
107 | *(vu_long *)MPC5XXX_CS5_STOP = STOP_REG(CONFIG_SYS_CS5_START, CONFIG_SYS_CS5_SIZE); | |
945af8d7 WD |
108 | addecr |= (1 << 21); |
109 | #endif | |
6d0f6bcf JCPV |
110 | #if defined(CONFIG_SYS_CS5_CFG) |
111 | *(vu_long *)MPC5XXX_CS5_CFG = CONFIG_SYS_CS5_CFG; | |
945af8d7 WD |
112 | #endif |
113 | ||
114 | #if defined(CONFIG_MPC5200) | |
115 | addecr |= 1; | |
6d0f6bcf JCPV |
116 | #if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE) |
117 | *(vu_long *)MPC5XXX_CS6_START = START_REG(CONFIG_SYS_CS6_START); | |
118 | *(vu_long *)MPC5XXX_CS6_STOP = STOP_REG(CONFIG_SYS_CS6_START, CONFIG_SYS_CS6_SIZE); | |
945af8d7 WD |
119 | addecr |= (1 << 26); |
120 | #endif | |
6d0f6bcf JCPV |
121 | #if defined(CONFIG_SYS_CS6_CFG) |
122 | *(vu_long *)MPC5XXX_CS6_CFG = CONFIG_SYS_CS6_CFG; | |
945af8d7 WD |
123 | #endif |
124 | ||
6d0f6bcf JCPV |
125 | #if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE) |
126 | *(vu_long *)MPC5XXX_CS7_START = START_REG(CONFIG_SYS_CS7_START); | |
127 | *(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CONFIG_SYS_CS7_START, CONFIG_SYS_CS7_SIZE); | |
945af8d7 WD |
128 | addecr |= (1 << 27); |
129 | #endif | |
6d0f6bcf JCPV |
130 | #if defined(CONFIG_SYS_CS7_CFG) |
131 | *(vu_long *)MPC5XXX_CS7_CFG = CONFIG_SYS_CS7_CFG; | |
945af8d7 WD |
132 | #endif |
133 | ||
6d0f6bcf JCPV |
134 | #if defined(CONFIG_SYS_CS_BURST) |
135 | *(vu_long *)MPC5XXX_CS_BURST = CONFIG_SYS_CS_BURST; | |
945af8d7 | 136 | #endif |
6d0f6bcf JCPV |
137 | #if defined(CONFIG_SYS_CS_DEADCYCLE) |
138 | *(vu_long *)MPC5XXX_CS_DEADCYCLE = CONFIG_SYS_CS_DEADCYCLE; | |
945af8d7 WD |
139 | #endif |
140 | #endif /* CONFIG_MPC5200 */ | |
141 | ||
142 | /* Enable chip selects */ | |
143 | *(vu_long *)MPC5XXX_ADDECR = addecr; | |
144 | *(vu_long *)MPC5XXX_CS_CTRL = (1 << 24); | |
145 | ||
146 | /* Setup pin multiplexing */ | |
6d0f6bcf JCPV |
147 | #if defined(CONFIG_SYS_GPS_PORT_CONFIG) |
148 | *(vu_long *)MPC5XXX_GPS_PORT_CONFIG = CONFIG_SYS_GPS_PORT_CONFIG; | |
945af8d7 | 149 | #endif |
96dd9af4 WD |
150 | |
151 | #if defined(CONFIG_MPC5200) | |
152 | /* enable timebase */ | |
153 | *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 13); | |
7152b1d0 | 154 | |
8419c013 WD |
155 | /* Enable snooping for RAM */ |
156 | *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15); | |
6d0f6bcf | 157 | *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CONFIG_SYS_SDRAM_BASE | 0x1d; |
8419c013 | 158 | |
6d0f6bcf | 159 | # if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) |
7152b1d0 WD |
160 | /* Motorola reports IPB should better run at 133 MHz. */ |
161 | *(vu_long *)MPC5XXX_ADDECR |= 1; | |
162 | /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */ | |
163 | addecr = *(vu_long *)MPC5XXX_CDM_CFG; | |
164 | addecr &= ~0x103; | |
6d0f6bcf | 165 | # if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2) |
56523f12 WD |
166 | /* pci_clk_sel = 0x01 -> IPB_CLK/2 */ |
167 | addecr |= 0x01; | |
168 | # else | |
169 | /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */ | |
7152b1d0 | 170 | addecr |= 0x02; |
6d0f6bcf | 171 | # endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */ |
7152b1d0 | 172 | *(vu_long *)MPC5XXX_CDM_CFG = addecr; |
6d0f6bcf | 173 | # endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */ |
4aeb251f WD |
174 | /* Configure the XLB Arbiter */ |
175 | *(vu_long *)MPC5XXX_XLBARB_MPRIEN = 0xff; | |
176 | *(vu_long *)MPC5XXX_XLBARB_MPRIVAL = 0x11111111; | |
e1599e83 | 177 | |
6d0f6bcf | 178 | # if defined(CONFIG_SYS_XLB_PIPELINING) |
e1599e83 WD |
179 | /* Enable piplining */ |
180 | *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31); | |
181 | # endif | |
56523f12 | 182 | #endif /* CONFIG_MPC5200 */ |
945af8d7 WD |
183 | } |
184 | ||
185 | /* | |
186 | * initialize higher level parts of CPU like time base and timers | |
187 | */ | |
188 | int cpu_init_r (void) | |
189 | { | |
190 | /* mask all interrupts */ | |
191 | #if defined(CONFIG_MGT5100) | |
192 | *(vu_long *)MPC5XXX_ICTL_PER_MASK = 0xfffffc00; | |
193 | #elif defined(CONFIG_MPC5200) | |
194 | *(vu_long *)MPC5XXX_ICTL_PER_MASK = 0xffffff00; | |
195 | #endif | |
196 | *(vu_long *)MPC5XXX_ICTL_CRIT |= 0x0001ffff; | |
197 | *(vu_long *)MPC5XXX_ICTL_EXT &= ~0x00000f00; | |
4aeb251f WD |
198 | /* route critical ints to normal ints */ |
199 | *(vu_long *)MPC5XXX_ICTL_EXT |= 0x00000001; | |
945af8d7 | 200 | |
4431283c | 201 | #if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC) |
945af8d7 WD |
202 | /* load FEC microcode */ |
203 | loadtask(0, 2); | |
204 | #endif | |
205 | ||
206 | return (0); | |
207 | } |