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Add support for multiple PHYs.
[people/ms/u-boot.git] / cpu / mpc5xxx / fec.c
CommitLineData
945af8d7 1/*
5e5f9ed2 2 * (C) Copyright 2003-2005
945af8d7
WD		 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
7 */
8
9#include <common.h>
10#include <mpc5xxx.h>
11#include <malloc.h>
12#include <net.h>
13#include <miiphy.h>
14#include "sdma.h"
15#include "fec.h"
16
77846748 17/* #define DEBUG 0x28 */
945af8d7
WD		 18
19#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
cbd8a35c 20 defined(CONFIG_MPC5xxx_FEC)
945af8d7 21
63ff004c
MB		 22#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
23#error "CONFIG_MII has to be defined!"
24#endif
25
945af8d7 26#if (DEBUG & 0x60)
63ff004c
MB		 27static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
28static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
945af8d7
WD		 29#endif /* DEBUG */
30
31#if (DEBUG & 0x40)
32static uint32 local_crc32(char *string, unsigned int crc_value, int len);
33#endif
34
77846748
WD		 35typedef struct {
36 uint8 data[1500]; /* actual data */
37 int length; /* actual length */
38 int used; /* buffer in use or not */
39 uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
40} NBUF;
41
63ff004c
MB		 42int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
43int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
44
d4ca31c4
WD		 45/********************************************************************/
46#if (DEBUG & 0x2)
63ff004c 47static void mpc5xxx_fec_phydump (char *devname)
d4ca31c4
WD		 48{
49 uint16 phyStatus, i;
50 uint8 phyAddr = CONFIG_PHY_ADDR;
51 uint8 reg_mask[] = {
52#if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
53 /* regs to print: 0...7, 16...19, 21, 23, 24 */
54 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
55 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
56#else
57 /* regs to print: 0...8, 16...20 */
58 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
59 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
60#endif
61 };
62
63 for (i = 0; i < 32; i++) {
64 if (reg_mask[i]) {
63ff004c 65 miiphy_read(devname, phyAddr, i, &phyStatus);
d4ca31c4
WD		 66 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
67 }
68 }
69}
70#endif
71
945af8d7
WD		 72/********************************************************************/
73static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
74{
75 int ix;
76 char *data;
77846748 77 static int once = 0;
945af8d7 78
945af8d7 79 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
77846748
WD		 80 if (!once) {
81 data = (char *)malloc(FEC_MAX_PKT_SIZE);
82 if (data == NULL) {
83 printf ("RBD INIT FAILED\n");
84 return -1;
85 }
86 fec->rbdBase[ix].dataPointer = (uint32)data;
945af8d7
WD		 87 }
88 fec->rbdBase[ix].status = FEC_RBD_EMPTY;
89 fec->rbdBase[ix].dataLength = 0;
945af8d7 90 }
77846748 91 once ++;
945af8d7
WD		 92
93 /*
94 * have the last RBD to close the ring
95 */
96 fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
97 fec->rbdIndex = 0;
98
99 return 0;
100}
101
102/********************************************************************/
103static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
104{
105 int ix;
106
107 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
108 fec->tbdBase[ix].status = 0;
109 }
110
111 /*
112 * Have the last TBD to close the ring
113 */
114 fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
115
116 /*
117 * Initialize some indices
118 */
119 fec->tbdIndex = 0;
120 fec->usedTbdIndex = 0;
121 fec->cleanTbdNum = FEC_TBD_NUM;
122}
123
124/********************************************************************/
151ab83a 125static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd)
945af8d7
WD		 126{
127 /*
128 * Reset buffer descriptor as empty
129 */
130 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
131 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
132 else
133 pRbd->status = FEC_RBD_EMPTY;
134
135 pRbd->dataLength = 0;
136
137 /*
138 * Now, we have an empty RxBD, restart the SmartDMA receive task
139 */
140 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
141
142 /*
143 * Increment BD count
144 */
145 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
146}
147
148/********************************************************************/
149static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
150{
151ab83a 151 volatile FEC_TBD *pUsedTbd;
945af8d7
WD		 152
153#if (DEBUG & 0x1)
154 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
155 fec->cleanTbdNum, fec->usedTbdIndex);
156#endif
157
158 /*
159 * process all the consumed TBDs
160 */
161 while (fec->cleanTbdNum < FEC_TBD_NUM) {
162 pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
163 if (pUsedTbd->status & FEC_TBD_READY) {
164#if (DEBUG & 0x20)
165 printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
166#endif
167 return;
168 }
169
170 /*
171 * clean this buffer descriptor
172 */
173 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
174 pUsedTbd->status = FEC_TBD_WRAP;
175 else
176 pUsedTbd->status = 0;
177
178 /*
179 * update some indeces for a correct handling of the TBD ring
180 */
181 fec->cleanTbdNum++;
182 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
183 }
184}
185
186/********************************************************************/
187static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
188{
189 uint8 currByte; /* byte for which to compute the CRC */
190 int byte; /* loop - counter */
191 int bit; /* loop - counter */
192 uint32 crc = 0xffffffff; /* initial value */
193
194 /*
195 * The algorithm used is the following:
196 * we loop on each of the six bytes of the provided address,
197 * and we compute the CRC by left-shifting the previous
198 * value by one position, so that each bit in the current
199 * byte of the address may contribute the calculation. If
200 * the latter and the MSB in the CRC are different, then
201 * the CRC value so computed is also ex-ored with the
202 * "polynomium generator". The current byte of the address
203 * is also shifted right by one bit at each iteration.
204 * This is because the CRC generatore in hardware is implemented
205 * as a shift-register with as many ex-ores as the radixes
206 * in the polynomium. This suggests that we represent the
207 * polynomiumm itself as a 32-bit constant.
208 */
209 for (byte = 0; byte < 6; byte++) {
210 currByte = mac[byte];
211 for (bit = 0; bit < 8; bit++) {
212 if ((currByte & 0x01) ^ (crc & 0x01)) {
213 crc >>= 1;
214 crc = crc ^ 0xedb88320;
215 } else {
216 crc >>= 1;
217 }
218 currByte >>= 1;
219 }
220 }
221
222 crc = crc >> 26;
223
224 /*
225 * Set individual hash table register
226 */
227 if (crc >= 32) {
228 fec->eth->iaddr1 = (1 << (crc - 32));
229 fec->eth->iaddr2 = 0;
230 } else {
231 fec->eth->iaddr1 = 0;
232 fec->eth->iaddr2 = (1 << crc);
233 }
234
235 /*
236 * Set physical address
237 */
238 fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
239 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
240}
241
242/********************************************************************/
243static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
244{
7152b1d0 245 DECLARE_GLOBAL_DATA_PTR;
945af8d7
WD		 246 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
247 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
945af8d7
WD		 248
249#if (DEBUG & 0x1)
250 printf ("mpc5xxx_fec_init... Begin\n");
251#endif
252
253 /*
254 * Initialize RxBD/TxBD rings
255 */
256 mpc5xxx_fec_rbd_init(fec);
257 mpc5xxx_fec_tbd_init(fec);
258
945af8d7
WD		 259 /*
260 * Clear FEC-Lite interrupt event register(IEVENT)
261 */
262 fec->eth->ievent = 0xffffffff;
263
264 /*
265 * Set interrupt mask register
266 */
267 fec->eth->imask = 0x00000000;
268
269 /*
270 * Set FEC-Lite receive control register(R_CNTRL):
271 */
272 if (fec->xcv_type == SEVENWIRE) {
273 /*
274 * Frame length=1518; 7-wire mode
275 */
276 fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
277 } else {
278 /*
279 * Frame length=1518; MII mode;
280 */
281 fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
282 }
283
7e780369
WD		 284 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
285 if (fec->xcv_type != SEVENWIRE) {
945af8d7 286 /*
7152b1d0 287 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
945af8d7
WD		 288 * and do not drop the Preamble.
289 */
7152b1d0 290 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
945af8d7
WD		 291 }
292
293 /*
294 * Set Opcode/Pause Duration Register
295 */
296 fec->eth->op_pause = 0x00010020; /*FIXME0xffff0020; */
297
298 /*
299 * Set Rx FIFO alarm and granularity value
300 */
c44ffb9e
WD		 301 fec->eth->rfifo_cntrl = 0x0c000000
302 | (fec->eth->rfifo_cntrl & ~0x0f000000);
945af8d7
WD		 303 fec->eth->rfifo_alarm = 0x0000030c;
304#if (DEBUG & 0x22)
305 if (fec->eth->rfifo_status & 0x00700000 ) {
306 printf("mpc5xxx_fec_init() RFIFO error\n");
307 }
308#endif
309
310 /*
311 * Set Tx FIFO granularity value
312 */
c44ffb9e
WD		 313 fec->eth->tfifo_cntrl = 0x0c000000
314 | (fec->eth->tfifo_cntrl & ~0x0f000000);
945af8d7
WD		 315#if (DEBUG & 0x2)
316 printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
317 printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
318#endif
319
320 /*
321 * Set transmit fifo watermark register(X_WMRK), default = 64
322 */
323 fec->eth->tfifo_alarm = 0x00000080;
324 fec->eth->x_wmrk = 0x2;
325
326 /*
327 * Set individual address filter for unicast address
328 * and set physical address registers.
329 */
77ddac94 330 mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr);
945af8d7
WD		 331
332 /*
333 * Set multicast address filter
334 */
335 fec->eth->gaddr1 = 0x00000000;
336 fec->eth->gaddr2 = 0x00000000;
337
338 /*
339 * Turn ON cheater FSM: ????
340 */
341 fec->eth->xmit_fsm = 0x03000000;
342
343#if defined(CONFIG_MPC5200)
344 /*
345 * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
346 * work w/ the current receive task.
347 */
348 sdma->PtdCntrl |= 0x00000001;
349#endif
350
351 /*
352 * Set priority of different initiators
353 */
354 sdma->IPR0 = 7; /* always */
355 sdma->IPR3 = 6; /* Eth RX */
356 sdma->IPR4 = 5; /* Eth Tx */
357
358 /*
359 * Clear SmartDMA task interrupt pending bits
360 */
361 SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
362
945af8d7
WD		 363 /*
364 * Initialize SmartDMA parameters stored in SRAM
365 */
151ab83a
WD		 366 *(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase;
367 *(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase;
368 *(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase;
369 *(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase;
945af8d7 370
6c1362cf
WD		 371 /*
372 * Enable FEC-Lite controller
373 */
374 fec->eth->ecntrl |= 0x00000006;
375
376#if (DEBUG & 0x2)
377 if (fec->xcv_type != SEVENWIRE)
378 mpc5xxx_fec_phydump ();
379#endif
380
381 /*
382 * Enable SmartDMA receive task
383 */
384 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
385
386#if (DEBUG & 0x1)
387 printf("mpc5xxx_fec_init... Done \n");
388#endif
389
390 return 1;
391}
392
393/********************************************************************/
394static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
395{
396 DECLARE_GLOBAL_DATA_PTR;
397 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
398 const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
399
400#if (DEBUG & 0x1)
401 printf ("mpc5xxx_fec_init_phy... Begin\n");
402#endif
403
404 /*
405 * Initialize GPIO pins
406 */
407 if (fec->xcv_type == SEVENWIRE) {
408 /* 10MBit with 7-wire operation */
6c7a1408
WD		 409#if defined(CONFIG_TOTAL5200)
410 /* 7-wire and USB2 on Ethernet */
411 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000;
412#else /* !CONFIG_TOTAL5200 */
413 /* 7-wire only */
6c1362cf 414 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
6c7a1408 415#endif /* CONFIG_TOTAL5200 */
6c1362cf
WD		 416 } else {
417 /* 100MBit with MD operation */
418 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
419 }
420
421 /*
422 * Clear FEC-Lite interrupt event register(IEVENT)
423 */
424 fec->eth->ievent = 0xffffffff;
425
426 /*
427 * Set interrupt mask register
428 */
429 fec->eth->imask = 0x00000000;
430
431 if (fec->xcv_type != SEVENWIRE) {
432 /*
433 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
434 * and do not drop the Preamble.
435 */
436 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
437 }
438
945af8d7
WD		 439 if (fec->xcv_type != SEVENWIRE) {
440 /*
441 * Initialize PHY(LXT971A):
442 *
443 * Generally, on power up, the LXT971A reads its configuration
444 * pins to check for forced operation, If not cofigured for
445 * forced operation, it uses auto-negotiation/parallel detection
446 * to automatically determine line operating conditions.
447 * If the PHY device on the other side of the link supports
448 * auto-negotiation, the LXT971A auto-negotiates with it
449 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
450 * support auto-negotiation, the LXT971A automatically detects
451 * the presence of either link pulses(10Mbps PHY) or Idle
452 * symbols(100Mbps) and sets its operating conditions accordingly.
453 *
454 * When auto-negotiation is controlled by software, the following
455 * steps are recommended.
456 *
457 * Note:
458 * The physical address is dependent on hardware configuration.
459 *
460 */
461 int timeout = 1;
462 uint16 phyStatus;
463
464 /*
465 * Reset PHY, then delay 300ns
466 */
63ff004c 467 miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
945af8d7
WD		 468 udelay(1000);
469
470 if (fec->xcv_type == MII10) {
471 /*
472 * Force 10Base-T, FDX operation
473 */
a57106fc 474#if (DEBUG & 0x2)
945af8d7 475 printf("Forcing 10 Mbps ethernet link... ");
a57106fc 476#endif
63ff004c 477 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
945af8d7 478 /*
63ff004c 479 miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
945af8d7 480 */
63ff004c 481 miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
945af8d7
WD		 482
483 timeout = 20;
484 do { /* wait for link status to go down */
485 udelay(10000);
486 if ((timeout--) == 0) {
487#if (DEBUG & 0x2)
488 printf("hmmm, should not have waited...");
489#endif
490 break;
491 }
63ff004c 492 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
945af8d7
WD		 493#if (DEBUG & 0x2)
494 printf("=");
495#endif
496 } while ((phyStatus & 0x0004)); /* !link up */
497
498 timeout = 1000;
499 do { /* wait for link status to come back up */
500 udelay(10000);
501 if ((timeout--) == 0) {
502 printf("failed. Link is down.\n");
503 break;
504 }
63ff004c 505 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
945af8d7
WD		 506#if (DEBUG & 0x2)
507 printf("+");
508#endif
509 } while (!(phyStatus & 0x0004)); /* !link up */
510
ab209d51 511#if (DEBUG & 0x2)
945af8d7 512 printf ("done.\n");
ab209d51 513#endif
945af8d7
WD		 514 } else { /* MII100 */
515 /*
516 * Set the auto-negotiation advertisement register bits
517 */
63ff004c 518 miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
945af8d7
WD		 519
520 /*
521 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
522 */
63ff004c 523 miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
945af8d7
WD		 524
525 /*
526 * Wait for AN completion
527 */
528 timeout = 5000;
529 do {
530 udelay(1000);
531
532 if ((timeout--) == 0) {
533#if (DEBUG & 0x2)
534 printf("PHY auto neg 0 failed...\n");
535#endif
536 return -1;
537 }
538
63ff004c 539 if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
945af8d7
WD		 540#if (DEBUG & 0x2)
541 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
542#endif
543 return -1;
544 }
7e780369 545 } while (!(phyStatus & 0x0004));
945af8d7
WD		 546
547#if (DEBUG & 0x2)
548 printf("PHY auto neg complete! \n");
549#endif
550 }
551
552 }
553
945af8d7 554#if (DEBUG & 0x2)
d4ca31c4 555 if (fec->xcv_type != SEVENWIRE)
63ff004c 556 mpc5xxx_fec_phydump (dev->name);
945af8d7 557#endif
d4ca31c4 558
945af8d7
WD		 559
560#if (DEBUG & 0x1)
6c1362cf 561 printf("mpc5xxx_fec_init_phy... Done \n");
945af8d7
WD		 562#endif
563
013dc8d9 564 return 1;
945af8d7
WD		 565}
566
567/********************************************************************/
568static void mpc5xxx_fec_halt(struct eth_device *dev)
569{
77846748 570#if defined(CONFIG_MPC5200)
945af8d7 571 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
77846748
WD		 572#endif
573 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
945af8d7
WD		 574 int counter = 0xffff;
575
576#if (DEBUG & 0x2)
d4ca31c4
WD		 577 if (fec->xcv_type != SEVENWIRE)
578 mpc5xxx_fec_phydump ();
945af8d7
WD		 579#endif
580
945af8d7
WD		 581 /*
582 * mask FEC chip interrupts
583 */
584 fec->eth->imask = 0;
585
586 /*
587 * issue graceful stop command to the FEC transmitter if necessary
588 */
589 fec->eth->x_cntrl |= 0x00000001;
590
591 /*
592 * wait for graceful stop to register
593 */
594 while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
595
945af8d7
WD		 596 /*
597 * Disable SmartDMA tasks
598 */
599 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
600 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
601
602#if defined(CONFIG_MPC5200)
603 /*
604 * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
605 * done. It doesn't work w/ the current receive task.
606 */
607 sdma->PtdCntrl &= ~0x00000001;
608#endif
609
610 /*
611 * Disable the Ethernet Controller
612 */
613 fec->eth->ecntrl &= 0xfffffffd;
614
615 /*
616 * Clear FIFO status registers
617 */
618 fec->eth->rfifo_status &= 0x00700000;
619 fec->eth->tfifo_status &= 0x00700000;
620
621 fec->eth->reset_cntrl = 0x01000000;
622
623 /*
624 * Issue a reset command to the FEC chip
625 */
626 fec->eth->ecntrl |= 0x1;
627
628 /*
629 * wait at least 16 clock cycles
630 */
631 udelay(10);
632
633#if (DEBUG & 0x3)
634 printf("Ethernet task stopped\n");
635#endif
636}
637
638#if (DEBUG & 0x60)
639/********************************************************************/
640
63ff004c 641static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
945af8d7 642{
d4ca31c4 643 uint16 phyAddr = CONFIG_PHY_ADDR;
945af8d7
WD		 644 uint16 phyStatus;
645
646 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
647 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
648
63ff004c 649 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
945af8d7
WD		 650 printf("\nphyStatus: 0x%04x\n", phyStatus);
651 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
652 printf("ievent: 0x%08x\n", fec->eth->ievent);
653 printf("x_status: 0x%08x\n", fec->eth->x_status);
654 printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
655
656 printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
657 printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
658 printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
659 printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
660 printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
661 printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
662 }
663}
664
63ff004c 665static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
945af8d7 666{
d4ca31c4 667 uint16 phyAddr = CONFIG_PHY_ADDR;
945af8d7
WD		 668 uint16 phyStatus;
669
670 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
671 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
672
63ff004c 673 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
945af8d7
WD		 674 printf("\nphyStatus: 0x%04x\n", phyStatus);
675 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
676 printf("ievent: 0x%08x\n", fec->eth->ievent);
677 printf("x_status: 0x%08x\n", fec->eth->x_status);
678 printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
679
680 printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
681 printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
682 printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
683 printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
684 printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
685 printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
686 }
687}
688#endif /* DEBUG */
689
690/********************************************************************/
691
692static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
693 int data_length)
694{
695 /*
696 * This routine transmits one frame. This routine only accepts
697 * 6-byte Ethernet addresses.
698 */
699 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
151ab83a 700 volatile FEC_TBD *pTbd;
945af8d7
WD		 701
702#if (DEBUG & 0x20)
703 printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
63ff004c 704 tfifo_print(dev->name, fec);
945af8d7
WD		 705#endif
706
707 /*
708 * Clear Tx BD ring at first
709 */
710 mpc5xxx_fec_tbd_scrub(fec);
711
712 /*
713 * Check for valid length of data.
714 */
715 if ((data_length > 1500) || (data_length <= 0)) {
716 return -1;
717 }
718
719 /*
720 * Check the number of vacant TxBDs.
721 */
722 if (fec->cleanTbdNum < 1) {
723#if (DEBUG & 0x20)
724 printf("No available TxBDs ...\n");
725#endif
726 return -1;
727 }
728
729 /*
730 * Get the first TxBD to send the mac header
731 */
732 pTbd = &fec->tbdBase[fec->tbdIndex];
733 pTbd->dataLength = data_length;
734 pTbd->dataPointer = (uint32)eth_data;
77846748 735 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
945af8d7
WD		 736 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
737
738#if (DEBUG & 0x100)
739 printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
740#endif
741
742 /*
743 * Kick the MII i/f
744 */
745 if (fec->xcv_type != SEVENWIRE) {
746 uint16 phyStatus;
63ff004c 747 miiphy_read(dev->name, 0, 0x1, &phyStatus);
945af8d7
WD		 748 }
749
750 /*
751 * Enable SmartDMA transmit task
752 */
753
754#if (DEBUG & 0x20)
63ff004c 755 tfifo_print(dev->name, fec);
945af8d7
WD		 756#endif
757 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
758#if (DEBUG & 0x20)
63ff004c 759 tfifo_print(dev->name, fec);
945af8d7
WD		 760#endif
761#if (DEBUG & 0x8)
762 printf( "+" );
763#endif
764
765 fec->cleanTbdNum -= 1;
766
767#if (DEBUG & 0x129) && (DEBUG & 0x80000000)
768 printf ("smartDMA ethernet Tx task enabled\n");
769#endif
770 /*
771 * wait until frame is sent .
772 */
773 while (pTbd->status & FEC_TBD_READY) {
774 udelay(10);
775#if (DEBUG & 0x8)
776 printf ("TDB status = %04x\n", pTbd->status);
777#endif
778 }
779
780 return 0;
781}
782
783
784/********************************************************************/
785static int mpc5xxx_fec_recv(struct eth_device *dev)
786{
787 /*
788 * This command pulls one frame from the card
789 */
790 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
151ab83a 791 volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
945af8d7 792 unsigned long ievent;
77846748
WD		 793 int frame_length, len = 0;
794 NBUF *frame;
77ddac94 795 uchar buff[FEC_MAX_PKT_SIZE];
945af8d7
WD		 796
797#if (DEBUG & 0x1)
798 printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
799#endif
800#if (DEBUG & 0x8)
801 printf( "-" );
802#endif
803
804 /*
805 * Check if any critical events have happened
806 */
807 ievent = fec->eth->ievent;
808 fec->eth->ievent = ievent;
809 if (ievent & 0x20060000) {
810 /* BABT, Rx/Tx FIFO errors */
811 mpc5xxx_fec_halt(dev);
812 mpc5xxx_fec_init(dev, NULL);
813 return 0;
814 }
815 if (ievent & 0x80000000) {
816 /* Heartbeat error */
817 fec->eth->x_cntrl |= 0x00000001;
818 }
819 if (ievent & 0x10000000) {
820 /* Graceful stop complete */
821 if (fec->eth->x_cntrl & 0x00000001) {
822 mpc5xxx_fec_halt(dev);
823 fec->eth->x_cntrl &= ~0x00000001;
824 mpc5xxx_fec_init(dev, NULL);
825 }
826 }
827
77846748
WD		 828 if (!(pRbd->status & FEC_RBD_EMPTY)) {
829 if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
830 ((pRbd->dataLength - 4) > 14)) {
945af8d7 831
77846748
WD		 832 /*
833 * Get buffer address and size
834 */
835 frame = (NBUF *)pRbd->dataPointer;
836 frame_length = pRbd->dataLength - 4;
837
838#if (DEBUG & 0x20)
839 {
840 int i;
841 printf("recv data hdr:");
842 for (i = 0; i < 14; i++)
843 printf("%x ", *(frame->head + i));
844 printf("\n");
845 }
945af8d7 846#endif
77846748
WD		 847 /*
848 * Fill the buffer and pass it to upper layers
849 */
850 memcpy(buff, frame->head, 14);
851 memcpy(buff + 14, frame->data, frame_length);
852 NetReceive(buff, frame_length);
853 len = frame_length;
854 }
855 /*
856 * Reset buffer descriptor as empty
857 */
858 mpc5xxx_fec_rbd_clean(fec, pRbd);
945af8d7 859 }
77846748
WD		 860 SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
861 return len;
945af8d7
WD		 862}
863
864
865/********************************************************************/
866int mpc5xxx_fec_initialize(bd_t * bis)
867{
868 mpc5xxx_fec_priv *fec;
869 struct eth_device *dev;
12f34241
WD		 870 char *tmp, *end;
871 char env_enetaddr[6];
872 int i;
945af8d7
WD		 873
874 fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
875 dev = (struct eth_device *)malloc(sizeof(*dev));
12f34241 876 memset(dev, 0, sizeof *dev);
945af8d7
WD		 877
878 fec->eth = (ethernet_regs *)MPC5XXX_FEC;
879 fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
880 fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
a87589da
WD		 881#if defined(CONFIG_CANMB) || defined(CONFIG_HMI1001) || \
882 defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \
883 defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \
f1340e22 884 defined(CONFIG_TQM5200) || defined(CONFIG_O2DNT)
efa329cb 885# ifndef CONFIG_FEC_10MBIT
945af8d7 886 fec->xcv_type = MII100;
efa329cb 887# else
a57106fc 888 fec->xcv_type = MII10;
efa329cb 889# endif
6c7a1408
WD		 890#elif defined(CONFIG_TOTAL5200)
891 fec->xcv_type = SEVENWIRE;
a57106fc
WD		 892#else
893#error fec->xcv_type not initialized.
945af8d7
WD		 894#endif
895
896 dev->priv = (void *)fec;
897 dev->iobase = MPC5XXX_FEC;
898 dev->init = mpc5xxx_fec_init;
899 dev->halt = mpc5xxx_fec_halt;
900 dev->send = mpc5xxx_fec_send;
901 dev->recv = mpc5xxx_fec_recv;
902
77846748 903 sprintf(dev->name, "FEC ETHERNET");
945af8d7
WD		 904 eth_register(dev);
905
63ff004c
MB		 906#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
907 miiphy_register (dev->name,
908 fec5xxx_miiphy_read, fec5xxx_miiphy_write);
909#endif
910
12f34241
WD		 911 /*
912 * Try to set the mac address now. The fec mac address is
42d1f039 913 * a garbage after reset. When not using fec for booting
12f34241
WD		 914 * the Linux fec driver will try to work with this garbage.
915 */
916 tmp = getenv("ethaddr");
917 if (tmp) {
918 for (i=0; i<6; i++) {
919 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
920 if (tmp)
921 tmp = (*end) ? end+1 : end;
922 }
923 mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
924 }
925
6c1362cf 926 mpc5xxx_fec_init_phy(dev, bis);
63ff004c 927
945af8d7
WD		 928 return 1;
929}
930
931/* MII-interface related functions */
932/********************************************************************/
63ff004c 933int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
945af8d7
WD		 934{
935 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
936 uint32 reg; /* convenient holder for the PHY register */
937 uint32 phy; /* convenient holder for the PHY */
938 int timeout = 0xffff;
939
940 /*
941 * reading from any PHY's register is done by properly
942 * programming the FEC's MII data register.
943 */
944 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
945 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
946
947 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
948
949 /*
950 * wait for the related interrupt
951 */
952 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
953
954 if (timeout == 0) {
955#if (DEBUG & 0x2)
956 printf ("Read MDIO failed...\n");
957#endif
958 return -1;
959 }
960
961 /*
962 * clear mii interrupt bit
963 */
964 eth->ievent = 0x00800000;
965
966 /*
967 * it's now safe to read the PHY's register
968 */
969 *retVal = (uint16) eth->mii_data;
970
971 return 0;
972}
973
974/********************************************************************/
63ff004c 975int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
945af8d7
WD		 976{
977 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
978 uint32 reg; /* convenient holder for the PHY register */
979 uint32 phy; /* convenient holder for the PHY */
980 int timeout = 0xffff;
981
982 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
983 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
984
985 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
986 FEC_MII_DATA_TA | phy | reg | data);
987
988 /*
989 * wait for the MII interrupt
990 */
991 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
992
993 if (timeout == 0) {
994#if (DEBUG & 0x2)
995 printf ("Write MDIO failed...\n");
996#endif
997 return -1;
998 }
999
1000 /*
1001 * clear MII interrupt bit
1002 */
1003 eth->ievent = 0x00800000;
1004
1005 return 0;
1006}
1007
1008#if (DEBUG & 0x40)
1009static uint32 local_crc32(char *string, unsigned int crc_value, int len)
1010{
1011 int i;
1012 char c;
1013 unsigned int crc, count;
1014
1015 /*
1016 * crc32 algorithm
1017 */
1018 /*
1019 * crc = 0xffffffff; * The initialized value should be 0xffffffff
1020 */
1021 crc = crc_value;
1022
1023 for (i = len; --i >= 0;) {
1024 c = *string++;
1025 for (count = 0; count < 8; count++) {
1026 if ((c & 0x01) ^ (crc & 0x01)) {
1027 crc >>= 1;
1028 crc = crc ^ 0xedb88320;
1029 } else {
1030 crc >>= 1;
1031 }
1032 c >>= 1;
1033 }
1034 }
1035
1036 /*
1037 * In big endian system, do byte swaping for crc value
1038 */
1039 /**/ return crc;
1040}
1041#endif /* DEBUG */
1042
cbd8a35c 1043#endif /* CONFIG_MPC5xxx_FEC */
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