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96e48cf6 WD |
1 | /* |
2 | * (C) Copyright 2000-2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | ||
26 | #if defined(CONFIG_PCI) && defined(CONFIG_MPC5200) | |
27 | ||
28 | #include <asm/processor.h> | |
29 | #include <asm/io.h> | |
30 | #include <pci.h> | |
31 | #include <mpc5xxx.h> | |
32 | ||
33 | /* System RAM mapped over PCI */ | |
6d0f6bcf JCPV |
34 | #define CONFIG_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE |
35 | #define CONFIG_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE | |
96e48cf6 WD |
36 | #define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024) |
37 | ||
38 | /* PCIIWCR bit fields */ | |
39 | #define IWCR_MEM (0 << 3) | |
40 | #define IWCR_IO (1 << 3) | |
41 | #define IWCR_READ (0 << 1) | |
42 | #define IWCR_READLINE (1 << 1) | |
43 | #define IWCR_READMULT (2 << 1) | |
44 | #define IWCR_EN (1 << 0) | |
45 | ||
46 | static int mpc5200_read_config_dword(struct pci_controller *hose, | |
47 | pci_dev_t dev, int offset, u32* value) | |
48 | { | |
49 | *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset; | |
50 | eieio(); | |
35656de7 | 51 | udelay(10); |
5e4b3361 SR |
52 | #if (defined CONFIG_PF5200 || defined CONFIG_CPCI5200) |
53 | if (dev & 0x00ff0000) { | |
54 | u32 val; | |
55 | val = in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+2)); | |
56 | udelay(10); | |
57 | val = val << 16; | |
58 | val |= in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+0)); | |
59 | *value = val; | |
60 | } else { | |
61 | *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS); | |
62 | } | |
63 | udelay(10); | |
64 | #else | |
96e48cf6 | 65 | *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS); |
5e4b3361 | 66 | #endif |
96e48cf6 WD |
67 | eieio(); |
68 | *(volatile u32 *)MPC5XXX_PCI_CAR = 0; | |
35656de7 | 69 | udelay(10); |
96e48cf6 WD |
70 | return 0; |
71 | } | |
72 | ||
73 | static int mpc5200_write_config_dword(struct pci_controller *hose, | |
74 | pci_dev_t dev, int offset, u32 value) | |
75 | { | |
76 | *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset; | |
77 | eieio(); | |
35656de7 | 78 | udelay(10); |
96e48cf6 WD |
79 | out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value); |
80 | eieio(); | |
81 | *(volatile u32 *)MPC5XXX_PCI_CAR = 0; | |
35656de7 | 82 | udelay(10); |
96e48cf6 WD |
83 | return 0; |
84 | } | |
85 | ||
86 | void pci_mpc5xxx_init (struct pci_controller *hose) | |
87 | { | |
88 | hose->first_busno = 0; | |
89 | hose->last_busno = 0xff; | |
90 | ||
91 | /* System space */ | |
92 | pci_set_region(hose->regions + 0, | |
93 | CONFIG_PCI_MEMORY_BUS, | |
94 | CONFIG_PCI_MEMORY_PHYS, | |
95 | CONFIG_PCI_MEMORY_SIZE, | |
96 | PCI_REGION_MEM | PCI_REGION_MEMORY); | |
97 | ||
98 | /* PCI memory space */ | |
99 | pci_set_region(hose->regions + 1, | |
100 | CONFIG_PCI_MEM_BUS, | |
101 | CONFIG_PCI_MEM_PHYS, | |
102 | CONFIG_PCI_MEM_SIZE, | |
103 | PCI_REGION_MEM); | |
104 | ||
105 | /* PCI IO space */ | |
106 | pci_set_region(hose->regions + 2, | |
107 | CONFIG_PCI_IO_BUS, | |
108 | CONFIG_PCI_IO_PHYS, | |
109 | CONFIG_PCI_IO_SIZE, | |
110 | PCI_REGION_IO); | |
111 | ||
112 | hose->region_count = 3; | |
113 | ||
114 | pci_register_hose(hose); | |
115 | ||
116 | /* GPIO Multiplexing - enable PCI */ | |
117 | *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15); | |
42d1f039 | 118 | |
96e48cf6 WD |
119 | /* Set host bridge as pci master and enable memory decoding */ |
120 | *(vu_long *)MPC5XXX_PCI_CMD |= | |
121 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; | |
42d1f039 | 122 | |
96e48cf6 WD |
123 | /* Set maximum latency timer */ |
124 | *(vu_long *)MPC5XXX_PCI_CFG |= (0xf800); | |
125 | ||
126 | /* Set cache line size */ | |
127 | *(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) | | |
6d0f6bcf | 128 | (CONFIG_SYS_CACHELINE_SIZE / 4); |
42d1f039 | 129 | |
96e48cf6 | 130 | /* Map MBAR to PCI space */ |
6d0f6bcf JCPV |
131 | *(vu_long *)MPC5XXX_PCI_BAR0 = CONFIG_SYS_MBAR; |
132 | *(vu_long *)MPC5XXX_PCI_TBATR0 = CONFIG_SYS_MBAR | 1; | |
42d1f039 | 133 | |
96e48cf6 WD |
134 | /* Map RAM to PCI space */ |
135 | *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3); | |
136 | *(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1; | |
137 | ||
96e48cf6 WD |
138 | /* Park XLB on PCI */ |
139 | *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5)); | |
140 | *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5); | |
141 | ||
96e48cf6 WD |
142 | /* Disable interrupts from PCI controller */ |
143 | *(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12); | |
a9e642e2 WD |
144 | *(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24); |
145 | ||
146 | /* Set PCI retry counter to 0 = infinite retry. */ | |
147 | /* The default of 255 is too short for slow devices. */ | |
148 | *(vu_long *)MPC5XXX_PCI_ICR &= 0xFFFFFF00; | |
42d1f039 | 149 | |
96e48cf6 WD |
150 | /* Disable initiator windows */ |
151 | *(vu_long *)MPC5XXX_PCI_IWCR = 0; | |
42d1f039 | 152 | |
96e48cf6 WD |
153 | /* Map PCI memory to physical space */ |
154 | *(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS | | |
155 | (((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) | | |
156 | (CONFIG_PCI_MEM_BUS >> 16); | |
157 | *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_MEM | IWCR_READ | IWCR_EN) << 24; | |
158 | ||
159 | /* Map PCI I/O to physical space */ | |
160 | *(vu_long *)MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS | | |
161 | (((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) | | |
162 | (CONFIG_PCI_IO_BUS >> 16); | |
163 | *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_IO | IWCR_READ | IWCR_EN) << 16; | |
164 | ||
165 | /* Reset the PCI bus */ | |
166 | *(vu_long *)MPC5XXX_PCI_GSCR |= 1; | |
167 | udelay(1000); | |
168 | *(vu_long *)MPC5XXX_PCI_GSCR &= ~1; | |
169 | udelay(1000); | |
170 | ||
171 | pci_set_ops(hose, | |
172 | pci_hose_read_config_byte_via_dword, | |
173 | pci_hose_read_config_word_via_dword, | |
174 | mpc5200_read_config_dword, | |
175 | pci_hose_write_config_byte_via_dword, | |
176 | pci_hose_write_config_word_via_dword, | |
177 | mpc5200_write_config_dword); | |
42d1f039 | 178 | |
96e48cf6 WD |
179 | udelay(1000); |
180 | ||
181 | #ifdef CONFIG_PCI_SCAN_SHOW | |
182 | printf("PCI: Bus Dev VenId DevId Class Int\n"); | |
183 | #endif | |
184 | ||
185 | hose->last_busno = pci_hose_scan(hose); | |
186 | } | |
187 | #endif /* CONFIG_PCI && CONFIG_MPC5200 */ |