[people/ms/u-boot.git] / cpu / mpc824x / cpu_init.c

/*
 * (C) Copyright 2000
 * Rob Taylor. Flying Pig Systems. robt@flyingpig.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <mpc824x.h>

#ifndef CONFIG_SYS_BANK0_ROW
#define CONFIG_SYS_BANK0_ROW 0
#endif
#ifndef CONFIG_SYS_BANK1_ROW
#define CONFIG_SYS_BANK1_ROW 0
#endif
#ifndef CONFIG_SYS_BANK2_ROW
#define CONFIG_SYS_BANK2_ROW 0
#endif
#ifndef CONFIG_SYS_BANK3_ROW
#define CONFIG_SYS_BANK3_ROW 0
#endif
#ifndef CONFIG_SYS_BANK4_ROW
#define CONFIG_SYS_BANK4_ROW 0
#endif
#ifndef CONFIG_SYS_BANK5_ROW
#define CONFIG_SYS_BANK5_ROW 0
#endif
#ifndef CONFIG_SYS_BANK6_ROW
#define CONFIG_SYS_BANK6_ROW 0
#endif
#ifndef CONFIG_SYS_BANK7_ROW
#define CONFIG_SYS_BANK7_ROW 0
#endif
#ifndef CONFIG_SYS_DBUS_SIZE2
#define CONFIG_SYS_DBUS_SIZE2 0
#endif

/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 */
void
cpu_init_f (void)
{
/* MOUSSE board is initialized in asm */
#if !defined(CONFIG_MOUSSE) && !defined(CONFIG_BMW)
    register unsigned long val;
    CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
/*    CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/

#if defined(CONFIG_MUSENKI) || defined(CONFIG_PN62)
/* Why is this here, you ask?  Try, just try setting 0x8000
 * in PCIACR with CONFIG_WRITE_HALFWORD()
 * this one was a stumper, and we are annoyed
 */

#define M_CONFIG_WRITE_HALFWORD( addr, data ) \
	__asm__ __volatile__("		\
		stw  %2,0(%0)\n		\
		sync\n			\
		sth  %3,2(%1)\n		\
		sync\n			\
		"			\
		: /* no output */	\
		: "r" (CONFIG_ADDR), "r" (CONFIG_DATA),			\
		"r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16))	\
	);

	M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000);
#endif

	CONFIG_WRITE_BYTE(PCLSR, 0x8);	/* set PCI cache line size */
	CONFIG_WRITE_BYTE (PLTR, 0x40); /* set PCI latency timer */
	/*
	* Note that although this bit is cleared after a hard reset, it
	* must be explicitly set and then cleared by software during
	* initialization in order to guarantee correct operation of the
	* DLL and the SDRAM_CLK[0:3] signals (if they are used).
	*/
	CONFIG_READ_BYTE (AMBOR, val);
	CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
	CONFIG_WRITE_BYTE(AMBOR, val | 0x20);
	CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
#ifdef CONFIG_MPC8245
	/* silicon bug 28 MPC8245 */
	CONFIG_READ_BYTE(AMBOR,val);
	CONFIG_WRITE_BYTE(AMBOR,val|0x1);

#if 0
	/*
	 * The following bug only affects older (XPC8245) processors.
	 * DMA transfers initiated by external devices get corrupted due
	 * to a hardware scheduling problem.
	 *
	 * The effect is:
	 * when transferring X words, the first 32 words are transferred
	 * OK, the next 3 x 32 words are 'old' data (from previous DMA)
	 * while the rest of the X words is xferred fine.
	 *
	 * Disabling 3 of the 4 32 word hardware buffers solves the problem
	 * with no significant performance loss.
	 */

	CONFIG_READ_BYTE(PCMBCR,val);
	/* in order not to corrupt data which is being read over the PCI bus
	* with the PPC as slave, we need to reduce the number of PCMRBs to 1,
	* 4.11 in the  processor user manual
	* */

#if 1
	CONFIG_WRITE_BYTE(PCMBCR,(val|0xC0)); /* 1 PCMRB */
#else
	CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */
	CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */
	/* default, 4 PCMRBs are used */
#endif
#endif
#endif

	CONFIG_READ_WORD(PICR1, val);
#if defined(CONFIG_MPC8240)
	CONFIG_WRITE_WORD( PICR1,
		(val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) |
		       PIRC1_MSK | PICR1_PROC_TYPE_603E |
		       PICR1_FLASH_WR_EN | PICR1_MCP_EN |
		       PICR1_CF_DPARK | PICR1_EN_PCS |
		       PICR1_CF_APARK );
#elif defined(CONFIG_MPC8245)
	CONFIG_WRITE_WORD( PICR1,
		(val & (PICR1_RCS0)) |
		       PICR1_PROC_TYPE_603E |
		       PICR1_FLASH_WR_EN | PICR1_MCP_EN |
		       PICR1_CF_DPARK | PICR1_NO_BUSW_CK |
		       PICR1_DEC| PICR1_CF_APARK | 0x10); /* 8245 UM says bit 4 must be set */
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif

	CONFIG_READ_WORD(PICR2, val);
	val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/
#ifndef CONFIG_PN62
	val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/
#endif
	CONFIG_WRITE_WORD(PICR2, val);

	CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR);
#ifndef CONFIG_SYS_RAMBOOT
	CONFIG_WRITE_WORD(MCCR1, (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) |
				 (CONFIG_SYS_BANK0_ROW) |
				 (CONFIG_SYS_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) |
				 (CONFIG_SYS_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) |
				 (CONFIG_SYS_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) |
				 (CONFIG_SYS_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) |
				 (CONFIG_SYS_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) |
				 (CONFIG_SYS_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) |
				 (CONFIG_SYS_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) |
				 (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT));
#endif

#if defined(CONFIG_SYS_ASRISE) && defined(CONFIG_SYS_ASFALL)
	CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT |
				 CONFIG_SYS_ASRISE << MCCR2_ASRISE_SHIFT |
				 CONFIG_SYS_ASFALL << MCCR2_ASFALL_SHIFT);
#else
	CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT);
#endif

#if defined(CONFIG_MPC8240)
	CONFIG_WRITE_WORD(MCCR3,
		(((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
		(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) |
		(CONFIG_SYS_RDLAT  << MCCR3_RDLAT_SHIFT));
#elif defined(CONFIG_MPC8245)
	CONFIG_WRITE_WORD(MCCR3,
		(((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
		(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT));
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif

/* this is gross.  We think these should all be the same, and various boards
 *  should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if
 *  its not set, we define it to zero in this file
 */
#if defined(CONFIG_CU824) || defined(CONFIG_PN62)
	CONFIG_WRITE_WORD(MCCR4,
	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
	MCCR4_BIT21 |
	(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
	((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
	(((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
		  CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) |
	(CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) |
	(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT));
#elif defined(CONFIG_MPC8240)
	CONFIG_WRITE_WORD(MCCR4,
	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
	MCCR4_BIT21 |
	(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
	((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
	(((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
		  (CONFIG_SYS_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) |
	(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
#elif defined(CONFIG_MPC8245)
	CONFIG_READ_WORD(MCCR1, val);
	val &= MCCR1_DBUS_SIZE0;    /* test for 64-bit mem bus */

	CONFIG_WRITE_WORD(MCCR4,
		(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
		(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
		(CONFIG_SYS_EXTROM ? MCCR4_EXTROM : 0) |
		(CONFIG_SYS_REGDIMM ? MCCR4_REGDIMM : 0) |
		(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
		((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
		(CONFIG_SYS_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) |
		(((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
		      (val ? 2 : 3)) << MCCR4_SDMODE_SHIFT)  |
		(CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) |
		(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif

	CONFIG_WRITE_WORD(MSAR1,
		( (CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
		(((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(EMSAR1,
		( (CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
		(((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(MSAR2,
		( (CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
		(((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(EMSAR2,
		( (CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
		(((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(MEAR1,
		( (CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
		(((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(EMEAR1,
		( (CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
		(((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(MEAR2,
		( (CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
		(((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(EMEAR2,
		( (CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
		(((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));

	CONFIG_WRITE_BYTE(ODCR, CONFIG_SYS_ODCR);
#ifdef CONFIG_SYS_DLL_MAX_DELAY
	CONFIG_WRITE_BYTE(MIOCR1, CONFIG_SYS_DLL_MAX_DELAY);	/* needed to make DLL lock */
#endif
#if defined(CONFIG_SYS_DLL_EXTEND) && defined(CONFIG_SYS_PCI_HOLD_DEL)
	CONFIG_WRITE_BYTE(PMCR2, CONFIG_SYS_DLL_EXTEND | CONFIG_SYS_PCI_HOLD_DEL);
#endif
#if defined(MIOCR2) && defined(CONFIG_SYS_SDRAM_DSCD)
	CONFIG_WRITE_BYTE(MIOCR2, CONFIG_SYS_SDRAM_DSCD);	/* change memory input */
#endif /* setup & hold time */

	CONFIG_WRITE_BYTE(MBER,
		 CONFIG_SYS_BANK0_ENABLE |
		(CONFIG_SYS_BANK1_ENABLE << 1) |
		(CONFIG_SYS_BANK2_ENABLE << 2) |
		(CONFIG_SYS_BANK3_ENABLE << 3) |
		(CONFIG_SYS_BANK4_ENABLE << 4) |
		(CONFIG_SYS_BANK5_ENABLE << 5) |
		(CONFIG_SYS_BANK6_ENABLE << 6) |
		(CONFIG_SYS_BANK7_ENABLE << 7));

#ifdef CONFIG_SYS_PGMAX
	CONFIG_WRITE_BYTE(MPMR, CONFIG_SYS_PGMAX);
#endif

	/* ! Wait 200us before initialize other registers */
	/*FIXME: write a decent udelay wait */
	__asm__ __volatile__(
		" mtctr	%0 \n \
		0: bdnz	 0b\n"
		:
		: "r" (0x10000));

	CONFIG_READ_WORD(MCCR1, val);
	CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */
	__asm__ __volatile__("eieio");

#endif /* !CONFIG_MOUSSE && !CONFIG_BMW */
}


#ifdef CONFIG_MOUSSE
#ifdef INCLUDE_MPC107_REPORT
struct MPC107_s {
	unsigned int iobase;
	char desc[120];
} MPC107Regs[] = {
	{ BMC_BASE +  0x00, "MPC107 Vendor/Device ID"		},
	{ BMC_BASE +  0x04, "MPC107 PCI Command/Status Register" },
	{ BMC_BASE +  0x08, "MPC107 Revision"			},
	{ BMC_BASE +  0x0C, "MPC107 Cache Line Size"		},
	{ BMC_BASE +  0x10, "MPC107 LMBAR"			},
	{ BMC_BASE +  0x14, "MPC824x PCSR"			},
	{ BMC_BASE +  0xA8, "MPC824x PICR1"			},
	{ BMC_BASE +  0xAC, "MPC824x PICR2"			},
	{ BMC_BASE +  0x46, "MPC824x PACR"			},
	{ BMC_BASE + 0x310, "MPC824x ITWR"			},
	{ BMC_BASE + 0x300, "MPC824x OMBAR"			},
	{ BMC_BASE + 0x308, "MPC824x OTWR"			},
	{ BMC_BASE +  0x14, "MPC107 Peripheral Control and Status Register" },
	{ BMC_BASE + 0x78, "MPC107 EUMBAR"			},
	{ BMC_BASE + 0xC0, "MPC107 Processor Bus Error Status"	},
	{ BMC_BASE + 0xC4, "MPC107 PCI Bus Error Status"	},
	{ BMC_BASE + 0xC8, "MPC107 Processor/PCI Error Address"	},
	{ BMC_BASE + 0xE0, "MPC107 AMBOR Register"		},
	{ BMC_BASE + 0xF0, "MPC107 MCCR1 Register"		},
	{ BMC_BASE + 0xF4, "MPC107 MCCR2 Register"		},
	{ BMC_BASE + 0xF8, "MPC107 MCCR3 Register"		},
	{ BMC_BASE + 0xFC, "MPC107 MCCR4 Register"		},
};
#define N_MPC107_Regs	(sizeof(MPC107Regs)/sizeof(MPC107Regs[0]))
#endif /* INCLUDE_MPC107_REPORT */
#endif /* CONFIG_MOUSSE */

/*
 * initialize higher level parts of CPU like time base and timers
 */
int cpu_init_r (void)
{
#ifdef CONFIG_MOUSSE
#ifdef INCLUDE_MPC107_REPORT
	unsigned int tmp = 0, i;
#endif
	/*
	 * Initialize the EUMBBAR (Embedded Util Mem Block Base Addr Reg).
	 * This is necessary before the EPIC, DMA ctlr, I2C ctlr, etc. can
	 * be accessed.
	 */

#ifdef CONFIG_MPC8240			/* only on MPC8240 */
	mpc824x_mpc107_setreg (EUMBBAR, EUMBBAR_VAL);
	/* MOT/SPS: Issue #10002, PCI (FD Alias enable) */
	mpc824x_mpc107_setreg (AMBOR, 0x000000C0);
#endif


#ifdef INCLUDE_MPC107_REPORT
	/* Check MPC824x PCI Device and Vendor ID */
	while ((tmp = mpc824x_mpc107_getreg (BMC_BASE)) != 0x31057) {
		printf ("	MPC107: offset=0x%x, val = 0x%x\n",
			BMC_BASE,
			tmp);
	}

	for (i = 0; i < N_MPC107_Regs; i++) {
		printf ("	0x%x/%s = 0x%x\n",
			MPC107Regs[i].iobase,
			MPC107Regs[i].desc,
			mpc824x_mpc107_getreg (MPC107Regs[i].iobase));
	}

	printf ("IBAT0L = 0x%08X\n", mfspr (IBAT0L));
	printf ("IBAT0U = 0x%08X\n", mfspr (IBAT0U));
	printf ("IBAT1L = 0x%08X\n", mfspr (IBAT1L));
	printf ("IBAT1U = 0x%08X\n", mfspr (IBAT1U));
	printf ("IBAT2L = 0x%08X\n", mfspr (IBAT2L));
	printf ("IBAT2U = 0x%08X\n", mfspr (IBAT2U));
	printf ("IBAT3L = 0x%08X\n", mfspr (IBAT3L));
	printf ("IBAT3U = 0x%08X\n", mfspr (IBAT3U));
	printf ("DBAT0L = 0x%08X\n", mfspr (DBAT0L));
	printf ("DBAT0U = 0x%08X\n", mfspr (DBAT0U));
	printf ("DBAT1L = 0x%08X\n", mfspr (DBAT1L));
	printf ("DBAT1U = 0x%08X\n", mfspr (DBAT1U));
	printf ("DBAT2L = 0x%08X\n", mfspr (DBAT2L));
	printf ("DBAT2U = 0x%08X\n", mfspr (DBAT2U));
	printf ("DBAT3L = 0x%08X\n", mfspr (DBAT3L));
	printf ("DBAT3U = 0x%08X\n", mfspr (DBAT3U));
#endif /* INCLUDE_MPC107_REPORT */
#endif /* CONFIG_MOUSSE */
	return (0);
}
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2000
	3	* Rob Taylor. Flying Pig Systems. robt@flyingpig.com.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <asm/processor.h>
	26	#include <mpc824x.h>
	27
6d0f6bcf JCPV	28	#ifndef CONFIG_SYS_BANK0_ROW
6d0f6bcf JCPV	29	#define CONFIG_SYS_BANK0_ROW 0
c609719b	30	#endif
6d0f6bcf JCPV	31	#ifndef CONFIG_SYS_BANK1_ROW
6d0f6bcf JCPV	32	#define CONFIG_SYS_BANK1_ROW 0
c609719b	33	#endif
6d0f6bcf JCPV	34	#ifndef CONFIG_SYS_BANK2_ROW
6d0f6bcf JCPV	35	#define CONFIG_SYS_BANK2_ROW 0
c609719b	36	#endif
6d0f6bcf JCPV	37	#ifndef CONFIG_SYS_BANK3_ROW
6d0f6bcf JCPV	38	#define CONFIG_SYS_BANK3_ROW 0
c609719b	39	#endif
6d0f6bcf JCPV	40	#ifndef CONFIG_SYS_BANK4_ROW
6d0f6bcf JCPV	41	#define CONFIG_SYS_BANK4_ROW 0
c609719b	42	#endif
6d0f6bcf JCPV	43	#ifndef CONFIG_SYS_BANK5_ROW
6d0f6bcf JCPV	44	#define CONFIG_SYS_BANK5_ROW 0
c609719b	45	#endif
6d0f6bcf JCPV	46	#ifndef CONFIG_SYS_BANK6_ROW
6d0f6bcf JCPV	47	#define CONFIG_SYS_BANK6_ROW 0
c609719b	48	#endif
6d0f6bcf JCPV	49	#ifndef CONFIG_SYS_BANK7_ROW
6d0f6bcf JCPV	50	#define CONFIG_SYS_BANK7_ROW 0
c609719b	51	#endif
6d0f6bcf JCPV	52	#ifndef CONFIG_SYS_DBUS_SIZE2
6d0f6bcf JCPV	53	#define CONFIG_SYS_DBUS_SIZE2 0
c609719b WD	54	#endif
	55
	56	/*
	57	* Breath some life into the CPU...
	58	*
	59	* Set up the memory map,
	60	* initialize a bunch of registers,
	61	*/
	62	void
	63	cpu_init_f (void)
	64	{
	65	/* MOUSSE board is initialized in asm */
	66	#if !defined(CONFIG_MOUSSE) && !defined(CONFIG_BMW)
	67	register unsigned long val;
	68	CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
	69	/* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); / /reset PCISR*/
	70
	71	#if defined(CONFIG_MUSENKI) \|\| defined(CONFIG_PN62)
	72	/* Why is this here, you ask? Try, just try setting 0x8000
	73	* in PCIACR with CONFIG_WRITE_HALFWORD()
	74	* this one was a stumper, and we are annoyed
	75	*/
	76
	77	#define M_CONFIG_WRITE_HALFWORD( addr, data ) \
39539887 WD	78	__asm__ __volatile__(" \
	79	stw %2,0(%0)\n \
	80	sync\n \
	81	sth %3,2(%1)\n \
	82	sync\n \
	83	" \
	84	: /* no output */ \
	85	: "r" (CONFIG_ADDR), "r" (CONFIG_DATA), \
	86	"r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16)) \
	87	);
c609719b	88
39539887	89	M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000);
c609719b WD	90	#endif
c609719b WD	91
39539887	92	CONFIG_WRITE_BYTE(PCLSR, 0x8); /* set PCI cache line size */
30ce5ab0	93	CONFIG_WRITE_BYTE (PLTR, 0x40); /* set PCI latency timer */
39539887 WD	94	/*
	95	* Note that although this bit is cleared after a hard reset, it
	96	* must be explicitly set and then cleared by software during
	97	* initialization in order to guarantee correct operation of the
	98	* DLL and the SDRAM_CLK[0:3] signals (if they are used).
	99	*/
	100	CONFIG_READ_BYTE (AMBOR, val);
	101	CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
	102	CONFIG_WRITE_BYTE(AMBOR, val \| 0x20);
	103	CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
	104	#ifdef CONFIG_MPC8245
	105	/* silicon bug 28 MPC8245 */
	106	CONFIG_READ_BYTE(AMBOR,val);
	107	CONFIG_WRITE_BYTE(AMBOR,val\|0x1);
	108
8b0bfc68 WD	109	#if 0
	110	/*
	111	* The following bug only affects older (XPC8245) processors.
	112	* DMA transfers initiated by external devices get corrupted due
	113	* to a hardware scheduling problem.
	114	*
	115	* The effect is:
	116	* when transferring X words, the first 32 words are transferred
	117	* OK, the next 3 x 32 words are 'old' data (from previous DMA)
	118	* while the rest of the X words is xferred fine.
	119	*
	120	* Disabling 3 of the 4 32 word hardware buffers solves the problem
	121	* with no significant performance loss.
	122	*/
	123
39539887 WD	124	CONFIG_READ_BYTE(PCMBCR,val);
39539887 WD	125	/* in order not to corrupt data which is being read over the PCI bus
281e00a3	126	* with the PPC as slave, we need to reduce the number of PCMRBs to 1,
39539887 WD	127	* 4.11 in the processor user manual
39539887 WD	128	* */
c609719b	129
39539887 WD	130	#if 1
	131	CONFIG_WRITE_BYTE(PCMBCR,(val\|0xC0)); /* 1 PCMRB */
	132	#else
	133	CONFIG_WRITE_BYTE(PCMBCR,(val\|0x80)); /* 2 PCMRBs */
	134	CONFIG_WRITE_BYTE(PCMBCR,(val\|0x40)); /* 3 PCMRBs */
8b0bfc68 WD	135	/* default, 4 PCMRBs are used */
8b0bfc68 WD	136	#endif
39539887 WD	137	#endif
	138	#endif
	139
	140	CONFIG_READ_WORD(PICR1, val);
c609719b	141	#if defined(CONFIG_MPC8240)
39539887 WD	142	CONFIG_WRITE_WORD( PICR1,
	143	(val & (PICR1_ADDRESS_MAP \| PICR1_RCS0)) \|
	144	PIRC1_MSK \| PICR1_PROC_TYPE_603E \|
	145	PICR1_FLASH_WR_EN \| PICR1_MCP_EN \|
	146	PICR1_CF_DPARK \| PICR1_EN_PCS \|
	147	PICR1_CF_APARK );
c609719b	148	#elif defined(CONFIG_MPC8245)
39539887 WD	149	CONFIG_WRITE_WORD( PICR1,
	150	(val & (PICR1_RCS0)) \|
	151	PICR1_PROC_TYPE_603E \|
	152	PICR1_FLASH_WR_EN \| PICR1_MCP_EN \|
	153	PICR1_CF_DPARK \| PICR1_NO_BUSW_CK \|
	154	PICR1_DEC\| PICR1_CF_APARK \| 0x10); /* 8245 UM says bit 4 must be set */
c609719b WD	155	#else
	156	#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
	157	#endif
	158
39539887 WD	159	CONFIG_READ_WORD(PICR2, val);
39539887 WD	160	val= val & ~ (PICR2_CF_SNOOP_WS_MASK \| PICR2_CF_APHASE_WS_MASK); /mask off waitstate bits/
c609719b	161	#ifndef CONFIG_PN62
39539887	162	val \|= PICR2_CF_SNOOP_WS_1WS \| PICR2_CF_APHASE_WS_1WS; /1 wait state/
c609719b	163	#endif
39539887	164	CONFIG_WRITE_WORD(PICR2, val);
c609719b	165
6d0f6bcf JCPV	166	CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR);
	167	#ifndef CONFIG_SYS_RAMBOOT
	168	CONFIG_WRITE_WORD(MCCR1, (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) \|
	169	(CONFIG_SYS_BANK0_ROW) \|
	170	(CONFIG_SYS_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) \|
	171	(CONFIG_SYS_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) \|
	172	(CONFIG_SYS_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) \|
	173	(CONFIG_SYS_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) \|
	174	(CONFIG_SYS_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) \|
	175	(CONFIG_SYS_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) \|
	176	(CONFIG_SYS_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) \|
	177	(CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT));
c609719b WD	178	#endif
c609719b WD	179
6d0f6bcf JCPV	180	#if defined(CONFIG_SYS_ASRISE) && defined(CONFIG_SYS_ASFALL)
	181	CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT \|
	182	CONFIG_SYS_ASRISE << MCCR2_ASRISE_SHIFT \|
	183	CONFIG_SYS_ASFALL << MCCR2_ASFALL_SHIFT);
c609719b	184	#else
6d0f6bcf	185	CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT);
c609719b WD	186	#endif
	187
	188	#if defined(CONFIG_MPC8240)
39539887	189	CONFIG_WRITE_WORD(MCCR3,
6d0f6bcf JCPV	190	(((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) \|
	191	(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) \|
	192	(CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT));
c609719b	193	#elif defined(CONFIG_MPC8245)
39539887	194	CONFIG_WRITE_WORD(MCCR3,
6d0f6bcf JCPV	195	(((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) \|
6d0f6bcf JCPV	196	(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT));
c609719b WD	197	#else
	198	#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
	199	#endif
	200
	201	/* this is gross. We think these should all be the same, and various boards
6d0f6bcf	202	* should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if
c609719b WD	203	* its not set, we define it to zero in this file
	204	*/
	205	#if defined(CONFIG_CU824) \|\| defined(CONFIG_PN62)
	206	CONFIG_WRITE_WORD(MCCR4,
6d0f6bcf JCPV	207	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) \|
6d0f6bcf JCPV	208	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) \|
c609719b	209	MCCR4_BIT21 \|
6d0f6bcf JCPV	210	(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) \|
	211	((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) \|
	212	(((CONFIG_SYS_SDMODE_CAS_LAT <<4) \| (CONFIG_SYS_SDMODE_WRAP <<3) \|
	213	CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) \|
	214	(CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) \|
	215	(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT));
c609719b WD	216	#elif defined(CONFIG_MPC8240)
c609719b WD	217	CONFIG_WRITE_WORD(MCCR4,
6d0f6bcf JCPV	218	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) \|
6d0f6bcf JCPV	219	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) \|
c609719b	220	MCCR4_BIT21 \|
6d0f6bcf JCPV	221	(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) \|
	222	((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) \|
	223	(((CONFIG_SYS_SDMODE_CAS_LAT <<4) \| (CONFIG_SYS_SDMODE_WRAP <<3) \|
	224	(CONFIG_SYS_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) \|
	225	(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
c609719b	226	#elif defined(CONFIG_MPC8245)
39539887 WD	227	CONFIG_READ_WORD(MCCR1, val);
39539887 WD	228	val &= MCCR1_DBUS_SIZE0; /* test for 64-bit mem bus */
c609719b	229
39539887	230	CONFIG_WRITE_WORD(MCCR4,
6d0f6bcf JCPV	231	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) \|
	232	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) \|
	233	(CONFIG_SYS_EXTROM ? MCCR4_EXTROM : 0) \|
	234	(CONFIG_SYS_REGDIMM ? MCCR4_REGDIMM : 0) \|
	235	(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) \|
	236	((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) \|
	237	(CONFIG_SYS_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) \|
	238	(((CONFIG_SYS_SDMODE_CAS_LAT <<4) \| (CONFIG_SYS_SDMODE_WRAP <<3) \|
39539887	239	(val ? 2 : 3)) << MCCR4_SDMODE_SHIFT) \|
6d0f6bcf JCPV	240	(CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) \|
6d0f6bcf JCPV	241	(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
c609719b WD	242	#else
	243	#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
	244	#endif
	245
39539887	246	CONFIG_WRITE_WORD(MSAR1,
6d0f6bcf JCPV	247	( (CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) \|
	248	(((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) \|
	249	(((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) \|
	250	(((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
39539887	251	CONFIG_WRITE_WORD(EMSAR1,
6d0f6bcf JCPV	252	( (CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) \|
	253	(((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) \|
	254	(((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) \|
	255	(((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
39539887	256	CONFIG_WRITE_WORD(MSAR2,
6d0f6bcf JCPV	257	( (CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) \|
	258	(((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) \|
	259	(((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) \|
	260	(((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
39539887	261	CONFIG_WRITE_WORD(EMSAR2,
6d0f6bcf JCPV	262	( (CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) \|
	263	(((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) \|
	264	(((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) \|
	265	(((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
39539887	266	CONFIG_WRITE_WORD(MEAR1,
6d0f6bcf JCPV	267	( (CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) \|
	268	(((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) \|
	269	(((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) \|
	270	(((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
39539887	271	CONFIG_WRITE_WORD(EMEAR1,
6d0f6bcf JCPV	272	( (CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) \|
	273	(((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) \|
	274	(((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) \|
	275	(((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
39539887	276	CONFIG_WRITE_WORD(MEAR2,
6d0f6bcf JCPV	277	( (CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) \|
	278	(((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) \|
	279	(((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) \|
	280	(((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
39539887	281	CONFIG_WRITE_WORD(EMEAR2,
6d0f6bcf JCPV	282	( (CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) \|
	283	(((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) \|
	284	(((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) \|
	285	(((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
c609719b	286
6d0f6bcf JCPV	287	CONFIG_WRITE_BYTE(ODCR, CONFIG_SYS_ODCR);
	288	#ifdef CONFIG_SYS_DLL_MAX_DELAY
	289	CONFIG_WRITE_BYTE(MIOCR1, CONFIG_SYS_DLL_MAX_DELAY); /* needed to make DLL lock */
c609719b	290	#endif
6d0f6bcf JCPV	291	#if defined(CONFIG_SYS_DLL_EXTEND) && defined(CONFIG_SYS_PCI_HOLD_DEL)
6d0f6bcf JCPV	292	CONFIG_WRITE_BYTE(PMCR2, CONFIG_SYS_DLL_EXTEND \| CONFIG_SYS_PCI_HOLD_DEL);
c609719b	293	#endif
6d0f6bcf JCPV	294	#if defined(MIOCR2) && defined(CONFIG_SYS_SDRAM_DSCD)
6d0f6bcf JCPV	295	CONFIG_WRITE_BYTE(MIOCR2, CONFIG_SYS_SDRAM_DSCD); /* change memory input */
c609719b WD	296	#endif /* setup & hold time */
c609719b WD	297
39539887	298	CONFIG_WRITE_BYTE(MBER,
6d0f6bcf JCPV	299	CONFIG_SYS_BANK0_ENABLE \|
	300	(CONFIG_SYS_BANK1_ENABLE << 1) \|
	301	(CONFIG_SYS_BANK2_ENABLE << 2) \|
	302	(CONFIG_SYS_BANK3_ENABLE << 3) \|
	303	(CONFIG_SYS_BANK4_ENABLE << 4) \|
	304	(CONFIG_SYS_BANK5_ENABLE << 5) \|
	305	(CONFIG_SYS_BANK6_ENABLE << 6) \|
	306	(CONFIG_SYS_BANK7_ENABLE << 7));
c609719b	307
6d0f6bcf JCPV	308	#ifdef CONFIG_SYS_PGMAX
6d0f6bcf JCPV	309	CONFIG_WRITE_BYTE(MPMR, CONFIG_SYS_PGMAX);
c609719b WD	310	#endif
c609719b WD	311
39539887 WD	312	/* ! Wait 200us before initialize other registers */
	313	/FIXME: write a decent udelay wait /
	314	__asm__ __volatile__(
	315	" mtctr %0 \n \
	316	0: bdnz 0b\n"
	317	:
	318	: "r" (0x10000));
c609719b	319
39539887 WD	320	CONFIG_READ_WORD(MCCR1, val);
	321	CONFIG_WRITE_WORD(MCCR1, val \| MCCR1_MEMGO); /* set memory access going */
	322	__asm__ __volatile__("eieio");
c609719b WD	323
	324	#endif /* !CONFIG_MOUSSE && !CONFIG_BMW */
	325	}
	326
	327
	328	#ifdef CONFIG_MOUSSE
	329	#ifdef INCLUDE_MPC107_REPORT
39539887 WD	330	struct MPC107_s {
	331	unsigned int iobase;
	332	char desc[120];
	333	} MPC107Regs[] = {
	334	{ BMC_BASE + 0x00, "MPC107 Vendor/Device ID" },
	335	{ BMC_BASE + 0x04, "MPC107 PCI Command/Status Register" },
	336	{ BMC_BASE + 0x08, "MPC107 Revision" },
	337	{ BMC_BASE + 0x0C, "MPC107 Cache Line Size" },
	338	{ BMC_BASE + 0x10, "MPC107 LMBAR" },
	339	{ BMC_BASE + 0x14, "MPC824x PCSR" },
	340	{ BMC_BASE + 0xA8, "MPC824x PICR1" },
	341	{ BMC_BASE + 0xAC, "MPC824x PICR2" },
	342	{ BMC_BASE + 0x46, "MPC824x PACR" },
	343	{ BMC_BASE + 0x310, "MPC824x ITWR" },
	344	{ BMC_BASE + 0x300, "MPC824x OMBAR" },
	345	{ BMC_BASE + 0x308, "MPC824x OTWR" },
	346	{ BMC_BASE + 0x14, "MPC107 Peripheral Control and Status Register" },
	347	{ BMC_BASE + 0x78, "MPC107 EUMBAR" },
	348	{ BMC_BASE + 0xC0, "MPC107 Processor Bus Error Status" },
	349	{ BMC_BASE + 0xC4, "MPC107 PCI Bus Error Status" },
	350	{ BMC_BASE + 0xC8, "MPC107 Processor/PCI Error Address" },
	351	{ BMC_BASE + 0xE0, "MPC107 AMBOR Register" },
	352	{ BMC_BASE + 0xF0, "MPC107 MCCR1 Register" },
	353	{ BMC_BASE + 0xF4, "MPC107 MCCR2 Register" },
	354	{ BMC_BASE + 0xF8, "MPC107 MCCR3 Register" },
	355	{ BMC_BASE + 0xFC, "MPC107 MCCR4 Register" },
c609719b WD	356	};
	357	#define N_MPC107_Regs (sizeof(MPC107Regs)/sizeof(MPC107Regs[0]))
	358	#endif /* INCLUDE_MPC107_REPORT */
	359	#endif /* CONFIG_MOUSSE */
	360
	361	/*
	362	* initialize higher level parts of CPU like time base and timers
	363	*/
	364	int cpu_init_r (void)
	365	{
	366	#ifdef CONFIG_MOUSSE
	367	#ifdef INCLUDE_MPC107_REPORT
	368	unsigned int tmp = 0, i;
	369	#endif
	370	/*
	371	* Initialize the EUMBBAR (Embedded Util Mem Block Base Addr Reg).
	372	* This is necessary before the EPIC, DMA ctlr, I2C ctlr, etc. can
	373	* be accessed.
	374	*/
	375
	376	#ifdef CONFIG_MPC8240 /* only on MPC8240 */
	377	mpc824x_mpc107_setreg (EUMBBAR, EUMBBAR_VAL);
	378	/* MOT/SPS: Issue #10002, PCI (FD Alias enable) */
	379	mpc824x_mpc107_setreg (AMBOR, 0x000000C0);
	380	#endif
	381
	382
	383	#ifdef INCLUDE_MPC107_REPORT
	384	/* Check MPC824x PCI Device and Vendor ID */
	385	while ((tmp = mpc824x_mpc107_getreg (BMC_BASE)) != 0x31057) {
	386	printf (" MPC107: offset=0x%x, val = 0x%x\n",
	387	BMC_BASE,
	388	tmp);
	389	}
	390
	391	for (i = 0; i < N_MPC107_Regs; i++) {
	392	printf (" 0x%x/%s = 0x%x\n",
	393	MPC107Regs[i].iobase,
	394	MPC107Regs[i].desc,
	395	mpc824x_mpc107_getreg (MPC107Regs[i].iobase));
	396	}
	397
	398	printf ("IBAT0L = 0x%08X\n", mfspr (IBAT0L));
	399	printf ("IBAT0U = 0x%08X\n", mfspr (IBAT0U));
	400	printf ("IBAT1L = 0x%08X\n", mfspr (IBAT1L));
	401	printf ("IBAT1U = 0x%08X\n", mfspr (IBAT1U));
	402	printf ("IBAT2L = 0x%08X\n", mfspr (IBAT2L));
	403	printf ("IBAT2U = 0x%08X\n", mfspr (IBAT2U));
	404	printf ("IBAT3L = 0x%08X\n", mfspr (IBAT3L));
	405	printf ("IBAT3U = 0x%08X\n", mfspr (IBAT3U));
	406	printf ("DBAT0L = 0x%08X\n", mfspr (DBAT0L));
	407	printf ("DBAT0U = 0x%08X\n", mfspr (DBAT0U));
	408	printf ("DBAT1L = 0x%08X\n", mfspr (DBAT1L));
	409	printf ("DBAT1U = 0x%08X\n", mfspr (DBAT1U));
	410	printf ("DBAT2L = 0x%08X\n", mfspr (DBAT2L));
	411	printf ("DBAT2U = 0x%08X\n", mfspr (DBAT2U));
	412	printf ("DBAT3L = 0x%08X\n", mfspr (DBAT3L));
	413	printf ("DBAT3U = 0x%08X\n", mfspr (DBAT3U));
	414	#endif /* INCLUDE_MPC107_REPORT */
	415	#endif /* CONFIG_MOUSSE */
	416	return (0);
	417	}