[people/ms/u-boot.git] / cpu / mpc824x / start.S

/*
 *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
 *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/* U-Boot - Startup Code for PowerPC based Embedded Boards
 *
 *
 * The processor starts at 0x00000100 and the code is executed
 * from flash. The code is organized to be at an other address
 * in memory, but as long we don't jump around before relocating.
 * board_init lies at a quite high address and when the cpu has
 * jumped there, everything is ok.
 * This works because the cpu gives the FLASH (CS0) the whole
 * address space at startup, and board_init lies as a echo of
 * the flash somewhere up there in the memorymap.
 *
 * board_init will change CS0 to be positioned at the correct
 * address and (s)dram will be positioned at address 0
 */
#include <config.h>
#include <mpc824x.h>
#include <version.h>

#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <asm/cache.h>
#include <asm/mmu.h>

#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
#endif

/* We don't want the MMU yet.
*/
#undef	MSR_KERNEL
/* FP, Machine Check and Recoverable Interr. */
#define MSR_KERNEL ( MSR_FP | MSR_ME | MSR_RI )

/*
 * Set up GOT: Global Offset Table
 *
 * Use r14 to access the GOT
 */
	START_GOT
	GOT_ENTRY(_GOT2_TABLE_)
	GOT_ENTRY(_FIXUP_TABLE_)

	GOT_ENTRY(_start)
	GOT_ENTRY(_start_of_vectors)
	GOT_ENTRY(_end_of_vectors)
	GOT_ENTRY(transfer_to_handler)

	GOT_ENTRY(__init_end)
	GOT_ENTRY(_end)
	GOT_ENTRY(__bss_start)
#if defined(CONFIG_FADS)
	GOT_ENTRY(environment)
#endif
	END_GOT

/*
 * r3 - 1st arg to board_init(): IMMP pointer
 * r4 - 2nd arg to board_init(): boot flag
 */
	.text
	.long	0x27051956		/* U-Boot Magic Number			*/
	.globl	version_string
version_string:
	.ascii U_BOOT_VERSION
	.ascii " (", __DATE__, " - ", __TIME__, ")"
	.ascii CONFIG_IDENT_STRING, "\0"

	. = EXC_OFF_SYS_RESET
	.globl	_start
_start:
	li	r21, BOOTFLAG_COLD	/* Normal Power-On: Boot from FLASH	*/
	b	boot_cold

	. = EXC_OFF_SYS_RESET + 0x10

	.globl	_start_warm
_start_warm:
	li	r21, BOOTFLAG_WARM	/* Software reboot			*/
	b	boot_warm

boot_cold:
boot_warm:

	/* Initialize machine status; enable machine check interrupt		*/
	/*----------------------------------------------------------------------*/
	li	r3, MSR_KERNEL		/* Set FP, ME, RI flags */
	mtmsr	r3
	mtspr	SRR1, r3		/* Make SRR1 match MSR */

	addis	r0,0,0x0000		/* lets make sure that r0 is really 0 */
	mtspr   HID0, r0		/* disable I and D caches */

	mfspr	r3, ICR			/* clear Interrupt Cause Register */

	mfmsr	r3			/* turn off address translation */
	addis	r4,0,0xffff
	ori	r4,r4,0xffcf
	and	r3,r3,r4
	mtmsr	r3
	isync
	sync				/* the MMU should be off... */


in_flash:
#if defined(CONFIG_BMW)
	bl early_init_f /* Must be ASM: no stack yet! */
#endif
	/*
	 * Setup BATs - cannot be done in C since we don't have a stack yet
	 */
	bl	setup_bats

	/* Enable MMU.
	 */
	mfmsr	r3
	ori	r3, r3, (MSR_IR | MSR_DR)
	mtmsr	r3
#if !defined(CONFIG_BMW)
	/* Enable and invalidate data cache.
	 */
	mfspr	r3, HID0
	mr	r2, r3
	ori	r3, r3, HID0_DCE | HID0_DCI
	ori	r2, r2, HID0_DCE
	sync
	mtspr	HID0, r3
	mtspr	HID0, r2
	sync

	/* Allocate Initial RAM in data cache.
	 */
	lis	r3, CONFIG_SYS_INIT_RAM_ADDR@h
	ori	r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
	li	r2, 128
	mtctr	r2
1:
	dcbz	r0, r3
	addi	r3, r3, 32
	bdnz	1b

	/* Lock way0 in data cache.
	 */
	mfspr	r3, 1011
	lis	r2, 0xffff
	ori	r2, r2, 0xff1f
	and	r3, r3, r2
	ori	r3, r3, 0x0080
	sync
	mtspr	1011, r3
#endif /* !CONFIG_BMW */
	/*
	 * Thisk the stack pointer *somewhere* sensible. Doesnt
	 * matter much where as we'll move it when we relocate
	 */
	lis	r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
	ori	r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l

	li	r0, 0			/* Make room for stack frame header and	*/
	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/

	/* let the C-code set up the rest					*/
	/*									*/
	/* Be careful to keep code relocatable !				*/
	/*----------------------------------------------------------------------*/

	GET_GOT			/* initialize GOT access			*/

	/* r3: IMMR */
	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/

	mr	r3, r21
	/* r3: BOOTFLAG */
	bl	board_init_f	/* run 1st part of board init code (from Flash) */


	.globl	_start_of_vectors
_start_of_vectors:

/* Machine check */
	STD_EXCEPTION(EXC_OFF_MACH_CHCK, MachineCheck, MachineCheckException)

/* Data Storage exception.  "Never" generated on the 860. */
	STD_EXCEPTION(EXC_OFF_DATA_STOR, DataStorage, UnknownException)

/* Instruction Storage exception.  "Never" generated on the 860. */
	STD_EXCEPTION(EXC_OFF_INS_STOR, InstStorage, UnknownException)

/* External Interrupt exception. */
	STD_EXCEPTION(EXC_OFF_EXTERNAL, ExtInterrupt, external_interrupt)

/* Alignment exception. */
	. = EXC_OFF_ALIGN
Alignment:
	EXCEPTION_PROLOG(SRR0, SRR1)
	mfspr	r4,DAR
	stw	r4,_DAR(r21)
	mfspr	r5,DSISR
	stw	r5,_DSISR(r21)
	addi	r3,r1,STACK_FRAME_OVERHEAD
	li	r20,MSR_KERNEL
	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
	lwz	r6,GOT(transfer_to_handler)
	mtlr	r6
	blrl
.L_Alignment:
	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
	.long	int_return - _start + EXC_OFF_SYS_RESET

/* Program check exception */
	. = EXC_OFF_PROGRAM
ProgramCheck:
	EXCEPTION_PROLOG(SRR0, SRR1)
	addi	r3,r1,STACK_FRAME_OVERHEAD
	li	r20,MSR_KERNEL
	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
	lwz	r6,GOT(transfer_to_handler)
	mtlr	r6
	blrl
.L_ProgramCheck:
	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
	.long	int_return - _start + EXC_OFF_SYS_RESET

	/* No FPU on MPC8xx. This exception is not supposed to happen.
	*/
	STD_EXCEPTION(EXC_OFF_FPUNAVAIL, FPUnavailable, UnknownException)

	/* I guess we could implement decrementer, and may have
	 * to someday for timekeeping.
	 */
	STD_EXCEPTION(EXC_OFF_DECR, Decrementer, timer_interrupt)
	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
	STD_EXCEPTION(0xc00, SystemCall, UnknownException)

	STD_EXCEPTION(EXC_OFF_TRACE, SingleStep, UnknownException)

	STD_EXCEPTION(EXC_OFF_FPUNASSIST, Trap_0e, UnknownException)
	STD_EXCEPTION(EXC_OFF_PMI, Trap_0f, UnknownException)

	STD_EXCEPTION(EXC_OFF_ITME, InstructionTransMiss, UnknownException)
	STD_EXCEPTION(EXC_OFF_DLTME, DataLoadTransMiss, UnknownException)
	STD_EXCEPTION(EXC_OFF_DSTME, DataStoreTransMiss, UnknownException)
	STD_EXCEPTION(EXC_OFF_IABE, InstructionBreakpoint, DebugException)
	STD_EXCEPTION(EXC_OFF_SMIE, SysManageInt, UnknownException)
	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
	STD_EXCEPTION(0x1c00, ReservedC, UnknownException)
	STD_EXCEPTION(0x1d00, ReservedD, UnknownException)
	STD_EXCEPTION(0x1e00, ReservedE, UnknownException)
	STD_EXCEPTION(0x1f00, ReservedF, UnknownException)

	STD_EXCEPTION(EXC_OFF_RMTE, RunModeTrace, UnknownException)

	.globl	_end_of_vectors
_end_of_vectors:


	. = 0x3000

/*
 * This code finishes saving the registers to the exception frame
 * and jumps to the appropriate handler for the exception.
 * Register r21 is pointer into trap frame, r1 has new stack pointer.
 */
	.globl	transfer_to_handler
transfer_to_handler:
	stw	r22,_NIP(r21)
	lis	r22,MSR_POW@h
	andc	r23,r23,r22
	stw	r23,_MSR(r21)
	SAVE_GPR(7, r21)
	SAVE_4GPRS(8, r21)
	SAVE_8GPRS(12, r21)
	SAVE_8GPRS(24, r21)
#if 0
	andi.	r23,r23,MSR_PR
	mfspr	r23,SPRG3		/* if from user, fix up tss.regs */
	beq	2f
	addi	r24,r1,STACK_FRAME_OVERHEAD
	stw	r24,PT_REGS(r23)
2:	addi	r2,r23,-TSS		/* set r2 to current */
	tovirt(r2,r2,r23)
#endif
	mflr	r23
	andi.	r24,r23,0x3f00		/* get vector offset */
	stw	r24,TRAP(r21)
	li	r22,0
	stw	r22,RESULT(r21)
	mtspr	SPRG2,r22		/* r1 is now kernel sp */
#if 0
	addi	r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */
	cmplw	0,r1,r2
	cmplw	1,r1,r24
	crand	1,1,4
	bgt	stack_ovf		/* if r2 < r1 < r2+TASK_STRUCT_SIZE */
#endif
	lwz	r24,0(r23)		/* virtual address of handler */
	lwz	r23,4(r23)		/* where to go when done */
	mtspr	SRR0,r24
	ori	r20,r20,0x30		/* enable IR, DR */
	mtspr	SRR1,r20
	mtlr	r23
	SYNC
	rfi				/* jump to handler, enable MMU */

int_return:
	mfmsr	r28		/* Disable interrupts */
	li	r4,0
	ori	r4,r4,MSR_EE
	andc	r28,r28,r4
	SYNC			/* Some chip revs need this... */
	mtmsr	r28
	SYNC
	lwz	r2,_CTR(r1)
	lwz	r0,_LINK(r1)
	mtctr	r2
	mtlr	r0
	lwz	r2,_XER(r1)
	lwz	r0,_CCR(r1)
	mtspr	XER,r2
	mtcrf	0xFF,r0
	REST_10GPRS(3, r1)
	REST_10GPRS(13, r1)
	REST_8GPRS(23, r1)
	REST_GPR(31, r1)
	lwz	r2,_NIP(r1)	/* Restore environment */
	lwz	r0,_MSR(r1)
	mtspr	SRR0,r2
	mtspr	SRR1,r0
	lwz	r0,GPR0(r1)
	lwz	r2,GPR2(r1)
	lwz	r1,GPR1(r1)
	SYNC
	rfi

/* Cache functions.
*/
	.globl	icache_enable
icache_enable:
	mfspr	r5,HID0		/* turn on the I cache. */
	ori	r5,r5,0x8800	/* Instruction cache only! */
	addis	r6,0,0xFFFF
	ori	r6,r6,0xF7FF
	and	r6,r5,r6	/* clear the invalidate bit */
	sync
	mtspr	HID0,r5
	mtspr	HID0,r6
	isync
	sync
	blr

	.globl	icache_disable
icache_disable:
	mfspr	r5,HID0
	addis	r6,0,0xFFFF
	ori	r6,r6,0x7FFF
	and	r5,r5,r6
	sync
	mtspr	HID0,r5
	isync
	sync
	blr

	.globl	icache_status
icache_status:
	mfspr	r3, HID0
	srwi	r3, r3, 15	/* >>15 & 1=> select bit 16 */
	andi.	r3, r3, 1
	blr

	.globl	dcache_enable
dcache_enable:
	mfspr	r5,HID0		/* turn on the D cache. */
	ori	r5,r5,0x4400	/* Data cache only! */
	mfspr	r4, PVR		/* read PVR */
	srawi	r3, r4, 16	/* shift off the least 16 bits */
	cmpi	0, 0, r3, 0xC	/* Check for Max pvr */
	bne	NotMax
	ori	r5,r5,0x0040	/* setting the DCFA bit, for Max rev 1 errata */
NotMax:
	addis	r6,0,0xFFFF
	ori	r6,r6,0xFBFF
	and	r6,r5,r6	/* clear the invalidate bit */
	sync
	mtspr	HID0,r5
	mtspr	HID0,r6
	isync
	sync
	blr

	.globl	dcache_disable
dcache_disable:
	mfspr	r5,HID0
	addis	r6,0,0xFFFF
	ori	r6,r6,0xBFFF
	and	r5,r5,r6
	sync
	mtspr	HID0,r5
	isync
	sync
	blr

	.globl	dcache_status
dcache_status:
	mfspr	r3, HID0
	srwi	r3, r3, 14	/* >>14 & 1=> select bit 17 */
	andi.	r3, r3, 1
	blr

	.globl	dc_read
dc_read:
/*TODO : who uses this, what should it do?
*/
	blr


	.globl get_pvr
get_pvr:
	mfspr	r3, PVR
	blr


/*------------------------------------------------------------------------------*/

/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 * r3 = dest
 * r4 = src
 * r5 = length in bytes
 * r6 = cachelinesize
 */
	.globl	relocate_code
relocate_code:

	mr	r1,  r3		/* Set new stack pointer		*/
	mr	r9,  r4		/* Save copy of Global Data pointer	*/
	mr	r10, r5		/* Save copy of Destination Address	*/

	mr	r3,  r5				/* Destination Address	*/
#ifdef CONFIG_SYS_RAMBOOT
	lis	r4, CONFIG_SYS_SDRAM_BASE@h		/* Source      Address	*/
	ori	r4, r4, CONFIG_SYS_SDRAM_BASE@l
#else
	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
#endif
	lwz	r5, GOT(__init_end)
	sub	r5, r5, r4
	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size	*/

	/*
	 * Fix GOT pointer:
	 *
	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
	 *
	 * Offset:
	 */
	sub	r15, r10, r4

	/* First our own GOT */
	add	r14, r14, r15
	/* the the one used by the C code */
	add	r30, r30, r15

	/*
	 * Now relocate code
	 */

	cmplw	cr1,r3,r4
	addi	r0,r5,3
	srwi.	r0,r0,2
	beq	cr1,4f		/* In place copy is not necessary	*/
	beq	7f		/* Protect against 0 count		*/
	mtctr	r0
	bge	cr1,2f

	la	r8,-4(r4)
	la	r7,-4(r3)
1:	lwzu	r0,4(r8)
	stwu	r0,4(r7)
	bdnz	1b
	b	4f

2:	slwi	r0,r0,2
	add	r8,r4,r0
	add	r7,r3,r0
3:	lwzu	r0,-4(r8)
	stwu	r0,-4(r7)
	bdnz	3b

4:
#if !defined(CONFIG_BMW)
/* Unlock the data cache and invalidate locked area */
	xor	r0, r0, r0
	mtspr	1011, r0
	lis	r4, CONFIG_SYS_INIT_RAM_ADDR@h
	ori	r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l
	li	r0, 128
	mtctr	r0
41:
	dcbi	r0, r4
	addi	r4, r4, 32
	bdnz	41b
#endif

/*
 * Now flush the cache: note that we must start from a cache aligned
 * address. Otherwise we might miss one cache line.
 */
	cmpwi	r6,0
	add	r5,r3,r5
	beq	7f		/* Always flush prefetch queue in any case */
	subi	r0,r6,1
	andc	r3,r3,r0
	mr	r4,r3
5:	dcbst	0,r4
	add	r4,r4,r6
	cmplw	r4,r5
	blt	5b
	sync			/* Wait for all dcbst to complete on bus */
	mr	r4,r3
6:	icbi	0,r4
	add	r4,r4,r6
	cmplw	r4,r5
	blt	6b
7:	sync			/* Wait for all icbi to complete on bus	*/
	isync

/*
 * We are done. Do not return, instead branch to second part of board
 * initialization, now running from RAM.
 */

	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
	mtlr	r0
	blr

in_ram:

	/*
	 * Relocation Function, r14 point to got2+0x8000
	 *
	 * Adjust got2 pointers, no need to check for 0, this code
	 * already puts a few entries in the table.
	 */
	li	r0,__got2_entries@sectoff@l
	la	r3,GOT(_GOT2_TABLE_)
	lwz	r11,GOT(_GOT2_TABLE_)
	mtctr	r0
	sub	r11,r3,r11
	addi	r3,r3,-4
1:	lwzu	r0,4(r3)
	add	r0,r0,r11
	stw	r0,0(r3)
	bdnz	1b

	/*
	 * Now adjust the fixups and the pointers to the fixups
	 * in case we need to move ourselves again.
	 */
2:	li	r0,__fixup_entries@sectoff@l
	lwz	r3,GOT(_FIXUP_TABLE_)
	cmpwi	r0,0
	mtctr	r0
	addi	r3,r3,-4
	beq	4f
3:	lwzu	r4,4(r3)
	lwzux	r0,r4,r11
	add	r0,r0,r11
	stw	r10,0(r3)
	stw	r0,0(r4)
	bdnz	3b
4:
clear_bss:
	/*
	 * Now clear BSS segment
	 */
	lwz	r3,GOT(__bss_start)
	lwz	r4,GOT(_end)

	cmplw	0, r3, r4
	beq	6f

	li	r0, 0
5:
	stw	r0, 0(r3)
	addi	r3, r3, 4
	cmplw	0, r3, r4
	blt	5b
6:

	mr	r3, r9		/* Global Data pointer		*/
	mr	r4, r10		/* Destination Address		*/
	bl	board_init_r

	/*
	 * Copy exception vector code to low memory
	 *
	 * r3: dest_addr
	 * r7: source address, r8: end address, r9: target address
	 */
	.globl	trap_init
trap_init:
	lwz	r7, GOT(_start)
	lwz	r8, GOT(_end_of_vectors)

	li	r9, 0x100		/* reset vector always at 0x100 */

	cmplw	0, r7, r8
	bgelr				/* return if r7>=r8 - just in case */

	mflr	r4			/* save link register		*/
1:
	lwz	r0, 0(r7)
	stw	r0, 0(r9)
	addi	r7, r7, 4
	addi	r9, r9, 4
	cmplw	0, r7, r8
	bne	1b

	/*
	 * relocate `hdlr' and `int_return' entries
	 */
	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
2:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector	*/
	cmplw	0, r7, r8
	blt	2b

	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
	bl	trap_reloc

	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
	bl	trap_reloc

	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
3:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector	*/
	cmplw	0, r7, r8
	blt	3b

	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
4:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector	*/
	cmplw	0, r7, r8
	blt	4b

	mtlr	r4			/* restore link register	*/
	blr

	/*
	 * Function: relocate entries for one exception vector
	 */
trap_reloc:
	lwz	r0, 0(r7)		/* hdlr ...			*/
	add	r0, r0, r3		/*  ... += dest_addr		*/
	stw	r0, 0(r7)

	lwz	r0, 4(r7)		/* int_return ...		*/
	add	r0, r0, r3		/*  ... += dest_addr		*/
	stw	r0, 4(r7)

	blr

	/* Setup the BAT registers.
	 */
setup_bats:
	lis	r4, CONFIG_SYS_IBAT0L@h
	ori	r4, r4, CONFIG_SYS_IBAT0L@l
	lis	r3, CONFIG_SYS_IBAT0U@h
	ori	r3, r3, CONFIG_SYS_IBAT0U@l
	mtspr	IBAT0L, r4
	mtspr	IBAT0U, r3
	isync

	lis	r4, CONFIG_SYS_DBAT0L@h
	ori	r4, r4, CONFIG_SYS_DBAT0L@l
	lis	r3, CONFIG_SYS_DBAT0U@h
	ori	r3, r3, CONFIG_SYS_DBAT0U@l
	mtspr	DBAT0L, r4
	mtspr	DBAT0U, r3
	isync

	lis	r4, CONFIG_SYS_IBAT1L@h
	ori	r4, r4, CONFIG_SYS_IBAT1L@l
	lis	r3, CONFIG_SYS_IBAT1U@h
	ori	r3, r3, CONFIG_SYS_IBAT1U@l
	mtspr	IBAT1L, r4
	mtspr	IBAT1U, r3
	isync

	lis	r4, CONFIG_SYS_DBAT1L@h
	ori	r4, r4, CONFIG_SYS_DBAT1L@l
	lis	r3, CONFIG_SYS_DBAT1U@h
	ori	r3, r3, CONFIG_SYS_DBAT1U@l
	mtspr	DBAT1L, r4
	mtspr	DBAT1U, r3
	isync

	lis	r4, CONFIG_SYS_IBAT2L@h
	ori	r4, r4, CONFIG_SYS_IBAT2L@l
	lis	r3, CONFIG_SYS_IBAT2U@h
	ori	r3, r3, CONFIG_SYS_IBAT2U@l
	mtspr	IBAT2L, r4
	mtspr	IBAT2U, r3
	isync

	lis	r4, CONFIG_SYS_DBAT2L@h
	ori	r4, r4, CONFIG_SYS_DBAT2L@l
	lis	r3, CONFIG_SYS_DBAT2U@h
	ori	r3, r3, CONFIG_SYS_DBAT2U@l
	mtspr	DBAT2L, r4
	mtspr	DBAT2U, r3
	isync

	lis	r4, CONFIG_SYS_IBAT3L@h
	ori	r4, r4, CONFIG_SYS_IBAT3L@l
	lis	r3, CONFIG_SYS_IBAT3U@h
	ori	r3, r3, CONFIG_SYS_IBAT3U@l
	mtspr	IBAT3L, r4
	mtspr	IBAT3U, r3
	isync

	lis	r4, CONFIG_SYS_DBAT3L@h
	ori	r4, r4, CONFIG_SYS_DBAT3L@l
	lis	r3, CONFIG_SYS_DBAT3U@h
	ori	r3, r3, CONFIG_SYS_DBAT3U@l
	mtspr	DBAT3L, r4
	mtspr	DBAT3U, r3
	isync

	/* Invalidate TLBs.
	 * -> for (val = 0; val < 0x20000; val+=0x1000)
	 * ->   tlbie(val);
	 */
	lis	r3, 0
	lis	r5, 2

1:
	tlbie	r3
	addi	r3, r3, 0x1000
	cmp	0, 0, r3, r5
	blt	1b

	blr
Commit	Line	Data
c609719b WD	1	/*
	2	* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
	3	* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
	4	* Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	/* U-Boot - Startup Code for PowerPC based Embedded Boards
	26	*
	27	*
	28	* The processor starts at 0x00000100 and the code is executed
	29	* from flash. The code is organized to be at an other address
	30	* in memory, but as long we don't jump around before relocating.
	31	* board_init lies at a quite high address and when the cpu has
	32	* jumped there, everything is ok.
	33	* This works because the cpu gives the FLASH (CS0) the whole
	34	* address space at startup, and board_init lies as a echo of
	35	* the flash somewhere up there in the memorymap.
	36	*
	37	* board_init will change CS0 to be positioned at the correct
	38	* address and (s)dram will be positioned at address 0
	39	*/
	40	#include <config.h>
	41	#include <mpc824x.h>
	42	#include <version.h>
	43
	44	#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
	45
	46	#include <ppc_asm.tmpl>
	47	#include <ppc_defs.h>
	48
	49	#include <asm/cache.h>
	50	#include <asm/mmu.h>
	51
	52	#ifndef CONFIG_IDENT_STRING
	53	#define CONFIG_IDENT_STRING ""
	54	#endif
	55
	56	/* We don't want the MMU yet.
	57	*/
	58	#undef MSR_KERNEL
	59	/* FP, Machine Check and Recoverable Interr. */
	60	#define MSR_KERNEL ( MSR_FP \| MSR_ME \| MSR_RI )
	61
	62	/*
	63	* Set up GOT: Global Offset Table
	64	*
65	* Use r14 to access the GOT
66	*/
67	START_GOT
68	GOT_ENTRY(_GOT2_TABLE_)
69	GOT_ENTRY(_FIXUP_TABLE_)
70
71	GOT_ENTRY(_start)
72	GOT_ENTRY(_start_of_vectors)
73	GOT_ENTRY(_end_of_vectors)
74	GOT_ENTRY(transfer_to_handler)
75
3b57fe0a	76	GOT_ENTRY(__init_end)
c609719b	77	GOT_ENTRY(_end)
5d232d0e	78	GOT_ENTRY(__bss_start)
c609719b WD	79	#if defined(CONFIG_FADS)
	80	GOT_ENTRY(environment)
	81	#endif
	82	END_GOT
	83
	84	/*
	85	* r3 - 1st arg to board_init(): IMMP pointer
	86	* r4 - 2nd arg to board_init(): boot flag
	87	*/
	88	.text
	89	.long 0x27051956 /* U-Boot Magic Number */
	90	.globl version_string
	91	version_string:
	92	.ascii U_BOOT_VERSION
	93	.ascii " (", __DATE__, " - ", __TIME__, ")"
	94	.ascii CONFIG_IDENT_STRING, "\0"
	95
	96	. = EXC_OFF_SYS_RESET
	97	.globl _start
	98	_start:
	99	li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
	100	b boot_cold
	101
	102	. = EXC_OFF_SYS_RESET + 0x10
	103
	104	.globl _start_warm
	105	_start_warm:
	106	li r21, BOOTFLAG_WARM /* Software reboot */
	107	b boot_warm
	108
	109	boot_cold:
	110	boot_warm:
	111
	112	/* Initialize machine status; enable machine check interrupt */
	113	/----------------------------------------------------------------------/
	114	li r3, MSR_KERNEL /* Set FP, ME, RI flags */
	115	mtmsr r3
	116	mtspr SRR1, r3 /* Make SRR1 match MSR */
	117
	118	addis r0,0,0x0000 /* lets make sure that r0 is really 0 */
	119	mtspr HID0, r0 /* disable I and D caches */
	120
	121	mfspr r3, ICR /* clear Interrupt Cause Register */
	122
	123	mfmsr r3 /* turn off address translation */
	124	addis r4,0,0xffff
	125	ori r4,r4,0xffcf
	126	and r3,r3,r4
	127	mtmsr r3
	128	isync
	129	sync /* the MMU should be off... */
	130
	131
	132	in_flash:
	133	#if defined(CONFIG_BMW)
	134	bl early_init_f /* Must be ASM: no stack yet! */
	135	#endif
	136	/*
	137	* Setup BATs - cannot be done in C since we don't have a stack yet
	138	*/
	139	bl setup_bats
	140
	141	/* Enable MMU.
	142	*/
143	mfmsr r3
144	ori r3, r3, (MSR_IR \| MSR_DR)
145	mtmsr r3
146	#if !defined(CONFIG_BMW)
147	/* Enable and invalidate data cache.
148	*/
149	mfspr r3, HID0
150	mr r2, r3
151	ori r3, r3, HID0_DCE \| HID0_DCI
152	ori r2, r2, HID0_DCE
153	sync
154	mtspr HID0, r3
155	mtspr HID0, r2
156	sync
157
158	/* Allocate Initial RAM in data cache.
159	*/
6d0f6bcf JCPV	160	lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
6d0f6bcf JCPV	161	ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
c609719b WD	162	li r2, 128
	163	mtctr r2
	164	1:
	165	dcbz r0, r3
	166	addi r3, r3, 32
	167	bdnz 1b
	168
	169	/* Lock way0 in data cache.
	170	*/
	171	mfspr r3, 1011
	172	lis r2, 0xffff
	173	ori r2, r2, 0xff1f
	174	and r3, r3, r2
	175	ori r3, r3, 0x0080
	176	sync
	177	mtspr 1011, r3
	178	#endif /* !CONFIG_BMW */
	179	/*
	180	* Thisk the stack pointer somewhere sensible. Doesnt
	181	* matter much where as we'll move it when we relocate
	182	*/
6d0f6bcf JCPV	183	lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
6d0f6bcf JCPV	184	ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
c609719b WD	185
	186	li r0, 0 /* Make room for stack frame header and */
	187	stwu r0, -4(r1) /* clear final stack frame so that */
	188	stwu r0, -4(r1) /* stack backtraces terminate cleanly */
	189
	190	/* let the C-code set up the rest */
	191	/* */
	192	/* Be careful to keep code relocatable ! */
	193	/----------------------------------------------------------------------/
	194
	195	GET_GOT /* initialize GOT access */
	196
	197	/* r3: IMMR */
	198	bl cpu_init_f /* run low-level CPU init code (from Flash) */
	199
	200	mr r3, r21
	201	/* r3: BOOTFLAG */
	202	bl board_init_f /* run 1st part of board init code (from Flash) */
	203
	204
c609719b WD	205	.globl _start_of_vectors
	206	_start_of_vectors:
	207
	208	/* Machine check */
	209	STD_EXCEPTION(EXC_OFF_MACH_CHCK, MachineCheck, MachineCheckException)
	210
	211	/* Data Storage exception. "Never" generated on the 860. */
	212	STD_EXCEPTION(EXC_OFF_DATA_STOR, DataStorage, UnknownException)
	213
	214	/* Instruction Storage exception. "Never" generated on the 860. */
	215	STD_EXCEPTION(EXC_OFF_INS_STOR, InstStorage, UnknownException)
	216
	217	/* External Interrupt exception. */
	218	STD_EXCEPTION(EXC_OFF_EXTERNAL, ExtInterrupt, external_interrupt)
	219
	220	/* Alignment exception. */
	221	. = EXC_OFF_ALIGN
	222	Alignment:
02032e8f	223	EXCEPTION_PROLOG(SRR0, SRR1)
c609719b WD	224	mfspr r4,DAR
	225	stw r4,_DAR(r21)
	226	mfspr r5,DSISR
	227	stw r5,_DSISR(r21)
	228	addi r3,r1,STACK_FRAME_OVERHEAD
	229	li r20,MSR_KERNEL
	230	rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
	231	lwz r6,GOT(transfer_to_handler)
	232	mtlr r6
	233	blrl
	234	.L_Alignment:
	235	.long AlignmentException - _start + EXC_OFF_SYS_RESET
	236	.long int_return - _start + EXC_OFF_SYS_RESET
	237
	238	/* Program check exception */
	239	. = EXC_OFF_PROGRAM
	240	ProgramCheck:
02032e8f	241	EXCEPTION_PROLOG(SRR0, SRR1)
c609719b WD	242	addi r3,r1,STACK_FRAME_OVERHEAD
	243	li r20,MSR_KERNEL
	244	rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
	245	lwz r6,GOT(transfer_to_handler)
	246	mtlr r6
	247	blrl
	248	.L_ProgramCheck:
	249	.long ProgramCheckException - _start + EXC_OFF_SYS_RESET
	250	.long int_return - _start + EXC_OFF_SYS_RESET
	251
	252	/* No FPU on MPC8xx. This exception is not supposed to happen.
	253	*/
	254	STD_EXCEPTION(EXC_OFF_FPUNAVAIL, FPUnavailable, UnknownException)
	255
	256	/* I guess we could implement decrementer, and may have
	257	* to someday for timekeeping.
	258	*/
	259	STD_EXCEPTION(EXC_OFF_DECR, Decrementer, timer_interrupt)
	260	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
	261	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
27b207fd	262	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
c609719b WD	263
	264	STD_EXCEPTION(EXC_OFF_TRACE, SingleStep, UnknownException)
	265
	266	STD_EXCEPTION(EXC_OFF_FPUNASSIST, Trap_0e, UnknownException)
	267	STD_EXCEPTION(EXC_OFF_PMI, Trap_0f, UnknownException)
	268
	269	STD_EXCEPTION(EXC_OFF_ITME, InstructionTransMiss, UnknownException)
	270	STD_EXCEPTION(EXC_OFF_DLTME, DataLoadTransMiss, UnknownException)
	271	STD_EXCEPTION(EXC_OFF_DSTME, DataStoreTransMiss, UnknownException)
43d9616c	272	STD_EXCEPTION(EXC_OFF_IABE, InstructionBreakpoint, DebugException)
c609719b WD	273	STD_EXCEPTION(EXC_OFF_SMIE, SysManageInt, UnknownException)
	274	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
	275	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
	276	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
	277	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
	278	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
	279	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
	280	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
	281	STD_EXCEPTION(0x1c00, ReservedC, UnknownException)
	282	STD_EXCEPTION(0x1d00, ReservedD, UnknownException)
	283	STD_EXCEPTION(0x1e00, ReservedE, UnknownException)
	284	STD_EXCEPTION(0x1f00, ReservedF, UnknownException)
	285
	286	STD_EXCEPTION(EXC_OFF_RMTE, RunModeTrace, UnknownException)
	287
	288	.globl _end_of_vectors
	289	_end_of_vectors:
	290
	291
	292	. = 0x3000
	293
	294	/*
	295	* This code finishes saving the registers to the exception frame
	296	* and jumps to the appropriate handler for the exception.
	297	* Register r21 is pointer into trap frame, r1 has new stack pointer.
	298	*/
	299	.globl transfer_to_handler
	300	transfer_to_handler:
	301	stw r22,_NIP(r21)
	302	lis r22,MSR_POW@h
	303	andc r23,r23,r22
	304	stw r23,_MSR(r21)
	305	SAVE_GPR(7, r21)
	306	SAVE_4GPRS(8, r21)
	307	SAVE_8GPRS(12, r21)
	308	SAVE_8GPRS(24, r21)
	309	#if 0
	310	andi. r23,r23,MSR_PR
	311	mfspr r23,SPRG3 /* if from user, fix up tss.regs */
	312	beq 2f
	313	addi r24,r1,STACK_FRAME_OVERHEAD
	314	stw r24,PT_REGS(r23)
	315	2: addi r2,r23,-TSS /* set r2 to current */
	316	tovirt(r2,r2,r23)
	317	#endif
	318	mflr r23
	319	andi. r24,r23,0x3f00 /* get vector offset */
	320	stw r24,TRAP(r21)
	321	li r22,0
	322	stw r22,RESULT(r21)
	323	mtspr SPRG2,r22 /* r1 is now kernel sp */
	324	#if 0
	325	addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */
	326	cmplw 0,r1,r2
	327	cmplw 1,r1,r24
	328	crand 1,1,4
	329	bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */
	330	#endif
	331	lwz r24,0(r23) /* virtual address of handler */
	332	lwz r23,4(r23) /* where to go when done */
	333	mtspr SRR0,r24
	334	ori r20,r20,0x30 /* enable IR, DR */
	335	mtspr SRR1,r20
	336	mtlr r23
337	SYNC
338	rfi /* jump to handler, enable MMU */
339
340	int_return:
341	mfmsr r28 /* Disable interrupts */
342	li r4,0
343	ori r4,r4,MSR_EE
344	andc r28,r28,r4
345	SYNC /* Some chip revs need this... */
346	mtmsr r28
347	SYNC
348	lwz r2,_CTR(r1)
349	lwz r0,_LINK(r1)
350	mtctr r2
351	mtlr r0
352	lwz r2,_XER(r1)
353	lwz r0,_CCR(r1)
354	mtspr XER,r2
355	mtcrf 0xFF,r0
356	REST_10GPRS(3, r1)
357	REST_10GPRS(13, r1)
358	REST_8GPRS(23, r1)
359	REST_GPR(31, r1)
360	lwz r2,_NIP(r1) /* Restore environment */
361	lwz r0,_MSR(r1)
362	mtspr SRR0,r2
363	mtspr SRR1,r0
364	lwz r0,GPR0(r1)
365	lwz r2,GPR2(r1)
366	lwz r1,GPR1(r1)
367	SYNC
368	rfi
369
370	/* Cache functions.
371	*/
372	.globl icache_enable
373	icache_enable:
374	mfspr r5,HID0 /* turn on the I cache. */
375	ori r5,r5,0x8800 /* Instruction cache only! */
376	addis r6,0,0xFFFF
377	ori r6,r6,0xF7FF
378	and r6,r5,r6 /* clear the invalidate bit */
379	sync
380	mtspr HID0,r5
381	mtspr HID0,r6
382	isync
383	sync
384	blr
385
386	.globl icache_disable
387	icache_disable:
388	mfspr r5,HID0
389	addis r6,0,0xFFFF
390	ori r6,r6,0x7FFF
391	and r5,r5,r6
392	sync
393	mtspr HID0,r5
394	isync
395	sync
396	blr
397
398	.globl icache_status
399	icache_status:
400	mfspr r3, HID0
401	srwi r3, r3, 15 /* >>15 & 1=> select bit 16 */
402	andi. r3, r3, 1
403	blr
404
405	.globl dcache_enable
406	dcache_enable:
407	mfspr r5,HID0 /* turn on the D cache. */
408	ori r5,r5,0x4400 /* Data cache only! */
409	mfspr r4, PVR /* read PVR */
410	srawi r3, r4, 16 /* shift off the least 16 bits */
411	cmpi 0, 0, r3, 0xC /* Check for Max pvr */
412	bne NotMax
413	ori r5,r5,0x0040 /* setting the DCFA bit, for Max rev 1 errata */
414	NotMax:
415	addis r6,0,0xFFFF
416	ori r6,r6,0xFBFF
417	and r6,r5,r6 /* clear the invalidate bit */
418	sync
419	mtspr HID0,r5
420	mtspr HID0,r6
421	isync
422	sync
423	blr
424
425	.globl dcache_disable
426	dcache_disable:
427	mfspr r5,HID0
428	addis r6,0,0xFFFF
429	ori r6,r6,0xBFFF
430	and r5,r5,r6
431	sync
432	mtspr HID0,r5
433	isync
434	sync
435	blr
436
437	.globl dcache_status
438	dcache_status:
439	mfspr r3, HID0
440	srwi r3, r3, 14 /* >>14 & 1=> select bit 17 */
441	andi. r3, r3, 1
442	blr
443
444	.globl dc_read
445	dc_read:
446	/*TODO : who uses this, what should it do?
447	*/
448	blr
449
450
451	.globl get_pvr
452	get_pvr:
453	mfspr r3, PVR
454	blr
455
456
457	/------------------------------------------------------------------------------/
458
459	/*
460	* void relocate_code (addr_sp, gd, addr_moni)
461	*
462	* This "function" does not return, instead it continues in RAM
463	* after relocating the monitor code.
464	*
465	* r3 = dest
466	* r4 = src
467	* r5 = length in bytes
468	* r6 = cachelinesize
469	*/
470	.globl relocate_code
471	relocate_code:
472
473	mr r1, r3 /* Set new stack pointer */
474	mr r9, r4 /* Save copy of Global Data pointer */
475	mr r10, r5 /* Save copy of Destination Address */
476
477	mr r3, r5 /* Destination Address */
6d0f6bcf JCPV	478	#ifdef CONFIG_SYS_RAMBOOT
	479	lis r4, CONFIG_SYS_SDRAM_BASE@h /* Source Address */
	480	ori r4, r4, CONFIG_SYS_SDRAM_BASE@l
c609719b	481	#else
6d0f6bcf JCPV	482	lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
6d0f6bcf JCPV	483	ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
c609719b	484	#endif
3b57fe0a WD	485	lwz r5, GOT(__init_end)
3b57fe0a WD	486	sub r5, r5, r4
6d0f6bcf	487	li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
c609719b WD	488
	489	/*
	490	* Fix GOT pointer:
	491	*
6d0f6bcf	492	* New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
c609719b WD	493	*
	494	* Offset:
	495	*/
	496	sub r15, r10, r4
	497
	498	/* First our own GOT */
	499	add r14, r14, r15
	500	/* the the one used by the C code */
	501	add r30, r30, r15
	502
	503	/*
	504	* Now relocate code
	505	*/
	506
	507	cmplw cr1,r3,r4
	508	addi r0,r5,3
	509	srwi. r0,r0,2
	510	beq cr1,4f /* In place copy is not necessary */
	511	beq 7f /* Protect against 0 count */
	512	mtctr r0
	513	bge cr1,2f
	514
	515	la r8,-4(r4)
	516	la r7,-4(r3)
	517	1: lwzu r0,4(r8)
	518	stwu r0,4(r7)
	519	bdnz 1b
	520	b 4f
	521
	522	2: slwi r0,r0,2
	523	add r8,r4,r0
	524	add r7,r3,r0
	525	3: lwzu r0,-4(r8)
	526	stwu r0,-4(r7)
	527	bdnz 3b
	528
7205e407 WD	529	4:
	530	#if !defined(CONFIG_BMW)
	531	/* Unlock the data cache and invalidate locked area */
	532	xor r0, r0, r0
	533	mtspr 1011, r0
6d0f6bcf JCPV	534	lis r4, CONFIG_SYS_INIT_RAM_ADDR@h
6d0f6bcf JCPV	535	ori r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l
7205e407 WD	536	li r0, 128
	537	mtctr r0
	538	41:
	539	dcbi r0, r4
	540	addi r4, r4, 32
	541	bdnz 41b
	542	#endif
	543
c609719b WD	544	/*
	545	* Now flush the cache: note that we must start from a cache aligned
	546	* address. Otherwise we might miss one cache line.
	547	*/
7205e407	548	cmpwi r6,0
c609719b WD	549	add r5,r3,r5
	550	beq 7f /* Always flush prefetch queue in any case */
	551	subi r0,r6,1
	552	andc r3,r3,r0
	553	mr r4,r3
	554	5: dcbst 0,r4
	555	add r4,r4,r6
	556	cmplw r4,r5
	557	blt 5b
	558	sync /* Wait for all dcbst to complete on bus */
	559	mr r4,r3
	560	6: icbi 0,r4
	561	add r4,r4,r6
	562	cmplw r4,r5
	563	blt 6b
	564	7: sync /* Wait for all icbi to complete on bus */
	565	isync
	566
	567	/*
	568	* We are done. Do not return, instead branch to second part of board
	569	* initialization, now running from RAM.
	570	*/
	571
	572	addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
	573	mtlr r0
	574	blr
	575
	576	in_ram:
	577
	578	/*
	579	* Relocation Function, r14 point to got2+0x8000
	580	*
	581	* Adjust got2 pointers, no need to check for 0, this code
	582	* already puts a few entries in the table.
	583	*/
	584	li r0,__got2_entries@sectoff@l
	585	la r3,GOT(_GOT2_TABLE_)
	586	lwz r11,GOT(_GOT2_TABLE_)
	587	mtctr r0
	588	sub r11,r3,r11
	589	addi r3,r3,-4
	590	1: lwzu r0,4(r3)
	591	add r0,r0,r11
	592	stw r0,0(r3)
	593	bdnz 1b
	594
	595	/*
	596	* Now adjust the fixups and the pointers to the fixups
	597	* in case we need to move ourselves again.
	598	*/
	599	2: li r0,__fixup_entries@sectoff@l
	600	lwz r3,GOT(_FIXUP_TABLE_)
	601	cmpwi r0,0
	602	mtctr r0
	603	addi r3,r3,-4
	604	beq 4f
	605	3: lwzu r4,4(r3)
	606	lwzux r0,r4,r11
	607	add r0,r0,r11
	608	stw r10,0(r3)
	609	stw r0,0(r4)
	610	bdnz 3b
	611	4:
	612	clear_bss:
613	/*
614	* Now clear BSS segment
615	*/
5d232d0e	616	lwz r3,GOT(__bss_start)
c609719b WD	617	lwz r4,GOT(_end)
	618
	619	cmplw 0, r3, r4
	620	beq 6f
	621
	622	li r0, 0
	623	5:
	624	stw r0, 0(r3)
	625	addi r3, r3, 4
	626	cmplw 0, r3, r4
	627	blt 5b
	628	6:
	629
	630	mr r3, r9 /* Global Data pointer */
	631	mr r4, r10 /* Destination Address */
	632	bl board_init_r
	633
c609719b WD	634	/*
	635	* Copy exception vector code to low memory
	636	*
	637	* r3: dest_addr
	638	* r7: source address, r8: end address, r9: target address
	639	*/
	640	.globl trap_init
	641	trap_init:
	642	lwz r7, GOT(_start)
	643	lwz r8, GOT(_end_of_vectors)
	644
682011ff	645	li r9, 0x100 /* reset vector always at 0x100 */
c609719b WD	646
	647	cmplw 0, r7, r8
	648	bgelr /* return if r7>=r8 - just in case */
	649
	650	mflr r4 /* save link register */
	651	1:
	652	lwz r0, 0(r7)
	653	stw r0, 0(r9)
	654	addi r7, r7, 4
	655	addi r9, r9, 4
	656	cmplw 0, r7, r8
	657	bne 1b
	658
	659	/*
	660	* relocate `hdlr' and `int_return' entries
	661	*/
	662	li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
	663	li r8, Alignment - _start + EXC_OFF_SYS_RESET
	664	2:
	665	bl trap_reloc
	666	addi r7, r7, 0x100 /* next exception vector */
	667	cmplw 0, r7, r8
	668	blt 2b
	669
	670	li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
	671	bl trap_reloc
	672
	673	li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
	674	bl trap_reloc
	675
	676	li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
	677	li r8, SystemCall - _start + EXC_OFF_SYS_RESET
	678	3:
	679	bl trap_reloc
	680	addi r7, r7, 0x100 /* next exception vector */
	681	cmplw 0, r7, r8
	682	blt 3b
	683
	684	li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
	685	li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
	686	4:
	687	bl trap_reloc
	688	addi r7, r7, 0x100 /* next exception vector */
	689	cmplw 0, r7, r8
	690	blt 4b
	691
	692	mtlr r4 /* restore link register */
	693	blr
	694
	695	/*
	696	* Function: relocate entries for one exception vector
	697	*/
	698	trap_reloc:
	699	lwz r0, 0(r7) /* hdlr ... */
	700	add r0, r0, r3 /* ... += dest_addr */
	701	stw r0, 0(r7)
	702
	703	lwz r0, 4(r7) /* int_return ... */
	704	add r0, r0, r3 /* ... += dest_addr */
	705	stw r0, 4(r7)
	706
	707	blr
	708
	709	/* Setup the BAT registers.
710	*/
711	setup_bats:
6d0f6bcf JCPV	712	lis r4, CONFIG_SYS_IBAT0L@h
	713	ori r4, r4, CONFIG_SYS_IBAT0L@l
	714	lis r3, CONFIG_SYS_IBAT0U@h
	715	ori r3, r3, CONFIG_SYS_IBAT0U@l
c609719b WD	716	mtspr IBAT0L, r4
	717	mtspr IBAT0U, r3
	718	isync
	719
6d0f6bcf JCPV	720	lis r4, CONFIG_SYS_DBAT0L@h
	721	ori r4, r4, CONFIG_SYS_DBAT0L@l
	722	lis r3, CONFIG_SYS_DBAT0U@h
	723	ori r3, r3, CONFIG_SYS_DBAT0U@l
c609719b WD	724	mtspr DBAT0L, r4
	725	mtspr DBAT0U, r3
	726	isync
	727
6d0f6bcf JCPV	728	lis r4, CONFIG_SYS_IBAT1L@h
	729	ori r4, r4, CONFIG_SYS_IBAT1L@l
	730	lis r3, CONFIG_SYS_IBAT1U@h
	731	ori r3, r3, CONFIG_SYS_IBAT1U@l
c609719b WD	732	mtspr IBAT1L, r4
	733	mtspr IBAT1U, r3
	734	isync
	735
6d0f6bcf JCPV	736	lis r4, CONFIG_SYS_DBAT1L@h
	737	ori r4, r4, CONFIG_SYS_DBAT1L@l
	738	lis r3, CONFIG_SYS_DBAT1U@h
	739	ori r3, r3, CONFIG_SYS_DBAT1U@l
c609719b WD	740	mtspr DBAT1L, r4
	741	mtspr DBAT1U, r3
	742	isync
	743
6d0f6bcf JCPV	744	lis r4, CONFIG_SYS_IBAT2L@h
	745	ori r4, r4, CONFIG_SYS_IBAT2L@l
	746	lis r3, CONFIG_SYS_IBAT2U@h
	747	ori r3, r3, CONFIG_SYS_IBAT2U@l
c609719b WD	748	mtspr IBAT2L, r4
	749	mtspr IBAT2U, r3
	750	isync
	751
6d0f6bcf JCPV	752	lis r4, CONFIG_SYS_DBAT2L@h
	753	ori r4, r4, CONFIG_SYS_DBAT2L@l
	754	lis r3, CONFIG_SYS_DBAT2U@h
	755	ori r3, r3, CONFIG_SYS_DBAT2U@l
c609719b WD	756	mtspr DBAT2L, r4
	757	mtspr DBAT2U, r3
	758	isync
	759
6d0f6bcf JCPV	760	lis r4, CONFIG_SYS_IBAT3L@h
	761	ori r4, r4, CONFIG_SYS_IBAT3L@l
	762	lis r3, CONFIG_SYS_IBAT3U@h
	763	ori r3, r3, CONFIG_SYS_IBAT3U@l
c609719b WD	764	mtspr IBAT3L, r4
	765	mtspr IBAT3U, r3
	766	isync
	767
6d0f6bcf JCPV	768	lis r4, CONFIG_SYS_DBAT3L@h
	769	ori r4, r4, CONFIG_SYS_DBAT3L@l
	770	lis r3, CONFIG_SYS_DBAT3U@h
	771	ori r3, r3, CONFIG_SYS_DBAT3U@l
c609719b WD	772	mtspr DBAT3L, r4
	773	mtspr DBAT3U, r3
	774	isync
	775
	776	/* Invalidate TLBs.
	777	* -> for (val = 0; val < 0x20000; val+=0x1000)
	778	* -> tlbie(val);
	779	*/
	780	lis r3, 0
	781	lis r5, 2
	782
	783	1:
	784	tlbie r3
	785	addi r3, r3, 0x1000
	786	cmp 0, 0, r3, r5
	787	blt 1b
	788
	789	blr