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rename CFG_ macros to CONFIG_SYS
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4a9cbbe8 1/*
d87080b7 2 * (C) Copyright 2000-2006
4a9cbbe8
WD
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
8564acf9 25 * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x
4a9cbbe8
WD
26 *
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
29 *
4532cb69 30 * modified by
4a9cbbe8
WD
31 * Wolfgang Denk <wd@denx.de>
32 *
33 * modified for 8260 by
34 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
35 *
36 * added 8260 masks by
37 * Marius Groeger <mag@sysgo.de>
8564acf9 38 *
04a85b3b 39 * added HiP7 (824x/827x/8280) processors support by
8564acf9 40 * Yuli Barcohen <yuli@arabellasw.com>
4a9cbbe8
WD
41 */
42
43#include <common.h>
44#include <watchdog.h>
45#include <command.h>
46#include <mpc8260.h>
47#include <asm/processor.h>
48#include <asm/cpm_8260.h>
49
c9e7b9b9
SS
50#if defined(CONFIG_OF_LIBFDT)
51#include <libfdt.h>
52#include <libfdt_env.h>
e93becf8 53#include <fdt_support.h>
c9e7b9b9
SS
54#endif
55
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WD
56DECLARE_GLOBAL_DATA_PTR;
57
fa230445
HS
58#if defined(CONFIG_GET_CPU_STR_F)
59extern int get_cpu_str_f (char *buf);
60#endif
61
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WD
62int checkcpu (void)
63{
6d0f6bcf 64 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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WD
65 ulong clock = gd->cpu_clk;
66 uint pvr = get_pvr ();
67 uint immr, rev, m, k;
68 char buf[32];
69
70 puts ("CPU: ");
71
8564acf9
WD
72 switch (pvr) {
73 case PVR_8260:
74 case PVR_8260_HIP3:
75 k = 3;
76 break;
77 case PVR_8260_HIP4:
78 k = 4;
79 break;
5779d8d9 80 case PVR_8260_HIP7R1:
e1599e83 81 case PVR_8260_HIP7RA:
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WD
82 case PVR_8260_HIP7:
83 k = 7;
84 break;
85 default:
4a9cbbe8 86 return -1; /* whoops! not an MPC8260 */
8564acf9 87 }
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WD
88 rev = pvr & 0xff;
89
90 immr = immap->im_memctl.memc_immr;
6d0f6bcf 91 if ((immr & IMMR_ISB_MSK) != CONFIG_SYS_IMMR)
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WD
92 return -1; /* whoops! someone moved the IMMR */
93
fa230445
HS
94#if defined(CONFIG_GET_CPU_STR_F)
95 get_cpu_str_f (buf);
96 printf ("%s (HiP%d Rev %02x, Mask ", buf, k, rev);
97#else
8564acf9 98 printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
fa230445 99#endif
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WD
100
101 /*
102 * the bottom 16 bits of the immr are the Part Number and Mask Number
103 * (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the
104 * RISC Microcode Revision Number (13-10).
105 * For the 8260, Motorola doesn't include the Microcode Revision
106 * in the mask.
107 */
108 m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK);
109 k = *((ushort *) & immap->im_dprambase[PROFF_REVNUM]);
110
111 switch (m) {
112 case 0x0000:
4b9206ed 113 puts ("0.2 2J24M");
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WD
114 break;
115 case 0x0010:
4b9206ed 116 puts ("A.0 K22A");
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WD
117 break;
118 case 0x0011:
4b9206ed 119 puts ("A.1 1K22A-XC");
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120 break;
121 case 0x0001:
4b9206ed 122 puts ("B.1 1K23A");
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WD
123 break;
124 case 0x0021:
4b9206ed 125 puts ("B.2 2K23A-XC");
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WD
126 break;
127 case 0x0023:
4b9206ed 128 puts ("B.3 3K23A");
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WD
129 break;
130 case 0x0024:
4b9206ed 131 puts ("C.2 6K23A");
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WD
132 break;
133 case 0x0060:
4b9206ed 134 puts ("A.0(A) 2K25A");
4a9cbbe8 135 break;
4532cb69 136 case 0x0062:
4b9206ed 137 puts ("B.1 4K25A");
4532cb69 138 break;
54387ac9 139 case 0x0064:
4b9206ed 140 puts ("C.0 5K25A");
54387ac9 141 break;
8564acf9 142 case 0x0A00:
4b9206ed 143 puts ("0.0 0K49M");
8564acf9
WD
144 break;
145 case 0x0A01:
4b9206ed 146 puts ("0.1 1K49M");
8564acf9 147 break;
e1599e83
WD
148 case 0x0A10:
149 puts ("1.0 1K49M");
150 break;
04a85b3b 151 case 0x0C00:
e1599e83
WD
152 puts ("0.0 0K50M");
153 break;
154 case 0x0C10:
d980a169 155 puts ("1.0 1K50M");
e1599e83 156 break;
04a85b3b 157 case 0x0D00:
e1599e83
WD
158 puts ("0.0 0K50M");
159 break;
160 case 0x0D10:
d980a169 161 puts ("1.0 1K50M");
04a85b3b 162 break;
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WD
163 default:
164 printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
165 break;
166 }
167
168 printf (") at %s MHz\n", strmhz (buf, clock));
169
170 return 0;
171}
172
173/* ------------------------------------------------------------------------- */
174/* configures a UPM by writing into the UPM RAM array */
175/* uses bank 11 and a dummy physical address (=BRx_BA_MSK) */
176/* NOTE: the physical address chosen must not overlap into any other area */
177/* mapped by the memory controller because bank 11 has the lowest priority */
178
179void upmconfig (uint upm, uint * table, uint size)
180{
6d0f6bcf 181 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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WD
182 volatile memctl8260_t *memctl = &immap->im_memctl;
183 volatile uchar *dummy = (uchar *) BRx_BA_MSK; /* set all BA bits */
184 uint i;
185
186 /* first set up bank 11 to reference the correct UPM at a dummy address */
187
188 memctl->memc_or11 = ORxU_AM_MSK; /* set all AM bits */
189
190 switch (upm) {
191
192 case UPMA:
193 memctl->memc_br11 =
194 ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMA |
195 BRx_V;
196 memctl->memc_mamr = MxMR_OP_WARR;
197 break;
198
199 case UPMB:
200 memctl->memc_br11 =
201 ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMB |
202 BRx_V;
203 memctl->memc_mbmr = MxMR_OP_WARR;
204 break;
205
206 case UPMC:
207 memctl->memc_br11 =
208 ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMC |
209 BRx_V;
210 memctl->memc_mcmr = MxMR_OP_WARR;
211 break;
212
213 default:
214 panic ("upmconfig passed invalid UPM number (%u)\n", upm);
215 break;
216
217 }
218
219 /*
220 * at this point, the dummy address is set up to access the selected UPM,
221 * the MAD pointer is zero, and the MxMR OP is set for writing to RAM
222 *
223 * now we simply load the mdr with each word and poke the dummy address.
224 * the MAD is incremented on each access.
225 */
226
227 for (i = 0; i < size; i++) {
228 memctl->memc_mdr = table[i];
229 *dummy = 0;
230 }
231
232 /* now kill bank 11 */
233 memctl->memc_br11 = 0;
234}
235
236/* ------------------------------------------------------------------------- */
237
ba91e26a 238#if !defined(CONFIG_HAVE_OWN_RESET)
4a9cbbe8 239int
8bde7f77 240do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
4a9cbbe8
WD
241{
242 ulong msr, addr;
243
6d0f6bcf 244 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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WD
245
246 immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */
247
248 /* Interrupts and MMU off */
249 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
250
251 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
252 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
253
254 /*
255 * Trying to execute the next instruction at a non-existing address
256 * should cause a machine check, resulting in reset
257 */
6d0f6bcf
JCPV
258#ifdef CONFIG_SYS_RESET_ADDRESS
259 addr = CONFIG_SYS_RESET_ADDRESS;
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WD
260#else
261 /*
6d0f6bcf 262 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
4a9cbbe8 263 * - sizeof (ulong) is usually a valid address. Better pick an address
6d0f6bcf 264 * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
4a9cbbe8 265 */
6d0f6bcf 266 addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
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WD
267#endif
268 ((void (*)(void)) addr) ();
269 return 1;
270
271}
ba91e26a 272#endif /* CONFIG_HAVE_OWN_RESET */
4a9cbbe8
WD
273
274/* ------------------------------------------------------------------------- */
275
276/*
277 * Get timebase clock frequency (like cpu_clk in Hz)
278 *
279 */
280unsigned long get_tbclk (void)
281{
4a9cbbe8
WD
282 ulong tbclk;
283
284 tbclk = (gd->bus_clk + 3L) / 4L;
285
286 return (tbclk);
287}
288
289/* ------------------------------------------------------------------------- */
290
291#if defined(CONFIG_WATCHDOG)
292void watchdog_reset (void)
293{
294 int re_enable = disable_interrupts ();
295
6d0f6bcf 296 reset_8260_watchdog ((immap_t *) CONFIG_SYS_IMMR);
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WD
297 if (re_enable)
298 enable_interrupts ();
299}
300#endif /* CONFIG_WATCHDOG */
301
302/* ------------------------------------------------------------------------- */
75d3e8fb 303#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
c9e7b9b9
SS
304void ft_cpu_setup (void *blob, bd_t *bd)
305{
306 char * cpu_path = "/cpus/" OF_CPU;
307
ee4ae383
EH
308#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
309 defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
ba37aa03 310 fdt_fixup_ethernet(blob);
ee4ae383
EH
311#endif
312
e93becf8
KG
313 do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
314 do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
315 do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
c9e7b9b9
SS
316}
317#endif /* CONFIG_OF_LIBFDT */