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fe8c2806 WD |
1 | /* |
2 | * MPC8260 SCC Ethernet | |
3 | * | |
4 | * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net) | |
5 | * | |
6 | * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | * Marius Groeger <mgroeger@sysgo.de> | |
8 | * | |
9 | * (C) Copyright (c) 2001 | |
10 | * Advent Networks, Inc. <http://www.adventnetworks.com> | |
11 | * Jay Monkman <jtm@smoothsmoothie.com> | |
12 | * | |
13 | * See file CREDITS for list of people who contributed to this | |
14 | * project. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or | |
17 | * modify it under the terms of the GNU General Public License as | |
18 | * published by the Free Software Foundation; either version 2 of | |
19 | * the License, or (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
29 | * MA 02111-1307 USA | |
30 | */ | |
31 | ||
32 | #include <common.h> | |
33 | #include <asm/cpm_8260.h> | |
34 | #include <mpc8260.h> | |
35 | #include <net.h> | |
36 | #include <command.h> | |
37 | #include <config.h> | |
38 | ||
4431283c | 39 | #if defined(CONFIG_ETHER_ON_SCC) && defined(CONFIG_CMD_NET) |
fe8c2806 WD |
40 | |
41 | #if (CONFIG_ETHER_INDEX == 1) | |
42 | # define PROFF_ENET PROFF_SCC1 | |
43 | # define CPM_CR_ENET_PAGE CPM_CR_SCC1_PAGE | |
44 | # define CPM_CR_ENET_SBLOCK CPM_CR_SCC1_SBLOCK | |
45 | # define CMXSCR_MASK (CMXSCR_SC1 |\ | |
8bde7f77 WD |
46 | CMXSCR_RS1CS_MSK |\ |
47 | CMXSCR_TS1CS_MSK) | |
fe8c2806 WD |
48 | |
49 | #elif (CONFIG_ETHER_INDEX == 2) | |
50 | # define PROFF_ENET PROFF_SCC2 | |
51 | # define CPM_CR_ENET_PAGE CPM_CR_SCC2_PAGE | |
52 | # define CPM_CR_ENET_SBLOCK CPM_CR_SCC2_SBLOCK | |
53 | # define CMXSCR_MASK (CMXSCR_SC2 |\ | |
8bde7f77 WD |
54 | CMXSCR_RS2CS_MSK |\ |
55 | CMXSCR_TS2CS_MSK) | |
fe8c2806 WD |
56 | |
57 | #elif (CONFIG_ETHER_INDEX == 3) | |
58 | # define PROFF_ENET PROFF_SCC3 | |
59 | # define CPM_CR_ENET_PAGE CPM_CR_SCC3_PAGE | |
60 | # define CPM_CR_ENET_SBLOCK CPM_CR_SCC3_SBLOCK | |
61 | # define CMXSCR_MASK (CMXSCR_SC3 |\ | |
8bde7f77 WD |
62 | CMXSCR_RS3CS_MSK |\ |
63 | CMXSCR_TS3CS_MSK) | |
fe8c2806 WD |
64 | #elif (CONFIG_ETHER_INDEX == 4) |
65 | # define PROFF_ENET PROFF_SCC4 | |
66 | # define CPM_CR_ENET_PAGE CPM_CR_SCC4_PAGE | |
67 | # define CPM_CR_ENET_SBLOCK CPM_CR_SCC4_SBLOCK | |
68 | # define CMXSCR_MASK (CMXSCR_SC4 |\ | |
8bde7f77 WD |
69 | CMXSCR_RS4CS_MSK |\ |
70 | CMXSCR_TS4CS_MSK) | |
fe8c2806 WD |
71 | |
72 | #endif | |
73 | ||
74 | ||
75 | /* Ethernet Transmit and Receive Buffers */ | |
76 | #define DBUF_LENGTH 1520 | |
77 | ||
78 | #define TX_BUF_CNT 2 | |
79 | ||
6d0f6bcf JCPV |
80 | #if !defined(CONFIG_SYS_SCC_TOUT_LOOP) |
81 | #define CONFIG_SYS_SCC_TOUT_LOOP 1000000 | |
ac9db066 | 82 | #endif |
fe8c2806 WD |
83 | |
84 | static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ]; | |
85 | ||
86 | static uint rxIdx; /* index of the current RX buffer */ | |
87 | static uint txIdx; /* index of the current TX buffer */ | |
88 | ||
89 | /* | |
90 | * SCC Ethernet Tx and Rx buffer descriptors allocated at the | |
91 | * immr->udata_bd address on Dual-Port RAM | |
92 | * Provide for Double Buffering | |
93 | */ | |
94 | ||
95 | typedef volatile struct CommonBufferDescriptor { | |
96 | cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ | |
97 | cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ | |
98 | } RTXBD; | |
99 | ||
100 | static RTXBD *rtx; | |
101 | ||
102 | ||
103 | int eth_send(volatile void *packet, int length) | |
104 | { | |
105 | int i; | |
106 | int result = 0; | |
107 | ||
108 | if (length <= 0) { | |
8bde7f77 WD |
109 | printf("scc: bad packet size: %d\n", length); |
110 | goto out; | |
fe8c2806 WD |
111 | } |
112 | ||
113 | for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { | |
6d0f6bcf | 114 | if (i >= CONFIG_SYS_SCC_TOUT_LOOP) { |
4b9206ed | 115 | puts ("scc: tx buffer not ready\n"); |
8bde7f77 WD |
116 | goto out; |
117 | } | |
fe8c2806 WD |
118 | } |
119 | ||
120 | rtx->txbd[txIdx].cbd_bufaddr = (uint)packet; | |
121 | rtx->txbd[txIdx].cbd_datlen = length; | |
122 | rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | | |
8bde7f77 | 123 | BD_ENET_TX_WRAP); |
fe8c2806 WD |
124 | |
125 | for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { | |
6d0f6bcf | 126 | if (i >= CONFIG_SYS_SCC_TOUT_LOOP) { |
4b9206ed | 127 | puts ("scc: tx error\n"); |
8bde7f77 WD |
128 | goto out; |
129 | } | |
fe8c2806 WD |
130 | } |
131 | ||
132 | /* return only status bits */ | |
133 | result = rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS; | |
134 | ||
135 | out: | |
136 | return result; | |
137 | } | |
138 | ||
139 | ||
140 | int eth_rx(void) | |
141 | { | |
142 | int length; | |
143 | ||
144 | for (;;) | |
145 | { | |
8bde7f77 WD |
146 | if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { |
147 | length = -1; | |
148 | break; /* nothing received - leave for() loop */ | |
149 | } | |
150 | ||
151 | length = rtx->rxbd[rxIdx].cbd_datlen; | |
152 | ||
153 | if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) | |
154 | { | |
155 | printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc); | |
156 | } | |
157 | else | |
158 | { | |
159 | /* Pass the packet up to the protocol layers. */ | |
160 | NetReceive(NetRxPackets[rxIdx], length - 4); | |
161 | } | |
162 | ||
163 | ||
164 | /* Give the buffer back to the SCC. */ | |
165 | rtx->rxbd[rxIdx].cbd_datlen = 0; | |
166 | ||
167 | /* wrap around buffer index when necessary */ | |
168 | if ((rxIdx + 1) >= PKTBUFSRX) { | |
169 | rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | | |
170 | BD_ENET_RX_EMPTY); | |
171 | rxIdx = 0; | |
172 | } | |
173 | else { | |
174 | rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; | |
175 | rxIdx++; | |
176 | } | |
fe8c2806 WD |
177 | } |
178 | return length; | |
179 | } | |
180 | ||
181 | /************************************************************** | |
182 | * | |
183 | * SCC Ethernet Initialization Routine | |
184 | * | |
185 | *************************************************************/ | |
186 | ||
187 | int eth_init(bd_t *bis) | |
188 | { | |
189 | int i; | |
6d0f6bcf | 190 | volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
fe8c2806 WD |
191 | scc_enet_t *pram_ptr; |
192 | uint dpaddr; | |
193 | ||
194 | rxIdx = 0; | |
195 | txIdx = 0; | |
196 | ||
197 | /* assign static pointer to BD area */ | |
198 | dpaddr = m8260_cpm_dpalloc(sizeof(RTXBD) + 2, 16); | |
199 | rtx = (RTXBD *)&immr->im_dprambase[dpaddr]; | |
200 | ||
201 | /* 24.21 - (1-3): ioports have been set up already */ | |
202 | ||
203 | /* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */ | |
204 | immr->im_cpmux.cmx_uar = 0; | |
205 | immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) | | |
6d0f6bcf | 206 | CONFIG_SYS_CMXSCR_VALUE); |
fe8c2806 WD |
207 | |
208 | ||
209 | /* 24.21 (6) write RBASE and TBASE to parameter RAM */ | |
210 | pram_ptr = (scc_enet_t *)&(immr->im_dprambase[PROFF_ENET]); | |
211 | pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]); | |
212 | pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]); | |
213 | ||
214 | pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Nrml Ops and Mot byte ordering */ | |
215 | pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Nrml access */ | |
216 | ||
217 | pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. package len 1520 */ | |
218 | ||
219 | pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */ | |
220 | pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */ | |
221 | ||
222 | ||
223 | /* 24.21 - (7): Write INIT RX AND TX PARAMETERS to CPCR */ | |
224 | while(immr->im_cpm.cp_cpcr & CPM_CR_FLG); | |
225 | immr->im_cpm.cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE, | |
8bde7f77 WD |
226 | CPM_CR_ENET_SBLOCK, |
227 | 0x0c, | |
228 | CPM_CR_INIT_TRX) | CPM_CR_FLG; | |
fe8c2806 WD |
229 | |
230 | /* 24.21 - (8-18): Set up parameter RAM */ | |
231 | pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */ | |
232 | pram_ptr->sen_alec = 0x0; /* Align Error Counter (unused) */ | |
233 | pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */ | |
234 | ||
235 | pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */ | |
236 | ||
237 | pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */ | |
238 | ||
239 | pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */ | |
240 | pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */ | |
241 | ||
242 | pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */ | |
243 | pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */ | |
244 | ||
245 | pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */ | |
246 | pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */ | |
247 | pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ | |
248 | pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ | |
249 | ||
250 | # define ea bis->bi_enetaddr | |
251 | pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; | |
252 | pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; | |
253 | pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; | |
254 | # undef ea | |
255 | ||
256 | pram_ptr->sen_pper = 0x0; /* Persistence (unused) */ | |
257 | ||
258 | pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */ | |
259 | pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */ | |
260 | pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */ | |
261 | pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */ | |
262 | ||
263 | pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */ | |
264 | pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */ | |
265 | pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */ | |
266 | ||
fe8c2806 WD |
267 | /* 24.21 - (19): Initialize RxBD */ |
268 | for (i = 0; i < PKTBUFSRX; i++) | |
269 | { | |
8bde7f77 WD |
270 | rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; |
271 | rtx->rxbd[i].cbd_datlen = 0; /* Reset */ | |
272 | rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i]; | |
fe8c2806 WD |
273 | } |
274 | ||
275 | rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; | |
276 | ||
277 | /* 24.21 - (20): Initialize TxBD */ | |
278 | for (i = 0; i < TX_BUF_CNT; i++) | |
279 | { | |
8bde7f77 WD |
280 | rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD | |
281 | BD_ENET_TX_LAST | | |
282 | BD_ENET_TX_TC); | |
283 | rtx->txbd[i].cbd_datlen = 0; /* Reset */ | |
284 | rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0]; | |
fe8c2806 WD |
285 | } |
286 | ||
287 | rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; | |
288 | ||
289 | /* 24.21 - (21): Write 0xffff to SCCE */ | |
290 | immr->im_scc[CONFIG_ETHER_INDEX-1].scc_scce = ~(0x0); | |
291 | ||
292 | /* 24.21 - (22): Write to SCCM to enable TXE, RXF, TXB events */ | |
293 | immr->im_scc[CONFIG_ETHER_INDEX-1].scc_sccm = (SCCE_ENET_TXE | | |
8bde7f77 WD |
294 | SCCE_ENET_RXF | |
295 | SCCE_ENET_TXB); | |
fe8c2806 WD |
296 | |
297 | /* 24.21 - (23): we don't use ethernet interrupts */ | |
298 | ||
299 | /* 24.21 - (24): Clear GSMR_H to enable normal operations */ | |
300 | immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrh = 0; | |
301 | ||
302 | /* 24.21 - (25): Clear GSMR_L to enable normal operations */ | |
303 | immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl = (SCC_GSMRL_TCI | | |
8bde7f77 WD |
304 | SCC_GSMRL_TPL_48 | |
305 | SCC_GSMRL_TPP_10 | | |
306 | SCC_GSMRL_MODE_ENET); | |
fe8c2806 WD |
307 | |
308 | /* 24.21 - (26): Initialize DSR */ | |
309 | immr->im_scc[CONFIG_ETHER_INDEX-1].scc_dsr = 0xd555; | |
310 | ||
311 | /* 24.21 - (27): Initialize PSMR2 | |
312 | * | |
313 | * Settings: | |
314 | * CRC = 32-Bit CCITT | |
315 | * NIB = Begin searching for SFD 22 bits after RENA | |
316 | * FDE = Full Duplex Enable | |
317 | * BRO = Reject broadcast packets | |
318 | * PROMISCOUS = Catch all packets regardless of dest. MAC adress | |
319 | */ | |
320 | immr->im_scc[CONFIG_ETHER_INDEX-1].scc_psmr = SCC_PSMR_ENCRC | | |
321 | SCC_PSMR_NIB22 | | |
322 | #if defined(CONFIG_SCC_ENET_FULL_DUPLEX) | |
323 | SCC_PSMR_FDE | | |
324 | #endif | |
325 | #if defined(CONFIG_SCC_ENET_NO_BROADCAST) | |
326 | SCC_PSMR_BRO | | |
327 | #endif | |
328 | #if defined(CONFIG_SCC_ENET_PROMISCOUS) | |
329 | SCC_PSMR_PRO | | |
330 | #endif | |
331 | 0; | |
332 | ||
333 | /* 24.21 - (28): Write to GSMR_L to enable SCC */ | |
334 | immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR | | |
8bde7f77 | 335 | SCC_GSMRL_ENT); |
fe8c2806 | 336 | |
48b42616 | 337 | return 0; |
fe8c2806 WD |
338 | } |
339 | ||
340 | ||
fe8c2806 WD |
341 | void eth_halt(void) |
342 | { | |
6d0f6bcf | 343 | volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
fe8c2806 | 344 | immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR | |
8bde7f77 | 345 | SCC_GSMRL_ENT); |
fe8c2806 WD |
346 | } |
347 | ||
348 | #if 0 | |
349 | void restart(void) | |
350 | { | |
6d0f6bcf | 351 | volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
fe8c2806 | 352 | immr->im_cpm.cp_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR | |
8bde7f77 | 353 | SCC_GSMRL_ENT); |
fe8c2806 WD |
354 | } |
355 | #endif | |
356 | ||
068b60a0 | 357 | #endif |