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efee1709 WD |
1 | /* |
2 | * Copyright (C) 2000 Murray Jensen <Murray.Jensen@cmst.csiro.au> | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <config.h> | |
24 | #include <command.h> | |
25 | #include <mpc8260.h> | |
26 | #include <version.h> | |
27 | ||
28 | #define CONFIG_8260 1 /* needed for Linux kernel header files */ | |
29 | #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ | |
30 | ||
31 | #include <ppc_asm.tmpl> | |
32 | #include <ppc_defs.h> | |
33 | ||
34 | #include <asm/cache.h> | |
35 | #include <asm/mmu.h> | |
36 | ||
4431283c | 37 | #if defined(CONFIG_CMD_KGDB) |
efee1709 WD |
38 | |
39 | /* | |
40 | * cache flushing routines for kgdb | |
41 | */ | |
42 | ||
43 | .globl kgdb_flush_cache_all | |
44 | kgdb_flush_cache_all: | |
45 | mfspr r3, HID0 | |
46 | ori r3, r3, HID0_ICFI|HID0_DCI /* Invalidate All */ | |
47 | SYNC | |
48 | mtspr HID0, r3 | |
49 | blr | |
50 | ||
51 | .globl kgdb_flush_cache_range | |
52 | kgdb_flush_cache_range: | |
6d0f6bcf | 53 | li r5,CONFIG_SYS_CACHELINE_SIZE-1 |
efee1709 WD |
54 | andc r3,r3,r5 |
55 | subf r4,r3,r4 | |
56 | add r4,r4,r5 | |
6d0f6bcf | 57 | srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT |
efee1709 WD |
58 | beqlr |
59 | mtctr r4 | |
60 | mr r6,r3 | |
61 | 1: dcbst 0,r3 | |
6d0f6bcf | 62 | addi r3,r3,CONFIG_SYS_CACHELINE_SIZE |
efee1709 WD |
63 | bdnz 1b |
64 | sync /* wait for dcbst's to get to ram */ | |
65 | mtctr r4 | |
66 | 2: icbi 0,r6 | |
6d0f6bcf | 67 | addi r6,r6,CONFIG_SYS_CACHELINE_SIZE |
efee1709 WD |
68 | bdnz 2b |
69 | SYNC | |
70 | blr | |
71 | ||
068b60a0 | 72 | #endif |