[people/ms/u-boot.git] / cpu / mpc85xx / commproc.c

/*
 * Adapted for Motorola MPC8560 chips
 * Xianghua Xiao <x.xiao@motorola.com>
 *
 * This file is based on "arch/ppc/8260_io/commproc.c" - here is it's
 * copyright notice:
 *
 * General Purpose functions for the global management of the
 * 8220 Communication Processor Module.
 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
 *	2.3.99 Updates
 * Copyright (c) 2003 Motorola,Inc.
 *
 * In addition to the individual control of the communication
 * channels, there are a few functions that globally affect the
 * communication processor.
 *
 * Buffer descriptors must be allocated from the dual ported memory
 * space.  The allocator for that is here.  When the communication
 * process is reset, we reclaim the memory available.  There is
 * currently no deallocator for this memory.
 */
#include <common.h>
#include <asm/cpm_85xx.h>

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_CPM2)
/*
 * because we have stack and init data in dual port ram
 * we must reduce the size
 */
#undef	CPM_DATAONLY_SIZE
#define CPM_DATAONLY_SIZE	((uint)(8 * 1024) - CPM_DATAONLY_BASE)

void
m8560_cpm_reset(void)
{
	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
	volatile ulong count;

	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);

	/* Reclaim the DP memory for our use.
	*/
	gd->dp_alloc_base = CPM_DATAONLY_BASE;
	gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE;

	/*
	 * Reset CPM
	 */
	cpm->im_cpm_cp.cpcr = CPM_CR_RST;
	count = 0;
	do {			/* Spin until command processed		*/
		__asm__ __volatile__ ("eieio");
	} while ((cpm->im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000);
}

/* Allocate some memory from the dual ported ram.
 * To help protocols with object alignment restrictions, we do that
 * if they ask.
 */
uint
m8560_cpm_dpalloc(uint size, uint align)
{
	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
	uint	retloc;
	uint	align_mask, off;
	uint	savebase;

	align_mask = align - 1;
	savebase = gd->dp_alloc_base;

	if ((off = (gd->dp_alloc_base & align_mask)) != 0)
		gd->dp_alloc_base += (align - off);

	if ((off = size & align_mask) != 0)
		size += align - off;

	if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) {
		gd->dp_alloc_base = savebase;
		panic("m8560_cpm_dpalloc: ran out of dual port ram!");
	}

	retloc = gd->dp_alloc_base;
	gd->dp_alloc_base += size;

	memset((void *)&(cpm->im_dprambase[retloc]), 0, size);

	return(retloc);
}

/* We also own one page of host buffer space for the allocation of
 * UART "fifos" and the like.
 */
uint
m8560_cpm_hostalloc(uint size, uint align)
{
	/* the host might not even have RAM yet - just use dual port RAM */
	return (m8560_cpm_dpalloc(size, align));
}

/* Set a baud rate generator.  This needs lots of work.  There are
 * eight BRGs, which can be connected to the CPM channels or output
 * as clocks.  The BRGs are in two different block of internal
 * memory mapped space.
 * The baud rate clock is the system clock divided by something.
 * It was set up long ago during the initial boot phase and is
 * is given to us.
 * Baud rate clocks are zero-based in the driver code (as that maps
 * to port numbers).  Documentation uses 1-based numbering.
 */
#define BRG_INT_CLK	gd->brg_clk
#define BRG_UART_CLK	((BRG_INT_CLK + 15) / 16)

/* This function is used by UARTS, or anything else that uses a 16x
 * oversampled clock.
 */
void
m8560_cpm_setbrg(uint brg, uint rate)
{
	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
	volatile uint	*bp;

	/* This is good enough to get SMCs running.....
	*/
	if (brg < 4) {
		bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
	}
	else {
		bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
		brg -= 4;
	}
	bp += brg;
	*bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
}

/* This function is used to set high speed synchronous baud rate
 * clocks.
 */
void
m8560_cpm_fastbrg(uint brg, uint rate, int div16)
{
	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
	volatile uint	*bp;

	/* This is good enough to get SMCs running.....
	*/
	if (brg < 4) {
		bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
	}
	else {
		bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
		brg -= 4;
	}
	bp += brg;
	*bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
	if (div16)
		*bp |= CPM_BRG_DIV16;
}

/* This function is used to set baud rate generators using an external
 * clock source and 16x oversampling.
 */

void
m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
{
	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
	volatile uint	*bp;

	if (brg < 4) {
		bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
	}
	else {
		bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
		brg -= 4;
	}
	bp += brg;
	*bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
	if (pinsel == 0)
		*bp |= CPM_BRG_EXTC_CLK3_9;
	else
		*bp |= CPM_BRG_EXTC_CLK5_15;
}

#ifdef CONFIG_POST

void post_word_store (ulong a)
{
	volatile ulong *save_addr =
		(volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR);

	*save_addr = a;
}

ulong post_word_load (void)
{
	volatile ulong *save_addr =
		(volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR);

	return *save_addr;
}

#endif	/* CONFIG_POST */

#endif /* CONFIG_CPM2 */
Commit	Line	Data
42d1f039 WD	1	/*
	2	* Adapted for Motorola MPC8560 chips
	3	* Xianghua Xiao <x.xiao@motorola.com>
	4	*
	5	* This file is based on "arch/ppc/8260_io/commproc.c" - here is it's
	6	* copyright notice:
	7	*
	8	* General Purpose functions for the global management of the
	9	* 8220 Communication Processor Module.
	10	* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
	11	* Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
	12	* 2.3.99 Updates
	13	* Copyright (c) 2003 Motorola,Inc.
	14	*
	15	* In addition to the individual control of the communication
	16	* channels, there are a few functions that globally affect the
	17	* communication processor.
	18	*
	19	* Buffer descriptors must be allocated from the dual ported memory
	20	* space. The allocator for that is here. When the communication
	21	* process is reset, we reclaim the memory available. There is
	22	* currently no deallocator for this memory.
	23	*/
	24	#include <common.h>
	25	#include <asm/cpm_85xx.h>
	26
d87080b7 WD	27	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	28
9c4c5ae3	29	#if defined(CONFIG_CPM2)
42d1f039 WD	30	/*
	31	* because we have stack and init data in dual port ram
	32	* we must reduce the size
	33	*/
	34	#undef CPM_DATAONLY_SIZE
	35	#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
	36
	37	void
	38	m8560_cpm_reset(void)
	39	{
6d0f6bcf	40	volatile ccsr_cpm_t cpm = (ccsr_cpm_t )CONFIG_SYS_MPC85xx_CPM_ADDR;
42d1f039 WD	41	volatile ulong count;
42d1f039 WD	42
6d0f6bcf	43	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
42d1f039 WD	44
	45	/* Reclaim the DP memory for our use.
	46	*/
	47	gd->dp_alloc_base = CPM_DATAONLY_BASE;
	48	gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE;
	49
	50	/*
	51	* Reset CPM
	52	*/
aafeefbd	53	cpm->im_cpm_cp.cpcr = CPM_CR_RST;
42d1f039 WD	54	count = 0;
	55	do { /* Spin until command processed */
	56	__asm__ __volatile__ ("eieio");
aafeefbd	57	} while ((cpm->im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000);
42d1f039 WD	58	}
	59
	60	/* Allocate some memory from the dual ported ram.
	61	* To help protocols with object alignment restrictions, we do that
	62	* if they ask.
	63	*/
	64	uint
	65	m8560_cpm_dpalloc(uint size, uint align)
	66	{
6d0f6bcf	67	volatile ccsr_cpm_t cpm = (ccsr_cpm_t )CONFIG_SYS_MPC85xx_CPM_ADDR;
42d1f039 WD	68	uint retloc;
	69	uint align_mask, off;
	70	uint savebase;
	71
	72	align_mask = align - 1;
	73	savebase = gd->dp_alloc_base;
	74
	75	if ((off = (gd->dp_alloc_base & align_mask)) != 0)
	76	gd->dp_alloc_base += (align - off);
	77
	78	if ((off = size & align_mask) != 0)
	79	size += align - off;
	80
	81	if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) {
	82	gd->dp_alloc_base = savebase;
	83	panic("m8560_cpm_dpalloc: ran out of dual port ram!");
	84	}
	85
	86	retloc = gd->dp_alloc_base;
	87	gd->dp_alloc_base += size;
	88
aafeefbd	89	memset((void *)&(cpm->im_dprambase[retloc]), 0, size);
42d1f039 WD	90
	91	return(retloc);
	92	}
	93
	94	/* We also own one page of host buffer space for the allocation of
	95	* UART "fifos" and the like.
	96	*/
	97	uint
	98	m8560_cpm_hostalloc(uint size, uint align)
	99	{
	100	/* the host might not even have RAM yet - just use dual port RAM */
	101	return (m8560_cpm_dpalloc(size, align));
	102	}
	103
	104	/* Set a baud rate generator. This needs lots of work. There are
	105	* eight BRGs, which can be connected to the CPM channels or output
	106	* as clocks. The BRGs are in two different block of internal
	107	* memory mapped space.
	108	* The baud rate clock is the system clock divided by something.
	109	* It was set up long ago during the initial boot phase and is
	110	* is given to us.
	111	* Baud rate clocks are zero-based in the driver code (as that maps
	112	* to port numbers). Documentation uses 1-based numbering.
	113	*/
	114	#define BRG_INT_CLK gd->brg_clk
	115	#define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16)
	116
	117	/* This function is used by UARTS, or anything else that uses a 16x
	118	* oversampled clock.
	119	*/
	120	void
	121	m8560_cpm_setbrg(uint brg, uint rate)
	122	{
6d0f6bcf	123	volatile ccsr_cpm_t cpm = (ccsr_cpm_t )CONFIG_SYS_MPC85xx_CPM_ADDR;
42d1f039 WD	124	volatile uint *bp;
	125
	126	/* This is good enough to get SMCs running.....
	127	*/
	128	if (brg < 4) {
aafeefbd	129	bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
42d1f039 WD	130	}
42d1f039 WD	131	else {
aafeefbd	132	bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
42d1f039 WD	133	brg -= 4;
	134	}
	135	bp += brg;
	136	*bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)\|CPM_BRG_EN;
	137	}
	138
	139	/* This function is used to set high speed synchronous baud rate
	140	* clocks.
	141	*/
	142	void
	143	m8560_cpm_fastbrg(uint brg, uint rate, int div16)
	144	{
6d0f6bcf	145	volatile ccsr_cpm_t cpm = (ccsr_cpm_t )CONFIG_SYS_MPC85xx_CPM_ADDR;
42d1f039 WD	146	volatile uint *bp;
	147
	148	/* This is good enough to get SMCs running.....
	149	*/
	150	if (brg < 4) {
aafeefbd	151	bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
42d1f039 WD	152	}
42d1f039 WD	153	else {
aafeefbd	154	bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
42d1f039 WD	155	brg -= 4;
	156	}
	157	bp += brg;
	158	*bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)\|CPM_BRG_EN;
	159	if (div16)
	160	*bp \|= CPM_BRG_DIV16;
	161	}
	162
	163	/* This function is used to set baud rate generators using an external
	164	* clock source and 16x oversampling.
	165	*/
	166
	167	void
	168	m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
	169	{
6d0f6bcf	170	volatile ccsr_cpm_t cpm = (ccsr_cpm_t )CONFIG_SYS_MPC85xx_CPM_ADDR;
42d1f039 WD	171	volatile uint *bp;
	172
	173	if (brg < 4) {
aafeefbd	174	bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
42d1f039 WD	175	}
42d1f039 WD	176	else {
aafeefbd	177	bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
42d1f039 WD	178	brg -= 4;
	179	}
	180	bp += brg;
	181	*bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)\|CPM_BRG_EN;
	182	if (pinsel == 0)
	183	*bp \|= CPM_BRG_EXTC_CLK3_9;
	184	else
	185	*bp \|= CPM_BRG_EXTC_CLK5_15;
	186	}
	187
	188	#ifdef CONFIG_POST
	189
	190	void post_word_store (ulong a)
	191	{
	192	volatile ulong *save_addr =
6d0f6bcf	193	(volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR);
42d1f039 WD	194
	195	*save_addr = a;
	196	}
	197
	198	ulong post_word_load (void)
	199	{
	200	volatile ulong *save_addr =
6d0f6bcf	201	(volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR);
42d1f039 WD	202
	203	return *save_addr;
	204	}
	205
	206	#endif /* CONFIG_POST */
	207
9c4c5ae3	208	#endif /* CONFIG_CPM2 */