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42d1f039 | 1 | /* |
1ced1216 | 2 | * Copyright 2004,2007,2008 Freescale Semiconductor, Inc. |
42d1f039 WD |
3 | * (C) Copyright 2002, 2003 Motorola Inc. |
4 | * Xianghua Xiao (X.Xiao@motorola.com) | |
5 | * | |
6 | * (C) Copyright 2000 | |
7 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
75b9d4ae | 28 | #include <config.h> |
42d1f039 WD |
29 | #include <common.h> |
30 | #include <watchdog.h> | |
31 | #include <command.h> | |
75b9d4ae | 32 | #include <tsec.h> |
42d1f039 | 33 | #include <asm/cache.h> |
740280e6 | 34 | #include <asm/io.h> |
42d1f039 | 35 | |
591933ca JY |
36 | DECLARE_GLOBAL_DATA_PTR; |
37 | ||
4dbdb768 KG |
38 | struct cpu_type cpu_type_list [] = { |
39 | CPU_TYPE_ENTRY(8533, 8533), | |
40 | CPU_TYPE_ENTRY(8533, 8533_E), | |
ef50d6c0 KG |
41 | CPU_TYPE_ENTRY(8536, 8536), |
42 | CPU_TYPE_ENTRY(8536, 8536_E), | |
4dbdb768 KG |
43 | CPU_TYPE_ENTRY(8540, 8540), |
44 | CPU_TYPE_ENTRY(8541, 8541), | |
45 | CPU_TYPE_ENTRY(8541, 8541_E), | |
46 | CPU_TYPE_ENTRY(8543, 8543), | |
47 | CPU_TYPE_ENTRY(8543, 8543_E), | |
48 | CPU_TYPE_ENTRY(8544, 8544), | |
49 | CPU_TYPE_ENTRY(8544, 8544_E), | |
50 | CPU_TYPE_ENTRY(8545, 8545), | |
51 | CPU_TYPE_ENTRY(8545, 8545_E), | |
52 | CPU_TYPE_ENTRY(8547, 8547_E), | |
53 | CPU_TYPE_ENTRY(8548, 8548), | |
54 | CPU_TYPE_ENTRY(8548, 8548_E), | |
55 | CPU_TYPE_ENTRY(8555, 8555), | |
56 | CPU_TYPE_ENTRY(8555, 8555_E), | |
57 | CPU_TYPE_ENTRY(8560, 8560), | |
58 | CPU_TYPE_ENTRY(8567, 8567), | |
59 | CPU_TYPE_ENTRY(8567, 8567_E), | |
60 | CPU_TYPE_ENTRY(8568, 8568), | |
61 | CPU_TYPE_ENTRY(8568, 8568_E), | |
62 | CPU_TYPE_ENTRY(8572, 8572), | |
63 | CPU_TYPE_ENTRY(8572, 8572_E), | |
1ced1216 AF |
64 | }; |
65 | ||
96026d42 | 66 | struct cpu_type *identify_cpu(u32 ver) |
4dbdb768 KG |
67 | { |
68 | int i; | |
69 | for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) | |
70 | if (cpu_type_list[i].soc_ver == ver) | |
71 | return &cpu_type_list[i]; | |
1ced1216 | 72 | |
4dbdb768 KG |
73 | return NULL; |
74 | } | |
1ced1216 | 75 | |
42d1f039 WD |
76 | int checkcpu (void) |
77 | { | |
97d80fc3 WD |
78 | sys_info_t sysinfo; |
79 | uint lcrr; /* local bus clock ratio register */ | |
80 | uint clkdiv; /* clock divider portion of lcrr */ | |
81 | uint pvr, svr; | |
d9b94f28 | 82 | uint fam; |
97d80fc3 WD |
83 | uint ver; |
84 | uint major, minor; | |
4dbdb768 | 85 | struct cpu_type *cpu; |
ee1e35be | 86 | #ifdef CONFIG_DDR_CLK_FREQ |
6d0f6bcf | 87 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
c0391111 JJ |
88 | u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) |
89 | >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; | |
ee1e35be KG |
90 | #else |
91 | u32 ddr_ratio = 0; | |
92 | #endif | |
97d80fc3 | 93 | |
97d80fc3 | 94 | svr = get_svr(); |
1ced1216 | 95 | ver = SVR_SOC_VER(svr); |
97d80fc3 | 96 | major = SVR_MAJ(svr); |
ef50d6c0 KG |
97 | #ifdef CONFIG_MPC8536 |
98 | major &= 0x7; /* the msb of this nibble is a mfg code */ | |
99 | #endif | |
97d80fc3 | 100 | minor = SVR_MIN(svr); |
42d1f039 | 101 | |
6c9e789e | 102 | puts("CPU: "); |
1ced1216 | 103 | |
4dbdb768 KG |
104 | cpu = identify_cpu(ver); |
105 | if (cpu) { | |
106 | puts(cpu->name); | |
1ced1216 | 107 | |
06b4186c | 108 | if (IS_E_PROCESSOR(svr)) |
4dbdb768 KG |
109 | puts("E"); |
110 | } else { | |
97d80fc3 | 111 | puts("Unknown"); |
4dbdb768 | 112 | } |
1ced1216 | 113 | |
97d80fc3 WD |
114 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); |
115 | ||
6c9e789e | 116 | pvr = get_pvr(); |
d9b94f28 | 117 | fam = PVR_FAM(pvr); |
6c9e789e WD |
118 | ver = PVR_VER(pvr); |
119 | major = PVR_MAJ(pvr); | |
120 | minor = PVR_MIN(pvr); | |
121 | ||
122 | printf("Core: "); | |
d9b94f28 JL |
123 | switch (fam) { |
124 | case PVR_FAM(PVR_85xx): | |
6c9e789e WD |
125 | puts("E500"); |
126 | break; | |
127 | default: | |
128 | puts("Unknown"); | |
129 | break; | |
130 | } | |
131 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); | |
132 | ||
97d80fc3 WD |
133 | get_sys_info(&sysinfo); |
134 | ||
d9b94f28 | 135 | puts("Clock Configuration:\n"); |
022f1216 KG |
136 | printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000)); |
137 | printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000)); | |
ee1e35be | 138 | |
d4357932 KG |
139 | switch (ddr_ratio) { |
140 | case 0x0: | |
e9ea6799 | 141 | printf(" DDR:%4lu MHz (%lu MT/s data rate), ", |
022f1216 | 142 | DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000)); |
d4357932 KG |
143 | break; |
144 | case 0x7: | |
e9ea6799 | 145 | printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ", |
022f1216 | 146 | DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000)); |
d4357932 KG |
147 | break; |
148 | default: | |
e9ea6799 | 149 | printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ", |
022f1216 | 150 | DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000)); |
d4357932 KG |
151 | break; |
152 | } | |
97d80fc3 | 153 | |
6d0f6bcf JCPV |
154 | #if defined(CONFIG_SYS_LBC_LCRR) |
155 | lcrr = CONFIG_SYS_LBC_LCRR; | |
97d80fc3 WD |
156 | #else |
157 | { | |
6d0f6bcf | 158 | volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); |
97d80fc3 WD |
159 | |
160 | lcrr = lbc->lcrr; | |
161 | } | |
162 | #endif | |
163 | clkdiv = lcrr & 0x0f; | |
164 | if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { | |
ef50d6c0 KG |
165 | #if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \ |
166 | defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536) | |
d9b94f28 JL |
167 | /* |
168 | * Yes, the entire PQ38 family use the same | |
169 | * bit-representation for twice the clock divider values. | |
170 | */ | |
171 | clkdiv *= 2; | |
172 | #endif | |
97d80fc3 | 173 | printf("LBC:%4lu MHz\n", |
022f1216 | 174 | DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv); |
97d80fc3 | 175 | } else { |
6c9e789e | 176 | printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr); |
97d80fc3 | 177 | } |
42d1f039 | 178 | |
1ced1216 | 179 | #ifdef CONFIG_CPM2 |
6beecfbb | 180 | printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); |
1ced1216 | 181 | #endif |
97d80fc3 | 182 | |
6c9e789e | 183 | puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); |
42d1f039 WD |
184 | |
185 | return 0; | |
186 | } | |
187 | ||
188 | ||
189 | /* ------------------------------------------------------------------------- */ | |
190 | ||
191 | int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) | |
192 | { | |
96629cba ZR |
193 | uint pvr; |
194 | uint ver; | |
793670c3 SP |
195 | unsigned long val, msr; |
196 | ||
96629cba ZR |
197 | pvr = get_pvr(); |
198 | ver = PVR_VER(pvr); | |
793670c3 | 199 | |
96629cba ZR |
200 | if (ver & 1){ |
201 | /* e500 v2 core has reset control register */ | |
202 | volatile unsigned int * rstcr; | |
6d0f6bcf | 203 | rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0); |
2f15278c | 204 | *rstcr = 0x2; /* HRESET_REQ */ |
793670c3 SP |
205 | udelay(100); |
206 | } | |
207 | ||
42d1f039 | 208 | /* |
793670c3 | 209 | * Fallthrough if the code above failed |
42d1f039 WD |
210 | * Initiate hard reset in debug control register DBCR0 |
211 | * Make sure MSR[DE] = 1 | |
212 | */ | |
df90968b | 213 | |
793670c3 SP |
214 | msr = mfmsr (); |
215 | msr |= MSR_DE; | |
216 | mtmsr (msr); | |
217 | ||
218 | val = mfspr(DBCR0); | |
219 | val |= 0x70000000; | |
220 | mtspr(DBCR0,val); | |
df90968b | 221 | |
42d1f039 WD |
222 | return 1; |
223 | } | |
224 | ||
225 | ||
226 | /* | |
227 | * Get timebase clock frequency | |
228 | */ | |
229 | unsigned long get_tbclk (void) | |
230 | { | |
591933ca | 231 | return (gd->bus_clk + 4UL)/8UL; |
42d1f039 WD |
232 | } |
233 | ||
234 | ||
235 | #if defined(CONFIG_WATCHDOG) | |
236 | void | |
237 | watchdog_reset(void) | |
238 | { | |
239 | int re_enable = disable_interrupts(); | |
240 | reset_85xx_watchdog(); | |
241 | if (re_enable) enable_interrupts(); | |
242 | } | |
243 | ||
244 | void | |
245 | reset_85xx_watchdog(void) | |
246 | { | |
247 | /* | |
248 | * Clear TSR(WIS) bit by writing 1 | |
249 | */ | |
250 | unsigned long val; | |
03b81b48 AF |
251 | val = mfspr(SPRN_TSR); |
252 | val |= TSR_WIS; | |
253 | mtspr(SPRN_TSR, val); | |
42d1f039 WD |
254 | } |
255 | #endif /* CONFIG_WATCHDOG */ | |
256 | ||
257 | #if defined(CONFIG_DDR_ECC) | |
42d1f039 | 258 | void dma_init(void) { |
6d0f6bcf | 259 | volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); |
42d1f039 WD |
260 | |
261 | dma->satr0 = 0x02c40000; | |
262 | dma->datr0 = 0x02c40000; | |
03b81b48 | 263 | dma->sr0 = 0xfffffff; /* clear any errors */ |
42d1f039 WD |
264 | asm("sync; isync; msync"); |
265 | return; | |
266 | } | |
267 | ||
268 | uint dma_check(void) { | |
6d0f6bcf | 269 | volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); |
42d1f039 WD |
270 | volatile uint status = dma->sr0; |
271 | ||
272 | /* While the channel is busy, spin */ | |
273 | while((status & 4) == 4) { | |
274 | status = dma->sr0; | |
275 | } | |
276 | ||
03b81b48 AF |
277 | /* clear MR0[CS] channel start bit */ |
278 | dma->mr0 &= 0x00000001; | |
279 | asm("sync;isync;msync"); | |
280 | ||
42d1f039 WD |
281 | if (status != 0) { |
282 | printf ("DMA Error: status = %x\n", status); | |
283 | } | |
284 | return status; | |
285 | } | |
286 | ||
287 | int dma_xfer(void *dest, uint count, void *src) { | |
6d0f6bcf | 288 | volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); |
42d1f039 WD |
289 | |
290 | dma->dar0 = (uint) dest; | |
291 | dma->sar0 = (uint) src; | |
292 | dma->bcr0 = count; | |
293 | dma->mr0 = 0xf000004; | |
294 | asm("sync;isync;msync"); | |
295 | dma->mr0 = 0xf000005; | |
296 | asm("sync;isync;msync"); | |
297 | return dma_check(); | |
298 | } | |
299 | #endif | |
75b9d4ae | 300 | |
740280e6 | 301 | /* |
59f63058 SP |
302 | * Configures a UPM. The function requires the respective MxMR to be set |
303 | * before calling this function. "size" is the number or entries, not a sizeof. | |
740280e6 SP |
304 | */ |
305 | void upmconfig (uint upm, uint * table, uint size) | |
306 | { | |
307 | int i, mdr, mad, old_mad = 0; | |
308 | volatile u32 *mxmr; | |
6d0f6bcf | 309 | volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); |
740280e6 SP |
310 | volatile u32 *brp,*orp; |
311 | volatile u8* dummy = NULL; | |
312 | int upmmask; | |
313 | ||
314 | switch (upm) { | |
315 | case UPMA: | |
316 | mxmr = &lbc->mamr; | |
317 | upmmask = BR_MS_UPMA; | |
318 | break; | |
319 | case UPMB: | |
320 | mxmr = &lbc->mbmr; | |
321 | upmmask = BR_MS_UPMB; | |
322 | break; | |
323 | case UPMC: | |
324 | mxmr = &lbc->mcmr; | |
325 | upmmask = BR_MS_UPMC; | |
326 | break; | |
327 | default: | |
328 | printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm); | |
329 | hang(); | |
330 | } | |
331 | ||
332 | /* Find the address for the dummy write transaction */ | |
333 | for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8; | |
334 | i++, brp += 2, orp += 2) { | |
e093a247 | 335 | |
740280e6 | 336 | /* Look for a valid BR with selected UPM */ |
59f63058 SP |
337 | if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) { |
338 | dummy = (volatile u8*)(in_be32(brp) & BR_BA); | |
740280e6 SP |
339 | break; |
340 | } | |
341 | } | |
342 | ||
343 | if (i == 8) { | |
344 | printf("Error: %s() could not find matching BR\n", __FUNCTION__); | |
345 | hang(); | |
346 | } | |
347 | ||
348 | for (i = 0; i < size; i++) { | |
349 | /* 1 */ | |
59f63058 | 350 | out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i); |
740280e6 SP |
351 | /* 2 */ |
352 | out_be32(&lbc->mdr, table[i]); | |
353 | /* 3 */ | |
354 | mdr = in_be32(&lbc->mdr); | |
355 | /* 4 */ | |
356 | *(volatile u8 *)dummy = 0; | |
357 | /* 5 */ | |
358 | do { | |
59f63058 | 359 | mad = in_be32(mxmr) & MxMR_MAD_MSK; |
740280e6 SP |
360 | } while (mad <= old_mad && !(!mad && i == (size-1))); |
361 | old_mad = mad; | |
362 | } | |
59f63058 | 363 | out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM); |
740280e6 | 364 | } |
dd35479a | 365 | |
dd35479a | 366 | |
75b9d4ae AF |
367 | /* |
368 | * Initializes on-chip ethernet controllers. | |
369 | * to override, implement board_eth_init() | |
370 | */ | |
dd35479a BW |
371 | int cpu_eth_init(bd_t *bis) |
372 | { | |
75b9d4ae AF |
373 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85xx_FEC) |
374 | tsec_standard_init(bis); | |
dd35479a | 375 | #endif |
75b9d4ae | 376 | |
dd35479a BW |
377 | return 0; |
378 | } |