[people/ms/u-boot.git] / cpu / mpc85xx / cpu_init.c

/*
 * (C) Copyright 2003 Motorola Inc.
 * Modified by Xianghua Xiao, X.Xiao@motorola.com
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>
#include <asm/processor.h>
#include <ioports.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;


#ifdef CONFIG_CPM2
static void config_8560_ioports (volatile immap_t * immr)
{
	int portnum;

	for (portnum = 0; portnum < 4; portnum++) {
		uint pmsk = 0,
		     ppar = 0,
		     psor = 0,
		     pdir = 0,
		     podr = 0,
		     pdat = 0;
		iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
		iop_conf_t *eiopc = iopc + 32;
		uint msk = 1;

		/*
		 * NOTE:
		 * index 0 refers to pin 31,
		 * index 31 refers to pin 0
		 */
		while (iopc < eiopc) {
			if (iopc->conf) {
				pmsk |= msk;
				if (iopc->ppar)
					ppar |= msk;
				if (iopc->psor)
					psor |= msk;
				if (iopc->pdir)
					pdir |= msk;
				if (iopc->podr)
					podr |= msk;
				if (iopc->pdat)
					pdat |= msk;
			}

			msk <<= 1;
			iopc++;
		}

		if (pmsk != 0) {
			volatile ioport_t *iop = ioport_addr (immr, portnum);
			uint tpmsk = ~pmsk;

			/*
			 * the (somewhat confused) paragraph at the
			 * bottom of page 35-5 warns that there might
			 * be "unknown behaviour" when programming
			 * PSORx and PDIRx, if PPARx = 1, so I
			 * decided this meant I had to disable the
			 * dedicated function first, and enable it
			 * last.
			 */
			iop->ppar &= tpmsk;
			iop->psor = (iop->psor & tpmsk) | psor;
			iop->podr = (iop->podr & tpmsk) | podr;
			iop->pdat = (iop->pdat & tpmsk) | pdat;
			iop->pdir = (iop->pdir & tpmsk) | pdir;
			iop->ppar |= ppar;
		}
	}
}
#endif

/*
 * Breathe some life into the CPU...
 *
 * Set up the memory map
 * initialize a bunch of registers
 */

void cpu_init_f (void)
{
	volatile immap_t    *immap = (immap_t *)CFG_IMMR;
	volatile ccsr_lbc_t *memctl = &immap->im_lbc;
	extern void m8560_cpm_reset (void);

	/* Pointer is writable since we allocated a register for it */
	gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);

	/* Clear initial global data */
	memset ((void *) gd, 0, sizeof (gd_t));


#ifdef CONFIG_CPM2
	config_8560_ioports(immap);
#endif

	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
	 * addresses - these have to be modified later when FLASH size
	 * has been determined
	 */
#if defined(CFG_OR0_REMAP)
	memctl->or0 = CFG_OR0_REMAP;
#endif
#if defined(CFG_OR1_REMAP)
	memctl->or1 = CFG_OR1_REMAP;
#endif

	/* now restrict to preliminary range */
#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
	memctl->br0 = CFG_BR0_PRELIM;
	memctl->or0 = CFG_OR0_PRELIM;
#endif

#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
	memctl->or1 = CFG_OR1_PRELIM;
	memctl->br1 = CFG_BR1_PRELIM;
#endif

#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
	memctl->or2 = CFG_OR2_PRELIM;
	memctl->br2 = CFG_BR2_PRELIM;
#endif

#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
	memctl->or3 = CFG_OR3_PRELIM;
	memctl->br3 = CFG_BR3_PRELIM;
#endif

#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
	memctl->or4 = CFG_OR4_PRELIM;
	memctl->br4 = CFG_BR4_PRELIM;
#endif

#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
	memctl->or5 = CFG_OR5_PRELIM;
	memctl->br5 = CFG_BR5_PRELIM;
#endif

#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
	memctl->or6 = CFG_OR6_PRELIM;
	memctl->br6 = CFG_BR6_PRELIM;
#endif

#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
	memctl->or7 = CFG_OR7_PRELIM;
	memctl->br7 = CFG_BR7_PRELIM;
#endif

#if defined(CONFIG_CPM2)
	m8560_cpm_reset();
#endif
}


/*
 * Initialize L2 as cache.
 *
 * The newer 8548, etc, parts have twice as much cache, but
 * use the same bit-encoding as the older 8555, etc, parts.
 *
 * FIXME: Use PVR_VER(pvr) == 1 test here instead of SVR_VER()?
 */

int cpu_init_r(void)
{
#if defined(CONFIG_L2_CACHE)
	volatile immap_t *immap = (immap_t *)CFG_IMMR;
	volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
	volatile uint cache_ctl;
	uint svr, ver;

	svr = get_svr();
	ver = SVR_VER(svr);

	asm("msync;isync");
	cache_ctl = l2cache->l2ctl;

	switch (cache_ctl & 0x30000000) {
	case 0x20000000:
		if (ver == SVR_8548 || ver == SVR_8548_E) {
			printf ("L2 cache 512KB:");
		} else {
			printf ("L2 cache 256KB:");
		}
		break;
	case 0x00000000:
	case 0x10000000:
	case 0x30000000:
	default:
		printf ("L2 cache unknown size (0x%08x)\n", cache_ctl);
		return -1;
	}

	asm("msync;isync");
	l2cache->l2ctl = 0x68000000; /* invalidate */
	cache_ctl = l2cache->l2ctl;
	asm("msync;isync");

	l2cache->l2ctl = 0xa8000000; /* enable 256KB L2 cache */
	cache_ctl = l2cache->l2ctl;
	asm("msync;isync");

	printf(" enabled\n");
#else
	printf("L2 cache: disabled\n");
#endif

	return 0;
}
Commit	Line	Data
42d1f039 WD	1	/*
	2	* (C) Copyright 2003 Motorola Inc.
	3	* Modified by Xianghua Xiao, X.Xiao@motorola.com
	4	*
	5	* (C) Copyright 2000
	6	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <common.h>
	28	#include <watchdog.h>
	29	#include <asm/processor.h>
	30	#include <ioports.h>
	31	#include <asm/io.h>
	32
d87080b7 WD	33	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	34
40d5fa35	35
9c4c5ae3	36	#ifdef CONFIG_CPM2
42d1f039 WD	37	static void config_8560_ioports (volatile immap_t * immr)
	38	{
	39	int portnum;
	40
	41	for (portnum = 0; portnum < 4; portnum++) {
	42	uint pmsk = 0,
	43	ppar = 0,
	44	psor = 0,
	45	pdir = 0,
	46	podr = 0,
	47	pdat = 0;
	48	iop_conf_t iopc = (iop_conf_t ) & iop_conf_tab[portnum][0];
	49	iop_conf_t *eiopc = iopc + 32;
	50	uint msk = 1;
	51
	52	/*
	53	* NOTE:
	54	* index 0 refers to pin 31,
	55	* index 31 refers to pin 0
	56	*/
	57	while (iopc < eiopc) {
	58	if (iopc->conf) {
	59	pmsk \|= msk;
	60	if (iopc->ppar)
	61	ppar \|= msk;
	62	if (iopc->psor)
	63	psor \|= msk;
	64	if (iopc->pdir)
	65	pdir \|= msk;
	66	if (iopc->podr)
	67	podr \|= msk;
	68	if (iopc->pdat)
	69	pdat \|= msk;
	70	}
	71
	72	msk <<= 1;
	73	iopc++;
	74	}
	75
	76	if (pmsk != 0) {
	77	volatile ioport_t *iop = ioport_addr (immr, portnum);
	78	uint tpmsk = ~pmsk;
	79
	80	/*
	81	* the (somewhat confused) paragraph at the
	82	* bottom of page 35-5 warns that there might
	83	* be "unknown behaviour" when programming
	84	* PSORx and PDIRx, if PPARx = 1, so I
	85	* decided this meant I had to disable the
	86	* dedicated function first, and enable it
	87	* last.
	88	*/
	89	iop->ppar &= tpmsk;
	90	iop->psor = (iop->psor & tpmsk) \| psor;
	91	iop->podr = (iop->podr & tpmsk) \| podr;
	92	iop->pdat = (iop->pdat & tpmsk) \| pdat;
	93	iop->pdir = (iop->pdir & tpmsk) \| pdir;
	94	iop->ppar \|= ppar;
	95	}
	96	}
	97	}
	98	#endif
	99
	100	/*
101	* Breathe some life into the CPU...
102	*
103	* Set up the memory map
104	* initialize a bunch of registers
105	*/
106
107	void cpu_init_f (void)
108	{
42d1f039 WD	109	volatile immap_t immap = (immap_t )CFG_IMMR;
	110	volatile ccsr_lbc_t *memctl = &immap->im_lbc;
	111	extern void m8560_cpm_reset (void);
	112
	113	/* Pointer is writable since we allocated a register for it */
	114	gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
	115
	116	/* Clear initial global data */
	117	memset ((void *) gd, 0, sizeof (gd_t));
	118
	119
9c4c5ae3	120	#ifdef CONFIG_CPM2
42d1f039 WD	121	config_8560_ioports(immap);
	122	#endif
	123
	124	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
	125	* addresses - these have to be modified later when FLASH size
	126	* has been determined
	127	*/
	128	#if defined(CFG_OR0_REMAP)
	129	memctl->or0 = CFG_OR0_REMAP;
	130	#endif
	131	#if defined(CFG_OR1_REMAP)
	132	memctl->or1 = CFG_OR1_REMAP;
	133	#endif
	134
	135	/* now restrict to preliminary range */
	136	#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
	137	memctl->br0 = CFG_BR0_PRELIM;
	138	memctl->or0 = CFG_OR0_PRELIM;
	139	#endif
	140
	141	#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
	142	memctl->or1 = CFG_OR1_PRELIM;
	143	memctl->br1 = CFG_BR1_PRELIM;
	144	#endif
	145
42d1f039 WD	146	#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
	147	memctl->or2 = CFG_OR2_PRELIM;
	148	memctl->br2 = CFG_BR2_PRELIM;
	149	#endif
42d1f039 WD	150
	151	#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
	152	memctl->or3 = CFG_OR3_PRELIM;
	153	memctl->br3 = CFG_BR3_PRELIM;
	154	#endif
	155
	156	#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
	157	memctl->or4 = CFG_OR4_PRELIM;
	158	memctl->br4 = CFG_BR4_PRELIM;
	159	#endif
	160
	161	#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
	162	memctl->or5 = CFG_OR5_PRELIM;
	163	memctl->br5 = CFG_BR5_PRELIM;
	164	#endif
	165
	166	#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
	167	memctl->or6 = CFG_OR6_PRELIM;
	168	memctl->br6 = CFG_BR6_PRELIM;
	169	#endif
	170
	171	#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
	172	memctl->or7 = CFG_OR7_PRELIM;
	173	memctl->br7 = CFG_BR7_PRELIM;
	174	#endif
	175
9c4c5ae3	176	#if defined(CONFIG_CPM2)
42d1f039 WD	177	m8560_cpm_reset();
	178	#endif
	179	}
	180
d9b94f28	181
42d1f039	182	/*
d9b94f28 JL	183	* Initialize L2 as cache.
	184	*
	185	* The newer 8548, etc, parts have twice as much cache, but
	186	* use the same bit-encoding as the older 8555, etc, parts.
	187	*
	188	* FIXME: Use PVR_VER(pvr) == 1 test here instead of SVR_VER()?
42d1f039	189	*/
d9b94f28 JL	190
d9b94f28 JL	191	int cpu_init_r(void)
42d1f039 WD	192	{
42d1f039 WD	193	#if defined(CONFIG_L2_CACHE)
d9b94f28	194	volatile immap_t immap = (immap_t )CFG_IMMR;
42d1f039	195	volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
d9b94f28 JL	196	volatile uint cache_ctl;
	197	uint svr, ver;
	198
	199	svr = get_svr();
	200	ver = SVR_VER(svr);
42d1f039	201
d65cfe89	202	asm("msync;isync");
d9b94f28 JL	203	cache_ctl = l2cache->l2ctl;
	204
	205	switch (cache_ctl & 0x30000000) {
d65cfe89	206	case 0x20000000:
d9b94f28 JL	207	if (ver == SVR_8548 \|\| ver == SVR_8548_E) {
	208	printf ("L2 cache 512KB:");
	209	} else {
	210	printf ("L2 cache 256KB:");
	211	}
d65cfe89 JL	212	break;
	213	case 0x00000000:
	214	case 0x10000000:
	215	case 0x30000000:
	216	default:
d9b94f28	217	printf ("L2 cache unknown size (0x%08x)\n", cache_ctl);
d65cfe89 JL	218	return -1;
	219	}
	220
42d1f039 WD	221	asm("msync;isync");
42d1f039 WD	222	l2cache->l2ctl = 0x68000000; /* invalidate */
d9b94f28	223	cache_ctl = l2cache->l2ctl;
42d1f039	224	asm("msync;isync");
d9b94f28	225
42d1f039	226	l2cache->l2ctl = 0xa8000000; /* enable 256KB L2 cache */
d9b94f28	227	cache_ctl = l2cache->l2ctl;
42d1f039 WD	228	asm("msync;isync");
42d1f039 WD	229
d9b94f28	230	printf(" enabled\n");
42d1f039	231	#else
d9b94f28	232	printf("L2 cache: disabled\n");
42d1f039 WD	233	#endif
	234
	235	return 0;
	236	}