[people/ms/u-boot.git] / cpu / mpc85xx / mp.c

/*
 * Copyright 2008 Freescale Semiconductor.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <ioports.h>
#include <lmb.h>
#include <asm/io.h>
#include "mp.h"

DECLARE_GLOBAL_DATA_PTR;

u32 get_my_id()
{
	return mfspr(SPRN_PIR);
}

int cpu_reset(int nr)
{
	volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
	out_be32(&pic->pir, 1 << nr);
	(void)in_be32(&pic->pir);
	out_be32(&pic->pir, 0x0);

	return 0;
}

int cpu_status(int nr)
{
	u32 *table, id = get_my_id();

	if (nr == id) {
		table = (u32 *)get_spin_addr();
		printf("table base @ 0x%p\n", table);
	} else {
		table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
		printf("Running on cpu %d\n", id);
		printf("\n");
		printf("table @ 0x%p\n", table);
		printf("   addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
		printf("   pir  - 0x%08x\n", table[BOOT_ENTRY_PIR]);
		printf("   r3   - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
		printf("   r6   - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]);
	}

	return 0;
}

static u8 boot_entry_map[4] = {
	0,
	BOOT_ENTRY_PIR,
	BOOT_ENTRY_R3_LOWER,
	BOOT_ENTRY_R6_LOWER,
};

int cpu_release(int nr, int argc, char *argv[])
{
	u32 i, val, *table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
	u64 boot_addr;

	if (nr == get_my_id()) {
		printf("Invalid to release the boot core.\n\n");
		return 1;
	}

	if (argc != 4) {
		printf("Invalid number of arguments to release.\n\n");
		return 1;
	}

#ifdef CONFIG_SYS_64BIT_STRTOUL
	boot_addr = simple_strtoull(argv[0], NULL, 16);
#else
	boot_addr = simple_strtoul(argv[0], NULL, 16);
#endif

	/* handle pir, r3, r6 */
	for (i = 1; i < 4; i++) {
		if (argv[i][0] != '-') {
			u8 entry = boot_entry_map[i];
			val = simple_strtoul(argv[i], NULL, 16);
			table[entry] = val;
		}
	}

	table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);

	/* ensure all table updates complete before final address write */
	eieio();

	table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);

	return 0;
}

ulong get_spin_addr(void)
{
	extern ulong __secondary_start_page;
	extern ulong __spin_table;

	ulong addr =
		(ulong)&__spin_table - (ulong)&__secondary_start_page;
	addr += 0xfffff000;

	return addr;
}

static void pq3_mp_up(unsigned long bootpg)
{
	u32 up, cpu_up_mask, whoami;
	u32 *table = (u32 *)get_spin_addr();
	volatile u32 bpcr;
	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
	u32 devdisr;
	int timeout = 10;

	whoami = in_be32(&pic->whoami);
	out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));

	/* disable time base at the platform */
	devdisr = in_be32(&gur->devdisr);
	if (whoami)
		devdisr |= MPC85xx_DEVDISR_TB0;
	else
		devdisr |= MPC85xx_DEVDISR_TB1;
	out_be32(&gur->devdisr, devdisr);

	/* release the hounds */
	up = ((1 << CONFIG_NUM_CPUS) - 1);
	bpcr = in_be32(&ecm->eebpcr);
	bpcr |= (up << 24);
	out_be32(&ecm->eebpcr, bpcr);
	asm("sync; isync; msync");

	cpu_up_mask = 1 << whoami;
	/* wait for everyone */
	while (timeout) {
		int i;
		for (i = 0; i < CONFIG_NUM_CPUS; i++) {
			if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
				cpu_up_mask |= (1 << i);
		};

		if ((cpu_up_mask & up) == up)
			break;

		udelay(100);
		timeout--;
	}

	if (timeout == 0)
		printf("CPU up timeout. CPU up mask is %x should be %x\n",
			cpu_up_mask, up);

	/* enable time base at the platform */
	if (whoami)
		devdisr |= MPC85xx_DEVDISR_TB1;
	else
		devdisr |= MPC85xx_DEVDISR_TB0;
	out_be32(&gur->devdisr, devdisr);
	mtspr(SPRN_TBWU, 0);
	mtspr(SPRN_TBWL, 0);

	devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
	out_be32(&gur->devdisr, devdisr);
}

void cpu_mp_lmb_reserve(struct lmb *lmb)
{
	u32 bootpg;

	/* if we have 4G or more of memory, put the boot page at 4Gb-4k */
	if ((u64)gd->ram_size > 0xfffff000)
		bootpg = 0xfffff000;
	else
		bootpg = gd->ram_size - 4096;

	lmb_reserve(lmb, bootpg, 4096);
}

void setup_mp(void)
{
	extern ulong __secondary_start_page;
	ulong fixup = (ulong)&__secondary_start_page;
	u32 bootpg;

	/* if we have 4G or more of memory, put the boot page at 4Gb-4k */
	if ((u64)gd->ram_size > 0xfffff000)
		bootpg = 0xfffff000;
	else
		bootpg = gd->ram_size - 4096;

	memcpy((void *)bootpg, (void *)fixup, 4096);
	flush_cache(bootpg, 4096);

	pq3_mp_up(bootpg);
}
Commit	Line	Data
ec2b74ff KG	1	/*
	2	* Copyright 2008 Freescale Semiconductor.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24	#include <asm/processor.h>
	25	#include <ioports.h>
dd6c910a	26	#include <lmb.h>
ec2b74ff KG	27	#include <asm/io.h>
	28	#include "mp.h"
	29
	30	DECLARE_GLOBAL_DATA_PTR;
	31
ec2b74ff KG	32	u32 get_my_id()
	33	{
	34	return mfspr(SPRN_PIR);
	35	}
	36
	37	int cpu_reset(int nr)
	38	{
6d0f6bcf	39	volatile ccsr_pic_t pic = (void )(CONFIG_SYS_MPC85xx_PIC_ADDR);
ec2b74ff KG	40	out_be32(&pic->pir, 1 << nr);
	41	(void)in_be32(&pic->pir);
	42	out_be32(&pic->pir, 0x0);
	43
	44	return 0;
	45	}
	46
	47	int cpu_status(int nr)
	48	{
	49	u32 *table, id = get_my_id();
	50
	51	if (nr == id) {
	52	table = (u32 *)get_spin_addr();
348753d4	53	printf("table base @ 0x%p\n", table);
ec2b74ff KG	54	} else {
	55	table = (u32 )get_spin_addr() + nr NUM_BOOT_ENTRY;
	56	printf("Running on cpu %d\n", id);
	57	printf("\n");
348753d4	58	printf("table @ 0x%p\n", table);
79679d80	59	printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
ec2b74ff	60	printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
79679d80 KG	61	printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
79679d80 KG	62	printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]);
ec2b74ff KG	63	}
	64
	65	return 0;
	66	}
	67
79679d80 KG	68	static u8 boot_entry_map[4] = {
	69	0,
	70	BOOT_ENTRY_PIR,
	71	BOOT_ENTRY_R3_LOWER,
	72	BOOT_ENTRY_R6_LOWER,
	73	};
	74
	75	int cpu_release(int nr, int argc, char *argv[])
ec2b74ff KG	76	{
ec2b74ff KG	77	u32 i, val, table = (u32 )get_spin_addr() + nr * NUM_BOOT_ENTRY;
79679d80	78	u64 boot_addr;
ec2b74ff KG	79
	80	if (nr == get_my_id()) {
	81	printf("Invalid to release the boot core.\n\n");
	82	return 1;
	83	}
	84
79679d80	85	if (argc != 4) {
ec2b74ff KG	86	printf("Invalid number of arguments to release.\n\n");
	87	return 1;
	88	}
	89
6d0f6bcf	90	#ifdef CONFIG_SYS_64BIT_STRTOUL
79679d80 KG	91	boot_addr = simple_strtoull(argv[0], NULL, 16);
	92	#else
	93	boot_addr = simple_strtoul(argv[0], NULL, 16);
	94	#endif
	95
	96	/* handle pir, r3, r6 */
	97	for (i = 1; i < 4; i++) {
ec2b74ff	98	if (argv[i][0] != '-') {
79679d80	99	u8 entry = boot_entry_map[i];
ec2b74ff	100	val = simple_strtoul(argv[i], NULL, 16);
79679d80	101	table[entry] = val;
ec2b74ff KG	102	}
	103	}
	104
79679d80	105	table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
cf6cc014 KG	106
	107	/* ensure all table updates complete before final address write */
	108	eieio();
	109
79679d80	110	table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
ec2b74ff KG	111
	112	return 0;
	113	}
	114
	115	ulong get_spin_addr(void)
	116	{
	117	extern ulong __secondary_start_page;
	118	extern ulong __spin_table;
	119
	120	ulong addr =
	121	(ulong)&__spin_table - (ulong)&__secondary_start_page;
	122	addr += 0xfffff000;
	123
	124	return addr;
	125	}
	126
	127	static void pq3_mp_up(unsigned long bootpg)
	128	{
	129	u32 up, cpu_up_mask, whoami;
	130	u32 table = (u32 )get_spin_addr();
	131	volatile u32 bpcr;
6d0f6bcf JCPV	132	volatile ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
	133	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	134	volatile ccsr_pic_t pic = (void )(CONFIG_SYS_MPC85xx_PIC_ADDR);
ec2b74ff KG	135	u32 devdisr;
	136	int timeout = 10;
	137
	138	whoami = in_be32(&pic->whoami);
	139	out_be32(&ecm->bptr, 0x80000000 \| (bootpg >> 12));
	140
	141	/* disable time base at the platform */
	142	devdisr = in_be32(&gur->devdisr);
	143	if (whoami)
	144	devdisr \|= MPC85xx_DEVDISR_TB0;
	145	else
	146	devdisr \|= MPC85xx_DEVDISR_TB1;
	147	out_be32(&gur->devdisr, devdisr);
	148
	149	/* release the hounds */
902ca092	150	up = ((1 << CONFIG_NUM_CPUS) - 1);
ec2b74ff KG	151	bpcr = in_be32(&ecm->eebpcr);
	152	bpcr \|= (up << 24);
	153	out_be32(&ecm->eebpcr, bpcr);
	154	asm("sync; isync; msync");
	155
	156	cpu_up_mask = 1 << whoami;
	157	/* wait for everyone */
	158	while (timeout) {
	159	int i;
902ca092	160	for (i = 0; i < CONFIG_NUM_CPUS; i++) {
97b3ecb5	161	if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
ec2b74ff KG	162	cpu_up_mask \|= (1 << i);
	163	};
	164
	165	if ((cpu_up_mask & up) == up)
	166	break;
	167
	168	udelay(100);
	169	timeout--;
	170	}
	171
97b3ecb5 KG	172	if (timeout == 0)
	173	printf("CPU up timeout. CPU up mask is %x should be %x\n",
	174	cpu_up_mask, up);
	175
ec2b74ff KG	176	/* enable time base at the platform */
	177	if (whoami)
	178	devdisr \|= MPC85xx_DEVDISR_TB1;
	179	else
	180	devdisr \|= MPC85xx_DEVDISR_TB0;
	181	out_be32(&gur->devdisr, devdisr);
	182	mtspr(SPRN_TBWU, 0);
	183	mtspr(SPRN_TBWL, 0);
	184
	185	devdisr &= ~(MPC85xx_DEVDISR_TB0 \| MPC85xx_DEVDISR_TB1);
	186	out_be32(&gur->devdisr, devdisr);
	187	}
	188
dd6c910a KG	189	void cpu_mp_lmb_reserve(struct lmb *lmb)
	190	{
	191	u32 bootpg;
	192
	193	/* if we have 4G or more of memory, put the boot page at 4Gb-4k */
	194	if ((u64)gd->ram_size > 0xfffff000)
	195	bootpg = 0xfffff000;
	196	else
	197	bootpg = gd->ram_size - 4096;
	198
	199	lmb_reserve(lmb, bootpg, 4096);
	200	}
	201
ec2b74ff KG	202	void setup_mp(void)
	203	{
	204	extern ulong __secondary_start_page;
	205	ulong fixup = (ulong)&__secondary_start_page;
	206	u32 bootpg;
	207
	208	/* if we have 4G or more of memory, put the boot page at 4Gb-4k */
	209	if ((u64)gd->ram_size > 0xfffff000)
	210	bootpg = 0xfffff000;
	211	else
	212	bootpg = gd->ram_size - 4096;
	213
	214	memcpy((void )bootpg, (void )fixup, 4096);
	215	flush_cache(bootpg, 4096);
	216
	217	pq3_mp_up(bootpg);
	218	}