[people/ms/u-boot.git] / cpu / mpc85xx / pci.c

/*
 * Copyright 2004 Freescale Semiconductor.
 * Copyright (C) 2003 Motorola Inc.
 * Xianghua Xiao (x.xiao@motorola.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * PCI Configuration space access support for MPC85xx PCI Bridge
 */
#include <common.h>
#include <asm/cpm_85xx.h>
#include <pci.h>


#if defined(CONFIG_PCI)

void
pci_mpc85xx_init(struct pci_controller *hose)
{
	volatile immap_t    *immap = (immap_t *)CFG_CCSRBAR;
	volatile ccsr_pcix_t *pcix = &immap->im_pcix;

	u16 reg16;

	hose->first_busno = 0;
	hose->last_busno = 0xff;

	pci_set_region(hose->regions + 0,
		       CFG_PCI1_MEM_BASE,
		       CFG_PCI1_MEM_PHYS,
		       CFG_PCI1_MEM_SIZE,
		       PCI_REGION_MEM);

	pci_set_region(hose->regions + 1,
		       CFG_PCI1_IO_BASE,
		       CFG_PCI1_IO_PHYS,
		       CFG_PCI1_IO_SIZE,
		       PCI_REGION_IO);

	hose->region_count = 2;

	pci_setup_indirect(hose,
			   (CFG_IMMR+0x8000),
			   (CFG_IMMR+0x8004));

	pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);

	/*
	 * Clear non-reserved bits in status register.
	 */
	pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
	pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);

	pcix->potar1   = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
	pcix->potear1  = 0x00000000;
	pcix->powbar1  = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
	pcix->powbear1 = 0x00000000;
	pcix->powar1   = 0x8004401c;	/* 512M MEM space */

	pcix->potar2   = 0x00000000;
	pcix->potear2  = 0x00000000;
	pcix->powbar2  = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
	pcix->powbear2 = 0x00000000;
	pcix->powar2   = 0x80088017;	/* 16M IO space */

	pcix->pitar1 = 0x00000000;
	pcix->piwbar1 = 0x00000000;
	pcix->piwar1 = 0xa0f5501e;	/* Enable, Prefetch, Local Mem,
					 * Snoop R/W, 2G */

	/*
	 * Hose scan.
	 */
	pci_register_hose(hose);

#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
	/*
	 * This is a SW workaround for an apparent HW problem
	 * in the PCI controller on the MPC85555/41 CDS boards.
	 * The first config cycle must be to a valid, known
	 * device on the PCI bus in order to trick the PCI
	 * controller state machine into a known valid state.
	 * Without this, the first config cycle has the chance
	 * of hanging the controller permanently, just leaving
	 * it in a semi-working state, or leaving it working.
	 *
	 * Pick on the Tundra, Device 17, to get it right.
	 */
	{
		u8 header_type;

		pci_hose_read_config_byte(hose,
					  PCI_BDF(0,17,0),
					  PCI_HEADER_TYPE,
					  &header_type);
	}
#endif

	hose->last_busno = pci_hose_scan(hose);
}

#endif /* CONFIG_PCI */
Commit	Line	Data
42d1f039	1	/*
0ac6f8b7	2	* Copyright 2004 Freescale Semiconductor.
42d1f039 WD	3	* Copyright (C) 2003 Motorola Inc.
	4	* Xianghua Xiao (x.xiao@motorola.com)
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	/*
	26	* PCI Configuration space access support for MPC85xx PCI Bridge
	27	*/
	28	#include <common.h>
	29	#include <asm/cpm_85xx.h>
	30	#include <pci.h>
	31
0ac6f8b7	32
42d1f039	33	#if defined(CONFIG_PCI)
0ac6f8b7	34
9aea9530 WD	35	void
9aea9530 WD	36	pci_mpc85xx_init(struct pci_controller *hose)
0ac6f8b7	37	{
9aea9530	38	volatile immap_t immap = (immap_t )CFG_CCSRBAR;
0ac6f8b7 WD	39	volatile ccsr_pcix_t *pcix = &immap->im_pcix;
	40
	41	u16 reg16;
	42
	43	hose->first_busno = 0;
	44	hose->last_busno = 0xff;
	45
9aea9530 WD	46	pci_set_region(hose->regions + 0,
	47	CFG_PCI1_MEM_BASE,
	48	CFG_PCI1_MEM_PHYS,
	49	CFG_PCI1_MEM_SIZE,
	50	PCI_REGION_MEM);
0ac6f8b7	51
9aea9530 WD	52	pci_set_region(hose->regions + 1,
	53	CFG_PCI1_IO_BASE,
	54	CFG_PCI1_IO_PHYS,
	55	CFG_PCI1_IO_SIZE,
	56	PCI_REGION_IO);
0ac6f8b7 WD	57
	58	hose->region_count = 2;
	59
9aea9530 WD	60	pci_setup_indirect(hose,
	61	(CFG_IMMR+0x8000),
	62	(CFG_IMMR+0x8004));
0ac6f8b7	63
9aea9530	64	pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
0ac6f8b7	65	reg16 \|= PCI_COMMAND_SERR \| PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY;
9aea9530	66	pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
0ac6f8b7 WD	67
	68	/*
	69	* Clear non-reserved bits in status register.
	70	*/
9aea9530 WD	71	pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
9aea9530 WD	72	pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
0ac6f8b7	73
9aea9530 WD	74	pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
	75	pcix->potear1 = 0x00000000;
	76	pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
0ac6f8b7	77	pcix->powbear1 = 0x00000000;
9aea9530	78	pcix->powar1 = 0x8004401c; /* 512M MEM space */
0ac6f8b7	79
cf33678e	80	pcix->potar2 = 0x00000000;
9aea9530 WD	81	pcix->potear2 = 0x00000000;
9aea9530 WD	82	pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
0ac6f8b7	83	pcix->powbear2 = 0x00000000;
9aea9530	84	pcix->powar2 = 0x80088017; /* 16M IO space */
0ac6f8b7 WD	85
	86	pcix->pitar1 = 0x00000000;
	87	pcix->piwbar1 = 0x00000000;
cf33678e WD	88	pcix->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local Mem,
cf33678e WD	89	* Snoop R/W, 2G */
0ac6f8b7 WD	90
	91	/*
	92	* Hose scan.
	93	*/
9aea9530	94	pci_register_hose(hose);
cf33678e WD	95
	96	#if defined(CONFIG_MPC8555CDS) \|\| defined(CONFIG_MPC8541CDS)
	97	/*
	98	* This is a SW workaround for an apparent HW problem
	99	* in the PCI controller on the MPC85555/41 CDS boards.
	100	* The first config cycle must be to a valid, known
	101	* device on the PCI bus in order to trick the PCI
	102	* controller state machine into a known valid state.
	103	* Without this, the first config cycle has the chance
	104	* of hanging the controller permanently, just leaving
	105	* it in a semi-working state, or leaving it working.
	106	*
	107	* Pick on the Tundra, Device 17, to get it right.
	108	*/
	109	{
	110	u8 header_type;
	111
	112	pci_hose_read_config_byte(hose,
	113	PCI_BDF(0,17,0),
	114	PCI_HEADER_TYPE,
	115	&header_type);
	116	}
cf33678e WD	117	#endif
cf33678e WD	118
9aea9530	119	hose->last_busno = pci_hose_scan(hose);
42d1f039	120	}
0ac6f8b7	121
42d1f039	122	#endif /* CONFIG_PCI */