[people/ms/u-boot.git] / cpu / mpc85xx / pci.c

/*
 * Copyright 2004 Freescale Semiconductor.
 * Copyright (C) 2003 Motorola Inc.
 * Xianghua Xiao (x.xiao@motorola.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * PCI Configuration space access support for MPC85xx PCI Bridge
 */
#include <common.h>
#include <asm/cpm_85xx.h>
#include <pci.h>


#if defined(CONFIG_PCI)


/*
 * Initialize PCI Devices, report devices found.
 */

#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxads_config_table[] = {
	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
				     PCI_ENET0_MEMADDR,
				     PCI_COMMAND_MEMORY |
				     PCI_COMMAND_MASTER}},
	{}
};
#endif

struct pci_controller local_hose = {
#ifndef CONFIG_PCI_PNP
	config_table: pci_mpc85xxads_config_table,
#endif
};


void pci_init_board (void)
{
	struct pci_controller *hose = (struct pci_controller *) &local_hose;
	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
	volatile ccsr_pcix_t *pcix = &immap->im_pcix;

	u16 reg16;

	hose->first_busno = 0;
	hose->last_busno = 0xff;

	pci_set_region (hose->regions + 0,
			CFG_PCI1_MEM_BASE,
			CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);

	pci_set_region (hose->regions + 1,
			CFG_PCI1_IO_BASE,
			CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO);

	hose->region_count = 2;

	pci_setup_indirect (hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004));

	pci_read_config_word (PCI_BDF (0, 0, 0), PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	pci_write_config_word (PCI_BDF (0, 0, 0), PCI_COMMAND, reg16);

	/*
	 * Clear non-reserved bits in status register.
	 */
	pci_write_config_word (PCI_BDF (0, 0, 0), PCI_STATUS, 0xffff);
	pci_write_config_byte (PCI_BDF (0, 0, 0), PCI_LATENCY_TIMER, 0x80);

	pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
	pcix->potear1 = 0x00000000;
	pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
	pcix->powbear1 = 0x00000000;
	pcix->powar1 = 0x8004401c;	/* 512M MEM space */

	pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
	pcix->potear2 = 0x00000000;
	pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
	pcix->powbear2 = 0x00000000;
	pcix->powar2 = 0x80088017;	/* 16M IO space */

	pcix->pitar1 = 0x00000000;
	pcix->piwbar1 = 0x00000000;
	pcix->piwar1 = 0xa0F5501f;

	/*
	 * Hose scan.
	 */
	pci_register_hose (hose);
	hose->last_busno = pci_hose_scan (hose);
}

#endif /* CONFIG_PCI */
Commit	Line	Data
42d1f039	1	/*
0ac6f8b7	2	* Copyright 2004 Freescale Semiconductor.
42d1f039 WD	3	* Copyright (C) 2003 Motorola Inc.
	4	* Xianghua Xiao (x.xiao@motorola.com)
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	/*
	26	* PCI Configuration space access support for MPC85xx PCI Bridge
	27	*/
	28	#include <common.h>
	29	#include <asm/cpm_85xx.h>
	30	#include <pci.h>
	31
0ac6f8b7	32
42d1f039	33	#if defined(CONFIG_PCI)
0ac6f8b7 WD	34
0ac6f8b7 WD	35
42d1f039 WD	36	/*
	37	* Initialize PCI Devices, report devices found.
	38	*/
0ac6f8b7	39
42d1f039 WD	40	#ifndef CONFIG_PCI_PNP
42d1f039 WD	41	static struct pci_config_table pci_mpc85xxads_config_table[] = {
0ac6f8b7 WD	42	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	43	PCI_IDSEL_NUMBER, PCI_ANY_ID,
	44	pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
	45	PCI_ENET0_MEMADDR,
	46	PCI_COMMAND_MEMORY \|
	47	PCI_COMMAND_MASTER}},
	48	{}
42d1f039 WD	49	};
	50	#endif
	51
	52	struct pci_controller local_hose = {
	53	#ifndef CONFIG_PCI_PNP
	54	config_table: pci_mpc85xxads_config_table,
	55	#endif
	56	};
	57
42d1f039	58
0ac6f8b7 WD	59	void pci_init_board (void)
	60	{
	61	struct pci_controller hose = (struct pci_controller ) &local_hose;
	62	volatile immap_t immap = (immap_t ) CFG_CCSRBAR;
	63	volatile ccsr_pcix_t *pcix = &immap->im_pcix;
	64
	65	u16 reg16;
	66
	67	hose->first_busno = 0;
	68	hose->last_busno = 0xff;
	69
	70	pci_set_region (hose->regions + 0,
	71	CFG_PCI1_MEM_BASE,
	72	CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
	73
	74	pci_set_region (hose->regions + 1,
	75	CFG_PCI1_IO_BASE,
	76	CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
	77
	78	hose->region_count = 2;
	79
	80	pci_setup_indirect (hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004));
	81
	82	pci_read_config_word (PCI_BDF (0, 0, 0), PCI_COMMAND, &reg16);
	83	reg16 \|= PCI_COMMAND_SERR \| PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY;
	84	pci_write_config_word (PCI_BDF (0, 0, 0), PCI_COMMAND, reg16);
	85
	86	/*
	87	* Clear non-reserved bits in status register.
	88	*/
	89	pci_write_config_word (PCI_BDF (0, 0, 0), PCI_STATUS, 0xffff);
	90	pci_write_config_byte (PCI_BDF (0, 0, 0), PCI_LATENCY_TIMER, 0x80);
	91
	92	pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
	93	pcix->potear1 = 0x00000000;
	94	pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
	95	pcix->powbear1 = 0x00000000;
	96	pcix->powar1 = 0x8004401c; /* 512M MEM space */
	97
	98	pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
	99	pcix->potear2 = 0x00000000;
	100	pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
	101	pcix->powbear2 = 0x00000000;
	102	pcix->powar2 = 0x80088017; /* 16M IO space */
	103
	104	pcix->pitar1 = 0x00000000;
	105	pcix->piwbar1 = 0x00000000;
	106	pcix->piwar1 = 0xa0F5501f;
	107
	108	/*
	109	* Hose scan.
	110	*/
	111	pci_register_hose (hose);
	112	hose->last_busno = pci_hose_scan (hose);
42d1f039	113	}
0ac6f8b7	114
42d1f039	115	#endif /* CONFIG_PCI */