[people/ms/u-boot.git] / cpu / mpc86xx / cache.S

#include <config.h>
#include <mpc86xx.h>
#include <version.h>

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <asm/cache.h>
#include <asm/mmu.h>

#ifndef CACHE_LINE_SIZE
# define CACHE_LINE_SIZE L1_CACHE_BYTES
#endif

#if CACHE_LINE_SIZE == 128
#define LG_CACHE_LINE_SIZE 7
#elif CACHE_LINE_SIZE == 32
#define LG_CACHE_LINE_SIZE 5
#elif CACHE_LINE_SIZE == 16
#define LG_CACHE_LINE_SIZE 4
#elif CACHE_LINE_SIZE == 8
#define LG_CACHE_LINE_SIZE 3
#else
# error "Invalid cache line size!"
#endif

/*
 * Most of this code is taken from 74xx_7xx/cache.S
 * and then cleaned up a bit
 */

/*
 * Invalidate L1 instruction cache.
 */
_GLOBAL(invalidate_l1_instruction_cache)
	/* use invalidate-all bit in HID0 */
	mfspr	r3,HID0
	ori	r3,r3,HID0_ICFI
	mtspr	HID0,r3
	isync
	blr

/*
 * Invalidate L1 data cache.
 */
_GLOBAL(invalidate_l1_data_cache)
	mfspr	r3,HID0
	ori	r3,r3,HID0_DCFI
	mtspr	HID0,r3
	isync
	blr

/*
 * Flush data cache.
 */
_GLOBAL(flush_dcache)
	lis	r3,0
	lis	r5,CACHE_LINE_SIZE
flush:
	cmp	0,1,r3,r5
	bge	done
	lwz	r5,0(r3)
	lis	r5,CACHE_LINE_SIZE
	addi	r3,r3,0x4
	b	flush
done:
	blr
/*
 * Write any modified data cache blocks out to memory
 * and invalidate the corresponding instruction cache blocks.
 * This is a no-op on the 601.
 *
 * flush_icache_range(unsigned long start, unsigned long stop)
 */
_GLOBAL(flush_icache_range)
	li	r5,CACHE_LINE_SIZE-1
	andc	r3,r3,r5
	subf	r4,r3,r4
	add	r4,r4,r5
	srwi.	r4,r4,LG_CACHE_LINE_SIZE
	beqlr
	mtctr	r4
	mr	r6,r3
1:	dcbst	0,r3
	addi	r3,r3,CACHE_LINE_SIZE
	bdnz	1b
	sync				/* wait for dcbst's to get to ram */
	mtctr	r4
2:	icbi	0,r6
	addi	r6,r6,CACHE_LINE_SIZE
	bdnz	2b
	sync				/* additional sync needed on g4 */
	isync
	blr
/*
 * Write any modified data cache blocks out to memory.
 * Does not invalidate the corresponding cache lines (especially for
 * any corresponding instruction cache).
 *
 * clean_dcache_range(unsigned long start, unsigned long stop)
 */
_GLOBAL(clean_dcache_range)
	li	r5,CACHE_LINE_SIZE-1
	andc	r3,r3,r5	/* align r3 down to cache line */
	subf	r4,r3,r4	/* r4 = offset of stop from start of cache line */
	add	r4,r4,r5	/* r4 += cache_line_size-1 */
	srwi.	r4,r4,LG_CACHE_LINE_SIZE  /* r4 = number of cache lines to flush */
	beqlr				  /* if r4 == 0 return */
	mtctr	r4			  /* ctr = r4 */

	sync
1:	dcbst	0,r3
	addi	r3,r3,CACHE_LINE_SIZE
	bdnz	1b
	sync				/* wait for dcbst's to get to ram */
	blr

/*
 * Write any modified data cache blocks out to memory
 * and invalidate the corresponding instruction cache blocks.
 *
 * flush_dcache_range(unsigned long start, unsigned long stop)
 */
_GLOBAL(flush_dcache_range)
	li	r5,CACHE_LINE_SIZE-1
	andc	r3,r3,r5
	subf	r4,r3,r4
	add	r4,r4,r5
	srwi.	r4,r4,LG_CACHE_LINE_SIZE
	beqlr
	mtctr	r4

	sync
1:	dcbf	0,r3
	addi	r3,r3,CACHE_LINE_SIZE
	bdnz	1b
	sync				/* wait for dcbf's to get to ram */
	blr

/*
 * Like above, but invalidate the D-cache.  This is used by the 8xx
 * to invalidate the cache so the PPC core doesn't get stale data
 * from the CPM (no cache snooping here :-).
 *
 * invalidate_dcache_range(unsigned long start, unsigned long stop)
 */
_GLOBAL(invalidate_dcache_range)
	li	r5,CACHE_LINE_SIZE-1
	andc	r3,r3,r5
	subf	r4,r3,r4
	add	r4,r4,r5
	srwi.	r4,r4,LG_CACHE_LINE_SIZE
	beqlr
	mtctr	r4

	sync
1:	dcbi	0,r3
	addi	r3,r3,CACHE_LINE_SIZE
	bdnz	1b
	sync				/* wait for dcbi's to get to ram */
	blr

/*
 * Flush a particular page from the data cache to RAM.
 * Note: this is necessary because the instruction cache does *not*
 * snoop from the data cache.
 *
 *	void __flush_page_to_ram(void *page)
 */
_GLOBAL(__flush_page_to_ram)
	rlwinm	r3,r3,0,0,19		/* Get page base address */
	li	r4,4096/CACHE_LINE_SIZE	/* Number of lines in a page */
	mtctr	r4
	mr	r6,r3
0:	dcbst	0,r3			/* Write line to ram */
	addi	r3,r3,CACHE_LINE_SIZE
	bdnz	0b
	sync
	mtctr	r4
1:	icbi	0,r6
	addi	r6,r6,CACHE_LINE_SIZE
	bdnz	1b
	sync
	isync
	blr

/*
 * Flush a particular page from the instruction cache.
 * Note: this is necessary because the instruction cache does *not*
 * snoop from the data cache.
 *
 *	void __flush_icache_page(void *page)
 */
_GLOBAL(__flush_icache_page)
	li	r4,4096/CACHE_LINE_SIZE	/* Number of lines in a page */
	mtctr	r4
1:	icbi	0,r3
	addi	r3,r3,CACHE_LINE_SIZE
	bdnz	1b
	sync
	isync
	blr

/*
 * Clear a page using the dcbz instruction, which doesn't cause any
 * memory traffic (except to write out any cache lines which get
 * displaced).  This only works on cacheable memory.
 */
_GLOBAL(clear_page)
	li	r0,4096/CACHE_LINE_SIZE
	mtctr	r0
1:	dcbz	0,r3
	addi	r3,r3,CACHE_LINE_SIZE
	bdnz	1b
	blr

/*
 * Enable L1 Instruction cache
 */
_GLOBAL(icache_enable)
	mfspr	r3, HID0
	li	r5, HID0_ICFI|HID0_ILOCK
	andc	r3, r3, r5
	ori	r3, r3, HID0_ICE
	ori	r5, r3, HID0_ICFI
	mtspr	HID0, r5
	mtspr	HID0, r3
	isync
	blr

/*
 * Disable L1 Instruction cache
 */
_GLOBAL(icache_disable)
	mflr	r4
	bl	invalidate_l1_instruction_cache		/* uses r3 */
	sync
	mtlr	r4
	mfspr	r3, HID0
	li	r5, 0
	ori	r5, r5, HID0_ICE
	andc	r3, r3, r5
	mtspr	HID0, r3
	isync
	blr

/*
 * Is instruction cache enabled?
 */
_GLOBAL(icache_status)
	mfspr	r3, HID0
	andi.	r3, r3, HID0_ICE
	blr


_GLOBAL(l1dcache_enable)
	mfspr	r3, HID0
	li	r5, HID0_DCFI|HID0_DLOCK
	andc	r3, r3, r5
	mtspr	HID0, r3		/* no invalidate, unlock */
	ori	r3, r3, HID0_DCE
	ori	r5, r3, HID0_DCFI
	mtspr	HID0, r5		/* enable + invalidate */
	mtspr	HID0, r3		/* enable */
	sync
	blr

/*
 * Enable data cache(s) - L1 and optionally L2
 * Calls l2cache_enable. LR saved in r5
 */
_GLOBAL(dcache_enable)
	mfspr	r3, HID0
	li	r5, HID0_DCFI|HID0_DLOCK
	andc	r3, r3, r5
	mtspr	HID0, r3		/* no invalidate, unlock */
	ori	r3, r3, HID0_DCE
	ori	r5, r3, HID0_DCFI
	mtspr	HID0, r5		/* enable + invalidate */
	mtspr	HID0, r3		/* enable */
	sync
#ifdef CONFIG_SYS_L2
	mflr	r5
	bl	l2cache_enable		/* uses r3 and r4 */
	sync
	mtlr	r5
#endif
	blr


/*
 * Disable data cache(s) - L1 and optionally L2
 * Calls flush_dcache and l2cache_disable_no_flush.
 * LR saved in r4
 */
_GLOBAL(dcache_disable)
	mflr	r4			/* save link register */
	bl	flush_dcache	/* uses r3 and r5 */
	sync
	mfspr	r3, HID0
	li	r5, HID0_DCFI|HID0_DLOCK
	andc	r3, r3, r5
	mtspr	HID0, r3		/* no invalidate, unlock */
	li	r5, HID0_DCE|HID0_DCFI
	andc	r3, r3, r5		/* no enable, no invalidate */
	mtspr	HID0, r3
	sync
#ifdef CONFIG_SYS_L2
	bl	l2cache_disable_no_flush /* uses r3 */
#endif
	mtlr	r4			/* restore link register */
	blr

/*
 * Is data cache enabled?
 */
_GLOBAL(dcache_status)
	mfspr	r3, HID0
	andi.	r3, r3, HID0_DCE
	blr

/*
 * Invalidate L2 cache using L2I, assume L2 is enabled
 */
_GLOBAL(l2cache_invalidate)
	mfspr	r3, l2cr
	rlwinm.	r3, r3, 0, 0, 0
	beq	1f

	mfspr	r3, l2cr
	rlwinm	r3, r3, 0, 1, 31

#ifdef	CONFIG_ALTIVEC
	dssall
#endif
	sync
	mtspr	l2cr, r3
	sync
1:	mfspr	r3, l2cr
	oris	r3, r3, L2CR_L2I@h
	mtspr	l2cr, r3

invl2:
	mfspr	r3, l2cr
	andis.	r3, r3, L2CR_L2I@h
	bne	invl2
	blr

/*
 * Enable L2 cache
 * Calls l2cache_invalidate. LR is saved in r4
 */
_GLOBAL(l2cache_enable)
	mflr	r4			/* save link register */
	bl	l2cache_invalidate	/* uses r3 */
	sync
	lis	r3, L2_ENABLE@h
	ori	r3, r3, L2_ENABLE@l
	mtspr	l2cr, r3
	isync
	mtlr	r4			/* restore link register */
	blr

/*
 * Disable L2 cache
 * Calls flush_dcache. LR is saved in r4
 */
_GLOBAL(l2cache_disable)
	mflr	r4			/* save link register */
	bl	flush_dcache		/* uses r3 and r5 */
	sync
	mtlr	r4			/* restore link register */
l2cache_disable_no_flush:		/* provide way to disable L2 w/o flushing */
	lis	r3, L2_INIT@h
	ori	r3, r3, L2_INIT@l
	mtspr	l2cr, r3
	isync
	blr
Commit	Line	Data
debb7354 JL	1	#include <config.h>
	2	#include <mpc86xx.h>
	3	#include <version.h>
	4
	5	#include <ppc_asm.tmpl>
	6	#include <ppc_defs.h>
	7
	8	#include <asm/cache.h>
	9	#include <asm/mmu.h>
	10
	11	#ifndef CACHE_LINE_SIZE
	12	# define CACHE_LINE_SIZE L1_CACHE_BYTES
	13	#endif
	14
	15	#if CACHE_LINE_SIZE == 128
	16	#define LG_CACHE_LINE_SIZE 7
	17	#elif CACHE_LINE_SIZE == 32
	18	#define LG_CACHE_LINE_SIZE 5
	19	#elif CACHE_LINE_SIZE == 16
	20	#define LG_CACHE_LINE_SIZE 4
	21	#elif CACHE_LINE_SIZE == 8
	22	#define LG_CACHE_LINE_SIZE 3
	23	#else
	24	# error "Invalid cache line size!"
	25	#endif
	26
	27	/*
	28	* Most of this code is taken from 74xx_7xx/cache.S
	29	* and then cleaned up a bit
	30	*/
cccce5d0	31
debb7354 JL	32	/*
	33	* Invalidate L1 instruction cache.
	34	*/
	35	_GLOBAL(invalidate_l1_instruction_cache)
	36	/* use invalidate-all bit in HID0 */
	37	mfspr r3,HID0
	38	ori r3,r3,HID0_ICFI
	39	mtspr HID0,r3
	40	isync
	41	blr
	42
	43	/*
	44	* Invalidate L1 data cache.
	45	*/
	46	_GLOBAL(invalidate_l1_data_cache)
	47	mfspr r3,HID0
	48	ori r3,r3,HID0_DCFI
	49	mtspr HID0,r3
	50	isync
	51	blr
	52
	53	/*
	54	* Flush data cache.
	55	*/
71edc271	56	_GLOBAL(flush_dcache)
debb7354 JL	57	lis r3,0
	58	lis r5,CACHE_LINE_SIZE
	59	flush:
	60	cmp 0,1,r3,r5
	61	bge done
	62	lwz r5,0(r3)
	63	lis r5,CACHE_LINE_SIZE
	64	addi r3,r3,0x4
	65	b flush
	66	done:
	67	blr
	68	/*
	69	* Write any modified data cache blocks out to memory
	70	* and invalidate the corresponding instruction cache blocks.
	71	* This is a no-op on the 601.
	72	*
	73	* flush_icache_range(unsigned long start, unsigned long stop)
	74	*/
	75	_GLOBAL(flush_icache_range)
	76	li r5,CACHE_LINE_SIZE-1
	77	andc r3,r3,r5
	78	subf r4,r3,r4
	79	add r4,r4,r5
	80	srwi. r4,r4,LG_CACHE_LINE_SIZE
	81	beqlr
	82	mtctr r4
	83	mr r6,r3
	84	1: dcbst 0,r3
	85	addi r3,r3,CACHE_LINE_SIZE
	86	bdnz 1b
	87	sync /* wait for dcbst's to get to ram */
	88	mtctr r4
	89	2: icbi 0,r6
	90	addi r6,r6,CACHE_LINE_SIZE
	91	bdnz 2b
	92	sync /* additional sync needed on g4 */
	93	isync
	94	blr
	95	/*
	96	* Write any modified data cache blocks out to memory.
	97	* Does not invalidate the corresponding cache lines (especially for
	98	* any corresponding instruction cache).
	99	*
	100	* clean_dcache_range(unsigned long start, unsigned long stop)
	101	*/
	102	_GLOBAL(clean_dcache_range)
	103	li r5,CACHE_LINE_SIZE-1
	104	andc r3,r3,r5 /* align r3 down to cache line */
	105	subf r4,r3,r4 /* r4 = offset of stop from start of cache line */
	106	add r4,r4,r5 /* r4 += cache_line_size-1 */
	107	srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */
	108	beqlr /* if r4 == 0 return */
	109	mtctr r4 /* ctr = r4 */
	110
	111	sync
	112	1: dcbst 0,r3
	113	addi r3,r3,CACHE_LINE_SIZE
	114	bdnz 1b
	115	sync /* wait for dcbst's to get to ram */
	116	blr
	117
	118	/*
	119	* Write any modified data cache blocks out to memory
	120	* and invalidate the corresponding instruction cache blocks.
121	*
122	* flush_dcache_range(unsigned long start, unsigned long stop)
123	*/
124	_GLOBAL(flush_dcache_range)
125	li r5,CACHE_LINE_SIZE-1
126	andc r3,r3,r5
127	subf r4,r3,r4
128	add r4,r4,r5
129	srwi. r4,r4,LG_CACHE_LINE_SIZE
130	beqlr
131	mtctr r4
132
133	sync
134	1: dcbf 0,r3
135	addi r3,r3,CACHE_LINE_SIZE
136	bdnz 1b
137	sync /* wait for dcbf's to get to ram */
138	blr
139
140	/*
141	* Like above, but invalidate the D-cache. This is used by the 8xx
142	* to invalidate the cache so the PPC core doesn't get stale data
143	* from the CPM (no cache snooping here :-).
144	*
145	* invalidate_dcache_range(unsigned long start, unsigned long stop)
146	*/
147	_GLOBAL(invalidate_dcache_range)
148	li r5,CACHE_LINE_SIZE-1
149	andc r3,r3,r5
150	subf r4,r3,r4
151	add r4,r4,r5
152	srwi. r4,r4,LG_CACHE_LINE_SIZE
153	beqlr
154	mtctr r4
155
156	sync
157	1: dcbi 0,r3
158	addi r3,r3,CACHE_LINE_SIZE
159	bdnz 1b
160	sync /* wait for dcbi's to get to ram */
161	blr
162
163	/*
164	* Flush a particular page from the data cache to RAM.
165	* Note: this is necessary because the instruction cache does not
166	* snoop from the data cache.
167	*
168	* void __flush_page_to_ram(void *page)
169	*/
170	_GLOBAL(__flush_page_to_ram)
171	rlwinm r3,r3,0,0,19 /* Get page base address */
172	li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
173	mtctr r4
174	mr r6,r3
175	0: dcbst 0,r3 /* Write line to ram */
176	addi r3,r3,CACHE_LINE_SIZE
177	bdnz 0b
178	sync
179	mtctr r4
180	1: icbi 0,r6
181	addi r6,r6,CACHE_LINE_SIZE
182	bdnz 1b
183	sync
184	isync
185	blr
186
187	/*
188	* Flush a particular page from the instruction cache.
189	* Note: this is necessary because the instruction cache does not
190	* snoop from the data cache.
191	*
192	* void __flush_icache_page(void *page)
193	*/
194	_GLOBAL(__flush_icache_page)
195	li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
196	mtctr r4
197	1: icbi 0,r3
198	addi r3,r3,CACHE_LINE_SIZE
199	bdnz 1b
200	sync
201	isync
202	blr
203
204	/*
205	* Clear a page using the dcbz instruction, which doesn't cause any
206	* memory traffic (except to write out any cache lines which get
207	* displaced). This only works on cacheable memory.
208	*/
209	_GLOBAL(clear_page)
210	li r0,4096/CACHE_LINE_SIZE
211	mtctr r0
212	1: dcbz 0,r3
213	addi r3,r3,CACHE_LINE_SIZE
214	bdnz 1b
215	blr
216
217	/*
218	* Enable L1 Instruction cache
219	*/
220	_GLOBAL(icache_enable)
221	mfspr r3, HID0
222	li r5, HID0_ICFI\|HID0_ILOCK
223	andc r3, r3, r5
224	ori r3, r3, HID0_ICE
225	ori r5, r3, HID0_ICFI
226	mtspr HID0, r5
227	mtspr HID0, r3
228	isync
229	blr
230
231	/*
232	* Disable L1 Instruction cache
233	*/
234	_GLOBAL(icache_disable)
fcd69a1a KG	235	mflr r4
	236	bl invalidate_l1_instruction_cache /* uses r3 */
	237	sync
	238	mtlr r4
debb7354 JL	239	mfspr r3, HID0
	240	li r5, 0
	241	ori r5, r5, HID0_ICE
	242	andc r3, r3, r5
	243	mtspr HID0, r3
	244	isync
	245	blr
	246
	247	/*
	248	* Is instruction cache enabled?
	249	*/
	250	_GLOBAL(icache_status)
	251	mfspr r3, HID0
	252	andi. r3, r3, HID0_ICE
	253	blr
	254
	255
	256	_GLOBAL(l1dcache_enable)
	257	mfspr r3, HID0
	258	li r5, HID0_DCFI\|HID0_DLOCK
	259	andc r3, r3, r5
	260	mtspr HID0, r3 /* no invalidate, unlock */
	261	ori r3, r3, HID0_DCE
	262	ori r5, r3, HID0_DCFI
	263	mtspr HID0, r5 /* enable + invalidate */
	264	mtspr HID0, r3 /* enable */
	265	sync
	266	blr
	267
	268	/*
	269	* Enable data cache(s) - L1 and optionally L2
	270	* Calls l2cache_enable. LR saved in r5
	271	*/
	272	_GLOBAL(dcache_enable)
	273	mfspr r3, HID0
	274	li r5, HID0_DCFI\|HID0_DLOCK
	275	andc r3, r3, r5
	276	mtspr HID0, r3 /* no invalidate, unlock */
	277	ori r3, r3, HID0_DCE
	278	ori r5, r3, HID0_DCFI
	279	mtspr HID0, r5 /* enable + invalidate */
	280	mtspr HID0, r3 /* enable */
	281	sync
6d0f6bcf	282	#ifdef CONFIG_SYS_L2
debb7354 JL	283	mflr r5
	284	bl l2cache_enable /* uses r3 and r4 */
	285	sync
	286	mtlr r5
	287	#endif
	288	blr
	289
	290
	291	/*
	292	* Disable data cache(s) - L1 and optionally L2
71edc271	293	* Calls flush_dcache and l2cache_disable_no_flush.
debb7354 JL	294	* LR saved in r4
	295	*/
	296	_GLOBAL(dcache_disable)
	297	mflr r4 /* save link register */
71edc271	298	bl flush_dcache /* uses r3 and r5 */
debb7354 JL	299	sync
	300	mfspr r3, HID0
	301	li r5, HID0_DCFI\|HID0_DLOCK
	302	andc r3, r3, r5
	303	mtspr HID0, r3 /* no invalidate, unlock */
	304	li r5, HID0_DCE\|HID0_DCFI
	305	andc r3, r3, r5 /* no enable, no invalidate */
	306	mtspr HID0, r3
	307	sync
6d0f6bcf	308	#ifdef CONFIG_SYS_L2
debb7354 JL	309	bl l2cache_disable_no_flush /* uses r3 */
	310	#endif
	311	mtlr r4 /* restore link register */
	312	blr
	313
	314	/*
	315	* Is data cache enabled?
	316	*/
	317	_GLOBAL(dcache_status)
	318	mfspr r3, HID0
	319	andi. r3, r3, HID0_DCE
	320	blr
	321
	322	/*
cccce5d0	323	* Invalidate L2 cache using L2I, assume L2 is enabled
debb7354 JL	324	*/
debb7354 JL	325	_GLOBAL(l2cache_invalidate)
cccce5d0 JL	326	mfspr r3, l2cr
	327	rlwinm. r3, r3, 0, 0, 0
	328	beq 1f
	329
	330	mfspr r3, l2cr
	331	rlwinm r3, r3, 0, 1, 31
	332
	333	#ifdef CONFIG_ALTIVEC
	334	dssall
	335	#endif
debb7354 JL	336	sync
	337	mtspr l2cr, r3
	338	sync
cccce5d0 JL	339	1: mfspr r3, l2cr
	340	oris r3, r3, L2CR_L2I@h
	341	mtspr l2cr, r3
	342
debb7354 JL	343	invl2:
debb7354 JL	344	mfspr r3, l2cr
f5a24259	345	andis. r3, r3, L2CR_L2I@h
debb7354	346	bne invl2
debb7354 JL	347	blr
	348
	349	/*
	350	* Enable L2 cache
	351	* Calls l2cache_invalidate. LR is saved in r4
	352	*/
	353	_GLOBAL(l2cache_enable)
	354	mflr r4 /* save link register */
	355	bl l2cache_invalidate /* uses r3 */
	356	sync
	357	lis r3, L2_ENABLE@h
	358	ori r3, r3, L2_ENABLE@l
	359	mtspr l2cr, r3
	360	isync
	361	mtlr r4 /* restore link register */
	362	blr
	363
	364	/*
	365	* Disable L2 cache
71edc271	366	* Calls flush_dcache. LR is saved in r4
debb7354 JL	367	*/
	368	_GLOBAL(l2cache_disable)
	369	mflr r4 /* save link register */
71edc271	370	bl flush_dcache /* uses r3 and r5 */
debb7354 JL	371	sync
	372	mtlr r4 /* restore link register */
	373	l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */
	374	lis r3, L2_INIT@h
	375	ori r3, r3, L2_INIT@l
	376	mtspr l2cr, r3
	377	isync
	378	blr