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debb7354 | 1 | /* |
cb5965fb JL |
2 | * Copyright 2006 Freescale Semiconductor |
3 | * Jeff Brown | |
debb7354 JL |
4 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
26 | #include <watchdog.h> | |
27 | #include <command.h> | |
28 | #include <asm/cache.h> | |
e34a0e91 | 29 | #include <asm/mmu.h> |
debb7354 | 30 | #include <mpc86xx.h> |
75b9d4ae | 31 | #include <tsec.h> |
4f93f8b1 | 32 | #include <asm/fsl_law.h> |
debb7354 | 33 | |
debb7354 | 34 | |
ffff3ae5 JL |
35 | int |
36 | checkcpu(void) | |
debb7354 JL |
37 | { |
38 | sys_info_t sysinfo; | |
39 | uint pvr, svr; | |
40 | uint ver; | |
41 | uint major, minor; | |
42 | uint lcrr; /* local bus clock ratio register */ | |
43 | uint clkdiv; /* clock divider portion of lcrr */ | |
6d0f6bcf | 44 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
9553df86 | 45 | volatile ccsr_gur_t *gur = &immap->im_gur; |
5c9efb36 | 46 | |
debb7354 JL |
47 | puts("Freescale PowerPC\n"); |
48 | ||
49 | pvr = get_pvr(); | |
50 | ver = PVR_VER(pvr); | |
51 | major = PVR_MAJ(pvr); | |
52 | minor = PVR_MIN(pvr); | |
53 | ||
5c9efb36 | 54 | puts("CPU:\n"); |
cb5965fb | 55 | puts(" Core: "); |
5c9efb36 | 56 | |
debb7354 JL |
57 | switch (ver) { |
58 | case PVR_VER(PVR_86xx): | |
9553df86 JL |
59 | { |
60 | uint msscr0 = mfspr(MSSCR0); | |
61 | printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); | |
62 | if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE) | |
63 | puts("\n Core1Translation Enabled"); | |
64 | debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr); | |
65 | } | |
66 | break; | |
debb7354 | 67 | default: |
ffff3ae5 JL |
68 | puts("Unknown"); |
69 | break; | |
debb7354 JL |
70 | } |
71 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); | |
72 | ||
73 | svr = get_svr(); | |
1ced1216 | 74 | ver = SVR_SOC_VER(svr); |
debb7354 JL |
75 | major = SVR_MAJ(svr); |
76 | minor = SVR_MIN(svr); | |
77 | ||
78 | puts(" System: "); | |
5c9efb36 | 79 | switch (ver) { |
debb7354 | 80 | case SVR_8641: |
d14ba6a7 | 81 | if (SVR_SUBVER(svr) == 1) { |
debb7354 | 82 | puts("8641D"); |
d14ba6a7 JL |
83 | } else { |
84 | puts("8641"); | |
85 | } | |
86 | break; | |
9553df86 JL |
87 | case SVR_8610: |
88 | puts("8610"); | |
89 | break; | |
debb7354 JL |
90 | default: |
91 | puts("Unknown"); | |
92 | break; | |
93 | } | |
94 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); | |
95 | ||
96 | get_sys_info(&sysinfo); | |
97 | ||
98 | puts(" Clocks: "); | |
99 | printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); | |
100 | printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000); | |
101 | printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); | |
5c9efb36 | 102 | |
6d0f6bcf JCPV |
103 | #if defined(CONFIG_SYS_LBC_LCRR) |
104 | lcrr = CONFIG_SYS_LBC_LCRR; | |
debb7354 JL |
105 | #else |
106 | { | |
6d0f6bcf | 107 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
ffff3ae5 | 108 | volatile ccsr_lbc_t *lbc = &immap->im_lbc; |
debb7354 | 109 | |
ffff3ae5 | 110 | lcrr = lbc->lcrr; |
debb7354 JL |
111 | } |
112 | #endif | |
113 | clkdiv = lcrr & 0x0f; | |
114 | if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { | |
115 | printf("LBC:%4lu MHz\n", | |
116 | sysinfo.freqSystemBus / 1000000 / clkdiv); | |
117 | } else { | |
118 | printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr); | |
119 | } | |
120 | ||
cb5965fb | 121 | puts(" L2: "); |
126aa70f | 122 | if (get_l2cr() & 0x80000000) |
cb5965fb | 123 | puts("Enabled\n"); |
126aa70f | 124 | else |
cb5965fb | 125 | puts("Disabled\n"); |
5c9efb36 JL |
126 | |
127 | return 0; | |
debb7354 JL |
128 | } |
129 | ||
130 | ||
debb7354 JL |
131 | static inline void |
132 | soft_restart(unsigned long addr) | |
133 | { | |
a8318ec2 | 134 | #if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD) |
5c9efb36 | 135 | |
ffff3ae5 JL |
136 | /* |
137 | * SRR0 has system reset vector, SRR1 has default MSR value | |
138 | * rfi restores MSR from SRR1 and sets the PC to the SRR0 value | |
139 | */ | |
debb7354 JL |
140 | |
141 | __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); | |
142 | __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); | |
143 | __asm__ __volatile__ ("mtspr 27, 4"); | |
144 | __asm__ __volatile__ ("rfi"); | |
145 | ||
146 | #else /* CONFIG_MPC8641HPCN */ | |
cb5965fb JL |
147 | |
148 | out8(PIXIS_BASE + PIXIS_RST, 0); | |
149 | ||
debb7354 | 150 | #endif /* !CONFIG_MPC8641HPCN */ |
cb5965fb | 151 | |
ffff3ae5 | 152 | while (1) ; /* not reached */ |
debb7354 JL |
153 | } |
154 | ||
155 | ||
126aa70f JL |
156 | /* |
157 | * No generic way to do board reset. Simply call soft_reset. | |
158 | */ | |
debb7354 | 159 | void |
126aa70f | 160 | do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
debb7354 | 161 | { |
a8318ec2 | 162 | #if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD) |
debb7354 | 163 | |
6d0f6bcf JCPV |
164 | #ifdef CONFIG_SYS_RESET_ADDRESS |
165 | ulong addr = CONFIG_SYS_RESET_ADDRESS; | |
debb7354 JL |
166 | #else |
167 | /* | |
6d0f6bcf JCPV |
168 | * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, |
169 | * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid | |
debb7354 | 170 | * address. Better pick an address known to be invalid on your |
6d0f6bcf | 171 | * system and assign it to CONFIG_SYS_RESET_ADDRESS. |
debb7354 | 172 | */ |
6d0f6bcf | 173 | ulong addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong); |
debb7354 JL |
174 | #endif |
175 | ||
5c9efb36 | 176 | /* flush and disable I/D cache */ |
debb7354 JL |
177 | __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); |
178 | __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); | |
179 | __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); | |
180 | __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); | |
181 | __asm__ __volatile__ ("sync"); | |
182 | __asm__ __volatile__ ("mtspr 1008, 4"); | |
183 | __asm__ __volatile__ ("isync"); | |
184 | __asm__ __volatile__ ("sync"); | |
185 | __asm__ __volatile__ ("mtspr 1008, 5"); | |
186 | __asm__ __volatile__ ("isync"); | |
187 | __asm__ __volatile__ ("sync"); | |
188 | ||
126aa70f | 189 | soft_restart(addr); |
debb7354 JL |
190 | |
191 | #else /* CONFIG_MPC8641HPCN */ | |
5c9efb36 | 192 | |
3d98b858 | 193 | out8(PIXIS_BASE + PIXIS_RST, 0); |
5c9efb36 | 194 | |
debb7354 | 195 | #endif /* !CONFIG_MPC8641HPCN */ |
5c9efb36 | 196 | |
ffff3ae5 | 197 | while (1) ; /* not reached */ |
debb7354 JL |
198 | } |
199 | ||
200 | ||
debb7354 JL |
201 | /* |
202 | * Get timebase clock frequency | |
203 | */ | |
ffff3ae5 JL |
204 | unsigned long |
205 | get_tbclk(void) | |
debb7354 | 206 | { |
ffff3ae5 | 207 | sys_info_t sys_info; |
debb7354 JL |
208 | |
209 | get_sys_info(&sys_info); | |
5c9efb36 | 210 | return (sys_info.freqSystemBus + 3L) / 4L; |
debb7354 JL |
211 | } |
212 | ||
debb7354 JL |
213 | |
214 | #if defined(CONFIG_WATCHDOG) | |
215 | void | |
216 | watchdog_reset(void) | |
217 | { | |
3473ab73 JJ |
218 | #if defined(CONFIG_MPC8610) |
219 | /* | |
220 | * This actually feed the hard enabled watchdog. | |
221 | */ | |
6d0f6bcf | 222 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
3473ab73 JJ |
223 | volatile ccsr_wdt_t *wdt = &immap->im_wdt; |
224 | volatile ccsr_gur_t *gur = &immap->im_gur; | |
225 | u32 tmp = gur->pordevsr; | |
226 | ||
227 | if (tmp & 0x4000) { | |
228 | wdt->swsrr = 0x556c; | |
229 | wdt->swsrr = 0xaa39; | |
230 | } | |
231 | #endif | |
debb7354 JL |
232 | } |
233 | #endif /* CONFIG_WATCHDOG */ | |
234 | ||
debb7354 JL |
235 | |
236 | #if defined(CONFIG_DDR_ECC) | |
ffff3ae5 JL |
237 | void |
238 | dma_init(void) | |
5c9efb36 | 239 | { |
6d0f6bcf | 240 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
debb7354 JL |
241 | volatile ccsr_dma_t *dma = &immap->im_dma; |
242 | ||
243 | dma->satr0 = 0x00040000; | |
244 | dma->datr0 = 0x00040000; | |
245 | asm("sync; isync"); | |
debb7354 JL |
246 | } |
247 | ||
ffff3ae5 JL |
248 | uint |
249 | dma_check(void) | |
5c9efb36 | 250 | { |
6d0f6bcf | 251 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
debb7354 JL |
252 | volatile ccsr_dma_t *dma = &immap->im_dma; |
253 | volatile uint status = dma->sr0; | |
254 | ||
255 | /* While the channel is busy, spin */ | |
ffff3ae5 | 256 | while ((status & 4) == 4) { |
debb7354 JL |
257 | status = dma->sr0; |
258 | } | |
259 | ||
260 | if (status != 0) { | |
ffff3ae5 | 261 | printf("DMA Error: status = %x\n", status); |
debb7354 JL |
262 | } |
263 | return status; | |
264 | } | |
265 | ||
ffff3ae5 JL |
266 | int |
267 | dma_xfer(void *dest, uint count, void *src) | |
5c9efb36 | 268 | { |
6d0f6bcf | 269 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
debb7354 JL |
270 | volatile ccsr_dma_t *dma = &immap->im_dma; |
271 | ||
272 | dma->dar0 = (uint) dest; | |
273 | dma->sar0 = (uint) src; | |
274 | dma->bcr0 = count; | |
275 | dma->mr0 = 0xf000004; | |
276 | asm("sync;isync"); | |
277 | dma->mr0 = 0xf000005; | |
278 | asm("sync;isync"); | |
279 | return dma_check(); | |
280 | } | |
5c9efb36 | 281 | |
debb7354 JL |
282 | #endif /* CONFIG_DDR_ECC */ |
283 | ||
284 | ||
4f93f8b1 BB |
285 | /* |
286 | * Print out the state of various machine registers. | |
e34a0e91 | 287 | * Currently prints out LAWs, BR0/OR0, and BATs |
4f93f8b1 BB |
288 | */ |
289 | void mpc86xx_reginfo(void) | |
290 | { | |
6d0f6bcf | 291 | immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
4f93f8b1 BB |
292 | ccsr_lbc_t *lbc = &immap->im_lbc; |
293 | ||
e34a0e91 | 294 | print_bats(); |
4f93f8b1 BB |
295 | print_laws(); |
296 | ||
297 | printf ("Local Bus Controller Registers\n" | |
298 | "\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0)); | |
299 | printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1)); | |
300 | printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2)); | |
301 | printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3)); | |
302 | printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4)); | |
303 | printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5)); | |
304 | printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6)); | |
305 | printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7)); | |
debb7354 JL |
306 | |
307 | } | |
dd35479a | 308 | |
75b9d4ae AF |
309 | /* |
310 | * Initializes on-chip ethernet controllers. | |
311 | * to override, implement board_eth_init() | |
dd35479a | 312 | */ |
dd35479a BW |
313 | int cpu_eth_init(bd_t *bis) |
314 | { | |
75b9d4ae AF |
315 | #if defined(CONFIG_TSEC_ENET) |
316 | tsec_standard_init(bis); | |
dd35479a | 317 | #endif |
75b9d4ae | 318 | |
dd35479a BW |
319 | return 0; |
320 | } |