[people/ms/u-boot.git] / cpu / mpc8xx / cpu.c

/*
 * (C) Copyright 2000-2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * m8xx.c
 *
 * CPU specific code
 *
 * written or collected and sometimes rewritten by
 * Magnus Damm <damm@bitsmart.com>
 *
 * minor modifications by
 * Wolfgang Denk <wd@denx.de>
 */

#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <mpc8xx.h>
#include <asm/cache.h>

#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <libfdt_env.h>
#include <fdt_support.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

static char *cpu_warning = "\n         " \
	"*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";

#if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \
     !defined(CONFIG_MPC862))

static int check_CPU (long clock, uint pvr, uint immr)
{
	char *id_str =
# if defined(CONFIG_MPC855)
	"PC855";
# elif defined(CONFIG_MPC860P)
	"PC860P";
# else
	NULL;
# endif
	volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
	uint k, m;
	char buf[32];
	char pre = 'X';
	char *mid = "xx";
	char *suf;

	/* the highest 16 bits should be 0x0050 for a 860 */

	if ((pvr >> 16) != 0x0050)
		return -1;

	k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
	m = 0;
	suf = "";

	/*
	 * Some boards use sockets so different CPUs can be used.
	 * We have to check chip version in run time.
	 */
	switch (k) {
	case 0x00020001: pre = 'P'; break;
	case 0x00030001: break;
	case 0x00120003: suf = "A"; break;
	case 0x00130003: suf = "A3"; break;

	case 0x00200004: suf = "B"; break;

	case 0x00300004: suf = "C"; break;
	case 0x00310004: suf = "C1"; m = 1; break;

	case 0x00200064: mid = "SR"; suf = "B"; break;
	case 0x00300065: mid = "SR"; suf = "C"; break;
	case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
	case 0x05010000: suf = "D3"; m = 1; break;
	case 0x05020000: suf = "D4"; m = 1; break;
		/* this value is not documented anywhere */
	case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
		/* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
	case 0x08010004:		/* Rev. A.0 */
		suf = "A";
		/* fall through */
	case 0x08000003:		/* Rev. 0.3 */
		pre = 'M'; m = 1;
		if (id_str == NULL)
			id_str =
# if defined(CONFIG_MPC852T)
		"PC852T";
# elif defined(CONFIG_MPC859T)
		"PC859T";
# elif defined(CONFIG_MPC859DSL)
		"PC859DSL";
# elif defined(CONFIG_MPC866T)
		"PC866T";
# else
		"PC866x"; /* Unknown chip from MPC866 family */
# endif
		break;
	case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
		if (id_str == NULL)
			id_str = "PC885"; /* 870/875/880/885 */
		break;

	default: suf = NULL; break;
	}

	if (id_str == NULL)
		id_str = "PC86x";	/* Unknown 86x chip */
	if (suf)
		printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
	else
		printf ("unknown M%s (0x%08x)", id_str, k);


#if defined(CONFIG_SYS_8xx_CPUCLK_MIN) && defined(CONFIG_SYS_8xx_CPUCLK_MAX)
	printf (" at %s MHz [%d.%d...%d.%d MHz]\n       ",
		strmhz (buf, clock),
		CONFIG_SYS_8xx_CPUCLK_MIN / 1000000,
		((CONFIG_SYS_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
		CONFIG_SYS_8xx_CPUCLK_MAX / 1000000,
		((CONFIG_SYS_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
	);
#else
	printf (" at %s MHz: ", strmhz (buf, clock));
#endif
	printf ("%u kB I-Cache %u kB D-Cache",
		checkicache () >> 10,
		checkdcache () >> 10
	);

	/* do we have a FEC (860T/P or 852/859/866/885)? */

	immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
	if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
		printf (" FEC present");
	}

	if (!m) {
		puts (cpu_warning);
	}

	putc ('\n');

#ifdef DEBUG
	if(clock != measure_gclk()) {
	    printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
	}
#endif

	return 0;
}

#elif defined(CONFIG_MPC862)

static int check_CPU (long clock, uint pvr, uint immr)
{
	volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
	uint k, m;
	char buf[32];
	char pre = 'X';
	char *mid = "xx";
	char *suf;

	/* the highest 16 bits should be 0x0050 for a 8xx */

	if ((pvr >> 16) != 0x0050)
		return -1;

	k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
	m = 0;

	switch (k) {

		/* this value is not documented anywhere */
	case 0x06000000: mid = "P"; suf = "0"; break;
	case 0x06010001: mid = "P"; suf = "A"; m = 1; break;
	case 0x07000003: mid = "P"; suf = "B"; m = 1; break;
	default: suf = NULL; break;
	}

#ifndef CONFIG_MPC857
	if (suf)
		printf ("%cPC862%sZPnn%s", pre, mid, suf);
	else
		printf ("unknown MPC862 (0x%08x)", k);
#else
	if (suf)
		printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */
	else
		printf ("unknown MPC857 (0x%08x)", k);
#endif

	printf (" at %s MHz:", strmhz (buf, clock));

	printf (" %u kB I-Cache", checkicache () >> 10);
	printf (" %u kB D-Cache", checkdcache () >> 10);

	/* lets check and see if we're running on a 862T (or P?) */

	immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
	if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
		printf (" FEC present");
	}

	if (!m) {
		puts (cpu_warning);
	}

	putc ('\n');

	return 0;
}

#elif defined(CONFIG_MPC823)

static int check_CPU (long clock, uint pvr, uint immr)
{
	volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
	uint k, m;
	char buf[32];
	char *suf;

	/* the highest 16 bits should be 0x0050 for a 8xx */

	if ((pvr >> 16) != 0x0050)
		return -1;

	k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
	m = 0;

	switch (k) {
		/* MPC823 */
	case 0x20000000: suf = "0"; break;
	case 0x20010000: suf = "0.1"; break;
	case 0x20020000: suf = "Z2/3"; break;
	case 0x20020001: suf = "Z3"; break;
	case 0x21000000: suf = "A"; break;
	case 0x21010000: suf = "B"; m = 1; break;
	case 0x21010001: suf = "B2"; m = 1; break;
		/* MPC823E */
	case 0x24010000: suf = NULL;
			puts ("PPC823EZTnnB2");
			m = 1;
			break;
	default:
			suf = NULL;
			printf ("unknown MPC823 (0x%08x)", k);
			break;
	}
	if (suf)
		printf ("PPC823ZTnn%s", suf);

	printf (" at %s MHz:", strmhz (buf, clock));

	printf (" %u kB I-Cache", checkicache () >> 10);
	printf (" %u kB D-Cache", checkdcache () >> 10);

	/* lets check and see if we're running on a 860T (or P?) */

	immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
	if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
		puts (" FEC present");
	}

	if (!m) {
		puts (cpu_warning);
	}

	putc ('\n');

	return 0;
}

#elif defined(CONFIG_MPC850)

static int check_CPU (long clock, uint pvr, uint immr)
{
	volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
	uint k, m;
	char buf[32];

	/* the highest 16 bits should be 0x0050 for a 8xx */

	if ((pvr >> 16) != 0x0050)
		return -1;

	k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
	m = 0;

	switch (k) {
	case 0x20020001:
		printf ("XPC850xxZT");
		break;
	case 0x21000065:
		printf ("XPC850xxZTA");
		break;
	case 0x21010067:
		printf ("XPC850xxZTB");
		m = 1;
		break;
	case 0x21020068:
		printf ("XPC850xxZTC");
		m = 1;
		break;
	default:
		printf ("unknown MPC850 (0x%08x)", k);
	}
	printf (" at %s MHz:", strmhz (buf, clock));

	printf (" %u kB I-Cache", checkicache () >> 10);
	printf (" %u kB D-Cache", checkdcache () >> 10);

	/* lets check and see if we're running on a 850T (or P?) */

	immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
	if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
		printf (" FEC present");
	}

	if (!m) {
		puts (cpu_warning);
	}

	putc ('\n');

	return 0;
}
#else
#error CPU undefined
#endif
/* ------------------------------------------------------------------------- */

int checkcpu (void)
{
	ulong clock = gd->cpu_clk;
	uint immr = get_immr (0);	/* Return full IMMR contents */
	uint pvr = get_pvr ();

	puts ("CPU:   ");

	/* 850 has PARTNUM 20 */
	/* 801 has PARTNUM 10 */
	return check_CPU (clock, pvr, immr);
}

/* ------------------------------------------------------------------------- */
/* L1 i-cache                                                                */
/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB)              */
/* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB)             */

int checkicache (void)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	u32 cacheon = rd_ic_cst () & IDC_ENABLED;

#ifdef CONFIG_IP86x
	u32 k = memctl->memc_br1 & ~0x00007fff;	/* probe in flash memoryarea */
#else
	u32 k = memctl->memc_br0 & ~0x00007fff;	/* probe in flash memoryarea */
#endif
	u32 m;
	u32 lines = -1;

	wr_ic_cst (IDC_UNALL);
	wr_ic_cst (IDC_INVALL);
	wr_ic_cst (IDC_DISABLE);
	__asm__ volatile ("isync");

	while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
		wr_ic_adr (k);
		wr_ic_cst (IDC_LDLCK);
		__asm__ volatile ("isync");

		lines++;
		k += 0x10;				/* the number of bytes in a cacheline */
	}

	wr_ic_cst (IDC_UNALL);
	wr_ic_cst (IDC_INVALL);

	if (cacheon)
		wr_ic_cst (IDC_ENABLE);
	else
		wr_ic_cst (IDC_DISABLE);

	__asm__ volatile ("isync");

	return lines << 4;
};

/* ------------------------------------------------------------------------- */
/* L1 d-cache                                                                */
/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB)              */
/* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB)              */
/* call with cache disabled                                                  */

int checkdcache (void)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	u32 cacheon = rd_dc_cst () & IDC_ENABLED;

#ifdef CONFIG_IP86x
	u32 k = memctl->memc_br1 & ~0x00007fff;	/* probe in flash memoryarea */
#else
	u32 k = memctl->memc_br0 & ~0x00007fff;	/* probe in flash memoryarea */
#endif
	u32 m;
	u32 lines = -1;

	wr_dc_cst (IDC_UNALL);
	wr_dc_cst (IDC_INVALL);
	wr_dc_cst (IDC_DISABLE);

	while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
		wr_dc_adr (k);
		wr_dc_cst (IDC_LDLCK);
		lines++;
		k += 0x10;	/* the number of bytes in a cacheline */
	}

	wr_dc_cst (IDC_UNALL);
	wr_dc_cst (IDC_INVALL);

	if (cacheon)
		wr_dc_cst (IDC_ENABLE);
	else
		wr_dc_cst (IDC_DISABLE);

	return lines << 4;
};

/* ------------------------------------------------------------------------- */

void upmconfig (uint upm, uint * table, uint size)
{
	uint i;
	uint addr = 0;
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

	for (i = 0; i < size; i++) {
		memctl->memc_mdr = table[i];	/* (16-15) */
		memctl->memc_mcr = addr | upm;	/* (16-16) */
		addr++;
	}
}

/* ------------------------------------------------------------------------- */

#ifndef CONFIG_LWMON

int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	ulong msr, addr;

	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;

	immap->im_clkrst.car_plprcr |= PLPRCR_CSR;	/* Checkstop Reset enable */

	/* Interrupts and MMU off */
	__asm__ volatile ("mtspr    81, 0");
	__asm__ volatile ("mfmsr    %0":"=r" (msr));

	msr &= ~0x1030;
	__asm__ volatile ("mtmsr    %0"::"r" (msr));

	/*
	 * Trying to execute the next instruction at a non-existing address
	 * should cause a machine check, resulting in reset
	 */
#ifdef CONFIG_SYS_RESET_ADDRESS
	addr = CONFIG_SYS_RESET_ADDRESS;
#else
	/*
	 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
	 * - sizeof (ulong) is usually a valid address. Better pick an address
	 * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
	 * "(ulong)-1" used to be a good choice for many systems...
	 */
	addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
#endif
	((void (*)(void)) addr) ();
	return 1;
}

#else	/* CONFIG_LWMON */

/*
 * On the LWMON board, the MCLR reset input of the PIC's on the board
 * uses a 47K/1n RC combination which has a 47us time  constant.  The
 * low  signal on the HRESET pin of the CPU is only 512 clocks = 8 us
 * and thus too short to reset the external hardware. So we  use  the
 * watchdog to reset the board.
 */
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	/* prevent triggering the watchdog */
	disable_interrupts ();

	/* make sure the watchdog is running */
	reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);

	/* wait for watchdog reset */
	while (1) {};

	/* NOTREACHED */
	return 1;
}

#endif	/* CONFIG_LWMON */

/* ------------------------------------------------------------------------- */

/*
 * Get timebase clock frequency (like cpu_clk in Hz)
 *
 * See sections 14.2 and 14.6 of the User's Manual
 */
unsigned long get_tbclk (void)
{
	uint immr = get_immr (0);	/* Return full IMMR contents */
	volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
	ulong oscclk, factor, pll;

	if (immap->im_clkrst.car_sccr & SCCR_TBS) {
		return (gd->cpu_clk / 16);
	}

	pll = immap->im_clkrst.car_plprcr;

#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)

	/*
	 * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
	 * factor is calculated as follows:
	 *
	 *		     MFN
	 *	     MFI + -------
	 *		   MFD + 1
	 * factor =  -----------------
	 *	     (PDF + 1) * 2^S
	 *
	 * For older chips, it's just MF field of PLPRCR plus one.
	 */
	if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
		factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
			(PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
	} else {
		factor = PLPRCR_val(MF)+1;
	}

	oscclk = gd->cpu_clk / factor;

	if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) {
		return (oscclk / 4);
	}
	return (oscclk / 16);
}

/* ------------------------------------------------------------------------- */

#if defined(CONFIG_WATCHDOG)
void watchdog_reset (void)
{
	int re_enable = disable_interrupts ();

	reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
	if (re_enable)
		enable_interrupts ();
}
#endif /* CONFIG_WATCHDOG */

#if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON)

void reset_8xx_watchdog (volatile immap_t * immr)
{
# if defined(CONFIG_LWMON)
	/*
	 * The LWMON board uses a MAX6301 Watchdog
	 * with the trigger pin connected to port PA.7
	 *
	 * (The old board version used a MAX706TESA Watchdog, which
	 * had to be handled exactly the same.)
	 */
# define WATCHDOG_BIT	0x0100
	immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT);	/* GPIO     */
	immr->im_ioport.iop_padir |= WATCHDOG_BIT;	/* Output   */
	immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT);	/* active output */

	immr->im_ioport.iop_padat ^= WATCHDOG_BIT;	/* Toggle WDI   */
# elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
	/*
	 * The KUP4 boards uses a TPS3705 Watchdog
	 * with the trigger pin connected to port PA.5
	 */
# define WATCHDOG_BIT	0x0400
	immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT);	/* GPIO     */
	immr->im_ioport.iop_padir |= WATCHDOG_BIT;	/* Output   */
	immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT);	/* active output */

	immr->im_ioport.iop_padat ^= WATCHDOG_BIT;	/* Toggle WDI   */
# else
	/*
	 * All other boards use the MPC8xx Internal Watchdog
	 */
	immr->im_siu_conf.sc_swsr = 0x556c;	/* write magic1 */
	immr->im_siu_conf.sc_swsr = 0xaa39;	/* write magic2 */
# endif /* CONFIG_LWMON */
}
#endif /* CONFIG_WATCHDOG */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2000-2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* m8xx.c
	26	*
	27	* CPU specific code
	28	*
	29	* written or collected and sometimes rewritten by
	30	* Magnus Damm <damm@bitsmart.com>
	31	*
	32	* minor modifications by
	33	* Wolfgang Denk <wd@denx.de>
	34	*/
	35
	36	#include <common.h>
	37	#include <watchdog.h>
	38	#include <command.h>
	39	#include <mpc8xx.h>
	40	#include <asm/cache.h>
	41
381e4e63 HS	42	#if defined(CONFIG_OF_LIBFDT)
	43	#include <libfdt.h>
	44	#include <libfdt_env.h>
	45	#include <fdt_support.h>
	46	#endif
	47
d87080b7 WD	48	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	49
c609719b WD	50	static char *cpu_warning = "\n " \
	51	"* Warning: CPU Core has Silicon Bugs -- Check the Errata *";
	52
2535d602	53	#if ((defined(CONFIG_MPC86x) \|\| defined(CONFIG_MPC855)) && \
c609719b	54	!defined(CONFIG_MPC862))
2535d602	55
180d3f74 WD	56	static int check_CPU (long clock, uint pvr, uint immr)
	57	{
	58	char *id_str =
2535d602	59	# if defined(CONFIG_MPC855)
180d3f74	60	"PC855";
2535d602	61	# elif defined(CONFIG_MPC860P)
180d3f74	62	"PC860P";
c609719b	63	# else
180d3f74	64	NULL;
c609719b	65	# endif
c609719b WD	66	volatile immap_t immap = (immap_t ) (immr & 0xFFFF0000);
	67	uint k, m;
	68	char buf[32];
	69	char pre = 'X';
	70	char *mid = "xx";
	71	char *suf;
	72
	73	/* the highest 16 bits should be 0x0050 for a 860 */
	74
	75	if ((pvr >> 16) != 0x0050)
	76	return -1;
	77
	78	k = (immr << 16) \| ((ushort ) & immap->im_cpm.cp_dparam[0xB0]);
	79	m = 0;
7b4fd36b	80	suf = "";
c609719b	81
180d3f74 WD	82	/*
	83	* Some boards use sockets so different CPUs can be used.
	84	* We have to check chip version in run time.
	85	*/
c609719b	86	switch (k) {
7b4fd36b WD	87	case 0x00020001: pre = 'P'; break;
7b4fd36b WD	88	case 0x00030001: break;
c609719b WD	89	case 0x00120003: suf = "A"; break;
	90	case 0x00130003: suf = "A3"; break;
	91
	92	case 0x00200004: suf = "B"; break;
	93
	94	case 0x00300004: suf = "C"; break;
2535d602	95	case 0x00310004: suf = "C1"; m = 1; break;
c609719b WD	96
	97	case 0x00200064: mid = "SR"; suf = "B"; break;
	98	case 0x00300065: mid = "SR"; suf = "C"; break;
	99	case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
	100	case 0x05010000: suf = "D3"; m = 1; break;
	101	case 0x05020000: suf = "D4"; m = 1; break;
c609719b WD	102	/* this value is not documented anywhere */
c609719b WD	103	case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
180d3f74	104	/* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
7b4fd36b WD	105	case 0x08010004: /* Rev. A.0 */
	106	suf = "A";
	107	/* fall through */
	108	case 0x08000003: /* Rev. 0.3 */
	109	pre = 'M'; m = 1;
180d3f74 WD	110	if (id_str == NULL)
	111	id_str =
	112	# if defined(CONFIG_MPC852T)
	113	"PC852T";
	114	# elif defined(CONFIG_MPC859T)
	115	"PC859T";
	116	# elif defined(CONFIG_MPC859DSL)
	117	"PC859DSL";
	118	# elif defined(CONFIG_MPC866T)
	119	"PC866T";
	120	# else
	121	"PC866x"; /* Unknown chip from MPC866 family */
	122	# endif
	123	break;
	124	case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
	125	if (id_str == NULL)
	126	id_str = "PC885"; /* 870/875/880/885 */
	127	break;
c609719b WD	128
	129	default: suf = NULL; break;
	130	}
	131
180d3f74 WD	132	if (id_str == NULL)
180d3f74 WD	133	id_str = "PC86x"; /* Unknown 86x chip */
c609719b	134	if (suf)
180d3f74	135	printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
c609719b	136	else
180d3f74	137	printf ("unknown M%s (0x%08x)", id_str, k);
c609719b	138
c609719b	139
6d0f6bcf	140	#if defined(CONFIG_SYS_8xx_CPUCLK_MIN) && defined(CONFIG_SYS_8xx_CPUCLK_MAX)
75d1ea7f WD	141	printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
75d1ea7f WD	142	strmhz (buf, clock),
6d0f6bcf JCPV	143	CONFIG_SYS_8xx_CPUCLK_MIN / 1000000,
	144	((CONFIG_SYS_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
	145	CONFIG_SYS_8xx_CPUCLK_MAX / 1000000,
	146	((CONFIG_SYS_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
75d1ea7f WD	147	);
	148	#else
	149	printf (" at %s MHz: ", strmhz (buf, clock));
	150	#endif
	151	printf ("%u kB I-Cache %u kB D-Cache",
	152	checkicache () >> 10,
	153	checkdcache () >> 10
	154	);
c609719b	155
66ca92a5	156	/* do we have a FEC (860T/P or 852/859/866/885)? */
c609719b WD	157
	158	immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
	159	if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
	160	printf (" FEC present");
	161	}
	162
	163	if (!m) {
	164	puts (cpu_warning);
	165	}
	166
	167	putc ('\n');
	168
2535d602	169	#ifdef DEBUG
42d1f039 WD	170	if(clock != measure_gclk()) {
	171	printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
	172	}
2535d602 WD	173	#endif
2535d602 WD	174
c609719b WD	175	return 0;
	176	}
	177
	178	#elif defined(CONFIG_MPC862)
	179
	180	static int check_CPU (long clock, uint pvr, uint immr)
	181	{
	182	volatile immap_t immap = (immap_t ) (immr & 0xFFFF0000);
	183	uint k, m;
	184	char buf[32];
	185	char pre = 'X';
	186	char *mid = "xx";
	187	char *suf;
	188
	189	/* the highest 16 bits should be 0x0050 for a 8xx */
	190
	191	if ((pvr >> 16) != 0x0050)
	192	return -1;
	193
	194	k = (immr << 16) \| ((ushort ) & immap->im_cpm.cp_dparam[0xB0]);
	195	m = 0;
	196
	197	switch (k) {
	198
	199	/* this value is not documented anywhere */
	200	case 0x06000000: mid = "P"; suf = "0"; break;
	201	case 0x06010001: mid = "P"; suf = "A"; m = 1; break;
	202	case 0x07000003: mid = "P"; suf = "B"; m = 1; break;
	203	default: suf = NULL; break;
	204	}
	205
f7d1572b	206	#ifndef CONFIG_MPC857
c609719b WD	207	if (suf)
	208	printf ("%cPC862%sZPnn%s", pre, mid, suf);
	209	else
	210	printf ("unknown MPC862 (0x%08x)", k);
f7d1572b WD	211	#else
	212	if (suf)
	213	printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */
	214	else
	215	printf ("unknown MPC857 (0x%08x)", k);
	216	#endif
c609719b WD	217
	218	printf (" at %s MHz:", strmhz (buf, clock));
	219
	220	printf (" %u kB I-Cache", checkicache () >> 10);
	221	printf (" %u kB D-Cache", checkdcache () >> 10);
	222
	223	/* lets check and see if we're running on a 862T (or P?) */
	224
	225	immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
	226	if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
	227	printf (" FEC present");
	228	}
	229
	230	if (!m) {
	231	puts (cpu_warning);
	232	}
	233
	234	putc ('\n');
	235
	236	return 0;
	237	}
	238
	239	#elif defined(CONFIG_MPC823)
	240
	241	static int check_CPU (long clock, uint pvr, uint immr)
	242	{
	243	volatile immap_t immap = (immap_t ) (immr & 0xFFFF0000);
	244	uint k, m;
	245	char buf[32];
	246	char *suf;
	247
	248	/* the highest 16 bits should be 0x0050 for a 8xx */
	249
	250	if ((pvr >> 16) != 0x0050)
	251	return -1;
	252
	253	k = (immr << 16) \| ((ushort ) & immap->im_cpm.cp_dparam[0xB0]);
	254	m = 0;
	255
	256	switch (k) {
	257	/* MPC823 */
	258	case 0x20000000: suf = "0"; break;
	259	case 0x20010000: suf = "0.1"; break;
	260	case 0x20020000: suf = "Z2/3"; break;
	261	case 0x20020001: suf = "Z3"; break;
	262	case 0x21000000: suf = "A"; break;
	263	case 0x21010000: suf = "B"; m = 1; break;
	264	case 0x21010001: suf = "B2"; m = 1; break;
	265	/* MPC823E */
	266	case 0x24010000: suf = NULL;
	267	puts ("PPC823EZTnnB2");
	268	m = 1;
	269	break;
	270	default:
	271	suf = NULL;
	272	printf ("unknown MPC823 (0x%08x)", k);
	273	break;
	274	}
	275	if (suf)
	276	printf ("PPC823ZTnn%s", suf);
	277
	278	printf (" at %s MHz:", strmhz (buf, clock));
	279
	280	printf (" %u kB I-Cache", checkicache () >> 10);
281	printf (" %u kB D-Cache", checkdcache () >> 10);
282
283	/* lets check and see if we're running on a 860T (or P?) */
284
285	immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
286	if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
287	puts (" FEC present");
288	}
289
290	if (!m) {
291	puts (cpu_warning);
292	}
293
294	putc ('\n');
295
296	return 0;
297	}
298
299	#elif defined(CONFIG_MPC850)
300
301	static int check_CPU (long clock, uint pvr, uint immr)
302	{
303	volatile immap_t immap = (immap_t ) (immr & 0xFFFF0000);
304	uint k, m;
305	char buf[32];
306
307	/* the highest 16 bits should be 0x0050 for a 8xx */
308
309	if ((pvr >> 16) != 0x0050)
310	return -1;
311
312	k = (immr << 16) \| ((ushort ) & immap->im_cpm.cp_dparam[0xB0]);
313	m = 0;
314
315	switch (k) {
316	case 0x20020001:
317	printf ("XPC850xxZT");
318	break;
319	case 0x21000065:
320	printf ("XPC850xxZTA");
321	break;
322	case 0x21010067:
323	printf ("XPC850xxZTB");
324	m = 1;
325	break;
326	case 0x21020068:
327	printf ("XPC850xxZTC");
328	m = 1;
329	break;
330	default:
331	printf ("unknown MPC850 (0x%08x)", k);
332	}
333	printf (" at %s MHz:", strmhz (buf, clock));
334
335	printf (" %u kB I-Cache", checkicache () >> 10);
336	printf (" %u kB D-Cache", checkdcache () >> 10);
337
338	/* lets check and see if we're running on a 850T (or P?) */
339
340	immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
341	if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
342	printf (" FEC present");
343	}
344
345	if (!m) {
346	puts (cpu_warning);
347	}
348
349	putc ('\n');
350
351	return 0;
352	}
353	#else
354	#error CPU undefined
355	#endif
356	/* ------------------------------------------------------------------------- */
357
358	int checkcpu (void)
359	{
c609719b WD	360	ulong clock = gd->cpu_clk;
	361	uint immr = get_immr (0); /* Return full IMMR contents */
	362	uint pvr = get_pvr ();
	363
	364	puts ("CPU: ");
	365
	366	/* 850 has PARTNUM 20 */
	367	/* 801 has PARTNUM 10 */
	368	return check_CPU (clock, pvr, immr);
	369	}
	370
	371	/* ------------------------------------------------------------------------- */
	372	/* L1 i-cache */
	373	/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
	374	/* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */
	375
	376	int checkicache (void)
	377	{
6d0f6bcf	378	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
c609719b WD	379	volatile memctl8xx_t *memctl = &immap->im_memctl;
	380	u32 cacheon = rd_ic_cst () & IDC_ENABLED;
	381
2535d602	382	#ifdef CONFIG_IP86x
c609719b WD	383	u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
	384	#else
	385	u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
	386	#endif
	387	u32 m;
	388	u32 lines = -1;
	389
	390	wr_ic_cst (IDC_UNALL);
	391	wr_ic_cst (IDC_INVALL);
	392	wr_ic_cst (IDC_DISABLE);
	393	__asm__ volatile ("isync");
	394
	395	while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
	396	wr_ic_adr (k);
	397	wr_ic_cst (IDC_LDLCK);
	398	__asm__ volatile ("isync");
	399
	400	lines++;
	401	k += 0x10; /* the number of bytes in a cacheline */
	402	}
	403
	404	wr_ic_cst (IDC_UNALL);
	405	wr_ic_cst (IDC_INVALL);
	406
	407	if (cacheon)
	408	wr_ic_cst (IDC_ENABLE);
	409	else
	410	wr_ic_cst (IDC_DISABLE);
	411
	412	__asm__ volatile ("isync");
	413
	414	return lines << 4;
	415	};
	416
	417	/* ------------------------------------------------------------------------- */
	418	/* L1 d-cache */
	419	/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
	420	/* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */
	421	/* call with cache disabled */
	422
	423	int checkdcache (void)
	424	{
6d0f6bcf	425	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
c609719b WD	426	volatile memctl8xx_t *memctl = &immap->im_memctl;
	427	u32 cacheon = rd_dc_cst () & IDC_ENABLED;
	428
2535d602	429	#ifdef CONFIG_IP86x
c609719b WD	430	u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
	431	#else
	432	u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
	433	#endif
	434	u32 m;
	435	u32 lines = -1;
	436
	437	wr_dc_cst (IDC_UNALL);
	438	wr_dc_cst (IDC_INVALL);
	439	wr_dc_cst (IDC_DISABLE);
	440
	441	while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
	442	wr_dc_adr (k);
	443	wr_dc_cst (IDC_LDLCK);
	444	lines++;
	445	k += 0x10; /* the number of bytes in a cacheline */
	446	}
	447
	448	wr_dc_cst (IDC_UNALL);
	449	wr_dc_cst (IDC_INVALL);
	450
	451	if (cacheon)
	452	wr_dc_cst (IDC_ENABLE);
	453	else
	454	wr_dc_cst (IDC_DISABLE);
	455
	456	return lines << 4;
	457	};
	458
	459	/* ------------------------------------------------------------------------- */
	460
	461	void upmconfig (uint upm, uint * table, uint size)
	462	{
	463	uint i;
	464	uint addr = 0;
6d0f6bcf	465	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
c609719b WD	466	volatile memctl8xx_t *memctl = &immap->im_memctl;
	467
	468	for (i = 0; i < size; i++) {
	469	memctl->memc_mdr = table[i]; /* (16-15) */
	470	memctl->memc_mcr = addr \| upm; /* (16-16) */
	471	addr++;
	472	}
	473	}
	474
	475	/* ------------------------------------------------------------------------- */
	476
ed16fefc WD	477	#ifndef CONFIG_LWMON
ed16fefc WD	478
8bde7f77	479	int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char argv[])
c609719b WD	480	{
	481	ulong msr, addr;
	482
6d0f6bcf	483	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
c609719b WD	484
	485	immap->im_clkrst.car_plprcr \|= PLPRCR_CSR; /* Checkstop Reset enable */
	486
	487	/* Interrupts and MMU off */
	488	__asm__ volatile ("mtspr 81, 0");
	489	__asm__ volatile ("mfmsr %0":"=r" (msr));
	490
	491	msr &= ~0x1030;
	492	__asm__ volatile ("mtmsr %0"::"r" (msr));
	493
	494	/*
	495	* Trying to execute the next instruction at a non-existing address
	496	* should cause a machine check, resulting in reset
	497	*/
6d0f6bcf JCPV	498	#ifdef CONFIG_SYS_RESET_ADDRESS
6d0f6bcf JCPV	499	addr = CONFIG_SYS_RESET_ADDRESS;
c609719b WD	500	#else
c609719b WD	501	/*
6d0f6bcf	502	* note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
c609719b	503	* - sizeof (ulong) is usually a valid address. Better pick an address
6d0f6bcf	504	* known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
c609719b WD	505	* "(ulong)-1" used to be a good choice for many systems...
c609719b WD	506	*/
6d0f6bcf	507	addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
c609719b WD	508	#endif
	509	((void (*)(void)) addr) ();
	510	return 1;
	511	}
	512
ed16fefc WD	513	#else /* CONFIG_LWMON */
	514
	515	/*
	516	* On the LWMON board, the MCLR reset input of the PIC's on the board
	517	* uses a 47K/1n RC combination which has a 47us time constant. The
	518	* low signal on the HRESET pin of the CPU is only 512 clocks = 8 us
	519	* and thus too short to reset the external hardware. So we use the
	520	* watchdog to reset the board.
	521	*/
	522	int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	523	{
	524	/* prevent triggering the watchdog */
	525	disable_interrupts ();
	526
	527	/* make sure the watchdog is running */
6d0f6bcf	528	reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
ed16fefc WD	529
	530	/* wait for watchdog reset */
	531	while (1) {};
	532
	533	/* NOTREACHED */
	534	return 1;
	535	}
	536
	537	#endif /* CONFIG_LWMON */
	538
c609719b WD	539	/* ------------------------------------------------------------------------- */
	540
	541	/*
	542	* Get timebase clock frequency (like cpu_clk in Hz)
	543	*
180d3f74	544	* See sections 14.2 and 14.6 of the User's Manual
c609719b WD	545	*/
	546	unsigned long get_tbclk (void)
	547	{
180d3f74 WD	548	uint immr = get_immr (0); /* Return full IMMR contents */
	549	volatile immap_t immap = (volatile immap_t )(immr & 0xFFFF0000);
	550	ulong oscclk, factor, pll;
c609719b	551
180d3f74	552	if (immap->im_clkrst.car_sccr & SCCR_TBS) {
c609719b WD	553	return (gd->cpu_clk / 16);
c609719b WD	554	}
2535d602	555
180d3f74 WD	556	pll = immap->im_clkrst.car_plprcr;
	557
	558	#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
	559
	560	/*
	561	* For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
	562	* factor is calculated as follows:
	563	*
	564	* MFN
	565	* MFI + -------
	566	* MFD + 1
	567	* factor = -----------------
	568	* (PDF + 1) * 2^S
	569	*
	570	* For older chips, it's just MF field of PLPRCR plus one.
	571	*/
b0aef11c	572	if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
180d3f74 WD	573	factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
	574	(PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
	575	} else {
	576	factor = PLPRCR_val(MF)+1;
	577	}
c609719b WD	578
	579	oscclk = gd->cpu_clk / factor;
	580
180d3f74	581	if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 \|\| factor > 2) {
c609719b WD	582	return (oscclk / 4);
	583	}
	584	return (oscclk / 16);
	585	}
	586
	587	/* ------------------------------------------------------------------------- */
	588
	589	#if defined(CONFIG_WATCHDOG)
	590	void watchdog_reset (void)
	591	{
	592	int re_enable = disable_interrupts ();
	593
6d0f6bcf	594	reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
c609719b WD	595	if (re_enable)
	596	enable_interrupts ();
	597	}
ed16fefc WD	598	#endif /* CONFIG_WATCHDOG */
	599
	600	#if defined(CONFIG_WATCHDOG) \|\| defined(CONFIG_LWMON)
c609719b WD	601
	602	void reset_8xx_watchdog (volatile immap_t * immr)
	603	{
	604	# if defined(CONFIG_LWMON)
	605	/*
	606	* The LWMON board uses a MAX6301 Watchdog
	607	* with the trigger pin connected to port PA.7
	608	*
	609	* (The old board version used a MAX706TESA Watchdog, which
	610	* had to be handled exactly the same.)
	611	*/
	612	# define WATCHDOG_BIT 0x0100
	613	immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
	614	immr->im_ioport.iop_padir \|= WATCHDOG_BIT; /* Output */
	615	immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
	616
02b11f8e WD	617	immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
	618	# elif defined(CONFIG_KUP4K) \|\| defined(CONFIG_KUP4X)
	619	/*
	620	* The KUP4 boards uses a TPS3705 Watchdog
	621	* with the trigger pin connected to port PA.5
	622	*/
	623	# define WATCHDOG_BIT 0x0400
	624	immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
	625	immr->im_ioport.iop_padir \|= WATCHDOG_BIT; /* Output */
	626	immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
	627
c609719b WD	628	immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
	629	# else
	630	/*
	631	* All other boards use the MPC8xx Internal Watchdog
	632	*/
	633	immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
	634	immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
	635	# endif /* CONFIG_LWMON */
	636	}
c609719b	637	#endif /* CONFIG_WATCHDOG */