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4a9cbbe8 WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <commproc.h> | |
26 | #include <command.h> | |
281e00a3 | 27 | #include <serial.h> |
d0fb80c3 | 28 | #include <watchdog.h> |
4a9cbbe8 | 29 | |
d87080b7 WD |
30 | DECLARE_GLOBAL_DATA_PTR; |
31 | ||
4a9cbbe8 WD |
32 | #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */ |
33 | ||
34 | #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */ | |
35 | #define SMC_INDEX 0 | |
4a9cbbe8 WD |
36 | #define PROFF_SMC PROFF_SMC1 |
37 | #define CPM_CR_CH_SMC CPM_CR_CH_SMC1 | |
38 | ||
39 | #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */ | |
40 | #define SMC_INDEX 1 | |
4a9cbbe8 WD |
41 | #define PROFF_SMC PROFF_SMC2 |
42 | #define CPM_CR_CH_SMC CPM_CR_CH_SMC2 | |
43 | ||
281e00a3 WD |
44 | #endif /* CONFIG_8xx_CONS_SMCx */ |
45 | ||
46 | #if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */ | |
4a9cbbe8 WD |
47 | #define SCC_INDEX 0 |
48 | #define PROFF_SCC PROFF_SCC1 | |
49 | #define CPM_CR_CH_SCC CPM_CR_CH_SCC1 | |
50 | ||
51 | #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */ | |
4a9cbbe8 WD |
52 | #define SCC_INDEX 1 |
53 | #define PROFF_SCC PROFF_SCC2 | |
54 | #define CPM_CR_CH_SCC CPM_CR_CH_SCC2 | |
55 | ||
56 | #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */ | |
4a9cbbe8 WD |
57 | #define SCC_INDEX 2 |
58 | #define PROFF_SCC PROFF_SCC3 | |
59 | #define CPM_CR_CH_SCC CPM_CR_CH_SCC3 | |
60 | ||
61 | #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */ | |
4a9cbbe8 WD |
62 | #define SCC_INDEX 3 |
63 | #define PROFF_SCC PROFF_SCC4 | |
64 | #define CPM_CR_CH_SCC CPM_CR_CH_SCC4 | |
65 | ||
281e00a3 | 66 | #endif /* CONFIG_8xx_CONS_SCCx */ |
4a9cbbe8 | 67 | |
2535d602 WD |
68 | static void serial_setdivisor(volatile cpm8xx_t *cp) |
69 | { | |
75d1ea7f | 70 | int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate; |
2535d602 WD |
71 | |
72 | if(divisor/16>0x1000) { | |
73 | /* bad divisor, assume 50Mhz clock and 9600 baud */ | |
75d1ea7f | 74 | divisor=(50*1000*1000 + 8*9600)/16/9600; |
2535d602 WD |
75 | } |
76 | ||
6d0f6bcf JCPV |
77 | #ifdef CONFIG_SYS_BRGCLK_PRESCALE |
78 | divisor /= CONFIG_SYS_BRGCLK_PRESCALE; | |
3bbc899f WD |
79 | #endif |
80 | ||
2535d602 WD |
81 | if(divisor<=0x1000) { |
82 | cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN; | |
83 | } else { | |
84 | cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16; | |
85 | } | |
86 | } | |
87 | ||
4a9cbbe8 WD |
88 | #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2)) |
89 | ||
90 | /* | |
91 | * Minimal serial functions needed to use one of the SMC ports | |
92 | * as serial console interface. | |
93 | */ | |
94 | ||
281e00a3 WD |
95 | static void smc_setbrg (void) |
96 | { | |
6d0f6bcf | 97 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
281e00a3 WD |
98 | volatile cpm8xx_t *cp = &(im->im_cpm); |
99 | ||
100 | /* Set up the baud rate generator. | |
101 | * See 8xx_io/commproc.c for details. | |
102 | * | |
103 | * Wire BRG1 to SMCx | |
104 | */ | |
105 | ||
106 | cp->cp_simode = 0x00000000; | |
107 | ||
108 | serial_setdivisor(cp); | |
109 | } | |
110 | ||
111 | static int smc_init (void) | |
4a9cbbe8 | 112 | { |
6d0f6bcf | 113 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 WD |
114 | volatile smc_t *sp; |
115 | volatile smc_uart_t *up; | |
116 | volatile cbd_t *tbdf, *rbdf; | |
117 | volatile cpm8xx_t *cp = &(im->im_cpm); | |
118 | #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850)) | |
119 | volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport); | |
120 | #endif | |
121 | uint dpaddr; | |
122 | ||
123 | /* initialize pointers to SMC */ | |
124 | ||
125 | sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]); | |
126 | up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC]; | |
6d0f6bcf | 127 | #ifdef CONFIG_SYS_SMC_UCODE_PATCH |
b423d055 HS |
128 | up = (smc_uart_t *) &cp->cp_dpmem[up->smc_rpbase]; |
129 | #else | |
130 | /* Disable relocation */ | |
131 | up->smc_rpbase = 0; | |
132 | #endif | |
4a9cbbe8 WD |
133 | |
134 | /* Disable transmitter/receiver. | |
135 | */ | |
136 | sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); | |
137 | ||
138 | /* Enable SDMA. | |
139 | */ | |
140 | im->im_siu_conf.sc_sdcr = 1; | |
141 | ||
142 | /* clear error conditions */ | |
6d0f6bcf JCPV |
143 | #ifdef CONFIG_SYS_SDSR |
144 | im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR; | |
4a9cbbe8 WD |
145 | #else |
146 | im->im_sdma.sdma_sdsr = 0x83; | |
147 | #endif | |
148 | ||
149 | /* clear SDMA interrupt mask */ | |
6d0f6bcf JCPV |
150 | #ifdef CONFIG_SYS_SDMR |
151 | im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR; | |
4a9cbbe8 WD |
152 | #else |
153 | im->im_sdma.sdma_sdmr = 0x00; | |
154 | #endif | |
155 | ||
156 | #if defined(CONFIG_8xx_CONS_SMC1) | |
157 | /* Use Port B for SMC1 instead of other functions. | |
158 | */ | |
159 | cp->cp_pbpar |= 0x000000c0; | |
160 | cp->cp_pbdir &= ~0x000000c0; | |
161 | cp->cp_pbodr &= ~0x000000c0; | |
162 | #else /* CONFIG_8xx_CONS_SMC2 */ | |
163 | # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850) | |
164 | /* Use Port A for SMC2 instead of other functions. | |
165 | */ | |
166 | ip->iop_papar |= 0x00c0; | |
167 | ip->iop_padir &= ~0x00c0; | |
168 | ip->iop_paodr &= ~0x00c0; | |
169 | # else /* must be a 860 then */ | |
170 | /* Use Port B for SMC2 instead of other functions. | |
171 | */ | |
172 | cp->cp_pbpar |= 0x00000c00; | |
173 | cp->cp_pbdir &= ~0x00000c00; | |
174 | cp->cp_pbodr &= ~0x00000c00; | |
175 | # endif | |
176 | #endif | |
177 | ||
b028f715 | 178 | #if defined(CONFIG_FADS) || defined(CONFIG_ADS) |
4a9cbbe8 WD |
179 | /* Enable RS232 */ |
180 | #if defined(CONFIG_8xx_CONS_SMC1) | |
181 | *((uint *) BCSR1) &= ~BCSR1_RS232EN_1; | |
182 | #else | |
183 | *((uint *) BCSR1) &= ~BCSR1_RS232EN_2; | |
184 | #endif | |
185 | #endif /* CONFIG_FADS */ | |
186 | ||
187 | #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) | |
188 | /* Enable Monitor Port Transceiver */ | |
189 | *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ; | |
190 | #endif /* CONFIG_RPXLITE */ | |
191 | ||
192 | /* Set the physical address of the host memory buffers in | |
193 | * the buffer descriptors. | |
194 | */ | |
195 | ||
6d0f6bcf | 196 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
4a9cbbe8 WD |
197 | dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ; |
198 | #else | |
199 | dpaddr = CPM_SERIAL_BASE ; | |
200 | #endif | |
201 | ||
202 | /* Allocate space for two buffer descriptors in the DP ram. | |
203 | * For now, this address seems OK, but it may have to | |
204 | * change with newer versions of the firmware. | |
205 | * damm: allocating space after the two buffers for rx/tx data | |
206 | */ | |
207 | ||
208 | rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; | |
209 | rbdf->cbd_bufaddr = (uint) (rbdf+2); | |
210 | rbdf->cbd_sc = 0; | |
211 | tbdf = rbdf + 1; | |
212 | tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; | |
213 | tbdf->cbd_sc = 0; | |
214 | ||
215 | /* Set up the uart parameters in the parameter ram. | |
216 | */ | |
217 | up->smc_rbase = dpaddr; | |
218 | up->smc_tbase = dpaddr+sizeof(cbd_t); | |
219 | up->smc_rfcr = SMC_EB; | |
220 | up->smc_tfcr = SMC_EB; | |
6d0f6bcf | 221 | #if defined (CONFIG_SYS_SMC_UCODE_PATCH) |
b423d055 HS |
222 | up->smc_rbptr = up->smc_rbase; |
223 | up->smc_tbptr = up->smc_tbase; | |
224 | up->smc_rstate = 0; | |
225 | up->smc_tstate = 0; | |
226 | #endif | |
4a9cbbe8 WD |
227 | |
228 | #if defined(CONFIG_MBX) | |
229 | board_serial_init(); | |
230 | #endif /* CONFIG_MBX */ | |
231 | ||
232 | /* Set UART mode, 8 bit, no parity, one stop. | |
233 | * Enable receive and transmit. | |
234 | */ | |
235 | sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; | |
236 | ||
237 | /* Mask all interrupts and remove anything pending. | |
238 | */ | |
239 | sp->smc_smcm = 0; | |
240 | sp->smc_smce = 0xff; | |
241 | ||
6d0f6bcf | 242 | #ifdef CONFIG_SYS_SPC1920_SMC1_CLK4 |
8139567b | 243 | /* clock source is PLD */ |
2a8dfe08 | 244 | |
8139567b | 245 | /* set freq to 19200 Baud */ |
6d0f6bcf | 246 | *((volatile uchar *) CONFIG_SYS_SPC1920_PLD_BASE+6) = 0x3; |
8139567b MK |
247 | /* configure clk4 as input */ |
248 | im->im_ioport.iop_pdpar |= 0x800; | |
249 | im->im_ioport.iop_pddir &= ~0x800; | |
f11033e7 | 250 | |
2a8dfe08 | 251 | cp->cp_simode = ((cp->cp_simode & ~0xf000) | 0x7000); |
b02d0177 MK |
252 | #else |
253 | /* Set up the baud rate generator */ | |
281e00a3 | 254 | smc_setbrg (); |
b02d0177 | 255 | #endif |
4a9cbbe8 WD |
256 | |
257 | /* Make the first buffer the only buffer. | |
258 | */ | |
259 | tbdf->cbd_sc |= BD_SC_WRAP; | |
260 | rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; | |
261 | ||
262 | /* Single character receive. | |
263 | */ | |
264 | up->smc_mrblr = 1; | |
265 | up->smc_maxidl = 0; | |
266 | ||
267 | /* Initialize Tx/Rx parameters. | |
268 | */ | |
269 | ||
270 | while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ | |
271 | ; | |
272 | ||
273 | cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG; | |
274 | ||
275 | while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ | |
276 | ; | |
277 | ||
278 | /* Enable transmitter/receiver. | |
279 | */ | |
280 | sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; | |
281 | ||
282 | return (0); | |
283 | } | |
284 | ||
281e00a3 WD |
285 | static void |
286 | smc_putc(const char c) | |
4a9cbbe8 WD |
287 | { |
288 | volatile cbd_t *tbdf; | |
289 | volatile char *buf; | |
290 | volatile smc_uart_t *up; | |
6d0f6bcf | 291 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 WD |
292 | volatile cpm8xx_t *cpmp = &(im->im_cpm); |
293 | ||
4532cb69 | 294 | #ifdef CONFIG_MODEM_SUPPORT |
4532cb69 WD |
295 | if (gd->be_quiet) |
296 | return; | |
297 | #endif | |
298 | ||
4a9cbbe8 | 299 | if (c == '\n') |
281e00a3 | 300 | smc_putc ('\r'); |
4a9cbbe8 WD |
301 | |
302 | up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; | |
6d0f6bcf | 303 | #ifdef CONFIG_SYS_SMC_UCODE_PATCH |
b423d055 HS |
304 | up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; |
305 | #endif | |
4a9cbbe8 WD |
306 | |
307 | tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase]; | |
308 | ||
309 | /* Wait for last character to go. | |
310 | */ | |
311 | ||
312 | buf = (char *)tbdf->cbd_bufaddr; | |
4a9cbbe8 WD |
313 | |
314 | *buf = c; | |
315 | tbdf->cbd_datlen = 1; | |
316 | tbdf->cbd_sc |= BD_SC_READY; | |
317 | __asm__("eieio"); | |
d0fb80c3 WD |
318 | |
319 | while (tbdf->cbd_sc & BD_SC_READY) { | |
320 | WATCHDOG_RESET (); | |
4a9cbbe8 | 321 | __asm__("eieio"); |
d0fb80c3 | 322 | } |
4a9cbbe8 WD |
323 | } |
324 | ||
281e00a3 WD |
325 | static void |
326 | smc_puts (const char *s) | |
327 | { | |
328 | while (*s) { | |
329 | smc_putc (*s++); | |
330 | } | |
331 | } | |
332 | ||
333 | static int | |
334 | smc_getc(void) | |
4a9cbbe8 WD |
335 | { |
336 | volatile cbd_t *rbdf; | |
337 | volatile unsigned char *buf; | |
338 | volatile smc_uart_t *up; | |
6d0f6bcf | 339 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 WD |
340 | volatile cpm8xx_t *cpmp = &(im->im_cpm); |
341 | unsigned char c; | |
342 | ||
343 | up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; | |
6d0f6bcf | 344 | #ifdef CONFIG_SYS_SMC_UCODE_PATCH |
b423d055 HS |
345 | up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; |
346 | #endif | |
4a9cbbe8 WD |
347 | |
348 | rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; | |
349 | ||
350 | /* Wait for character to show up. | |
351 | */ | |
352 | buf = (unsigned char *)rbdf->cbd_bufaddr; | |
d0fb80c3 | 353 | |
4a9cbbe8 | 354 | while (rbdf->cbd_sc & BD_SC_EMPTY) |
d0fb80c3 WD |
355 | WATCHDOG_RESET (); |
356 | ||
4a9cbbe8 WD |
357 | c = *buf; |
358 | rbdf->cbd_sc |= BD_SC_EMPTY; | |
359 | ||
360 | return(c); | |
361 | } | |
362 | ||
281e00a3 WD |
363 | static int |
364 | smc_tstc(void) | |
4a9cbbe8 WD |
365 | { |
366 | volatile cbd_t *rbdf; | |
367 | volatile smc_uart_t *up; | |
6d0f6bcf | 368 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 WD |
369 | volatile cpm8xx_t *cpmp = &(im->im_cpm); |
370 | ||
371 | up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; | |
6d0f6bcf | 372 | #ifdef CONFIG_SYS_SMC_UCODE_PATCH |
b423d055 HS |
373 | up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; |
374 | #endif | |
4a9cbbe8 WD |
375 | |
376 | rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; | |
377 | ||
378 | return(!(rbdf->cbd_sc & BD_SC_EMPTY)); | |
379 | } | |
380 | ||
281e00a3 WD |
381 | struct serial_device serial_smc_device = |
382 | { | |
383 | "serial_smc", | |
384 | "SMC", | |
385 | smc_init, | |
386 | smc_setbrg, | |
387 | smc_getc, | |
388 | smc_tstc, | |
389 | smc_putc, | |
390 | smc_puts, | |
391 | }; | |
392 | ||
393 | #endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */ | |
394 | ||
395 | #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \ | |
396 | defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) | |
397 | ||
398 | static void | |
399 | scc_setbrg (void) | |
400 | { | |
6d0f6bcf | 401 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
281e00a3 | 402 | volatile cpm8xx_t *cp = &(im->im_cpm); |
4a9cbbe8 | 403 | |
281e00a3 WD |
404 | /* Set up the baud rate generator. |
405 | * See 8xx_io/commproc.c for details. | |
406 | * | |
407 | * Wire BRG1 to SCCx | |
408 | */ | |
409 | ||
410 | cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX)); | |
411 | ||
412 | serial_setdivisor(cp); | |
413 | } | |
414 | ||
415 | static int scc_init (void) | |
4a9cbbe8 | 416 | { |
6d0f6bcf | 417 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 WD |
418 | volatile scc_t *sp; |
419 | volatile scc_uart_t *up; | |
420 | volatile cbd_t *tbdf, *rbdf; | |
421 | volatile cpm8xx_t *cp = &(im->im_cpm); | |
422 | uint dpaddr; | |
423 | #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850) | |
424 | volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport); | |
425 | #endif | |
426 | ||
427 | /* initialize pointers to SCC */ | |
428 | ||
429 | sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]); | |
430 | up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC]; | |
431 | ||
432 | #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2) | |
433 | { /* Disable Ethernet, enable Serial */ | |
434 | uchar c; | |
435 | ||
436 | c = pic_read (0x61); | |
437 | c &= ~0x40; /* enable COM3 */ | |
438 | c |= 0x80; /* disable Ethernet */ | |
439 | pic_write (0x61, c); | |
440 | ||
441 | /* enable RTS2 */ | |
442 | cp->cp_pbpar |= 0x2000; | |
443 | cp->cp_pbdat |= 0x2000; | |
444 | cp->cp_pbdir |= 0x2000; | |
445 | } | |
446 | #endif /* CONFIG_LWMON */ | |
447 | ||
448 | /* Disable transmitter/receiver. | |
449 | */ | |
450 | sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
451 | ||
452 | #if (SCC_INDEX == 2) && defined(CONFIG_MPC850) | |
453 | /* | |
454 | * The MPC850 has SCC3 on Port B | |
455 | */ | |
456 | cp->cp_pbpar |= 0x06; | |
457 | cp->cp_pbdir &= ~0x06; | |
458 | cp->cp_pbodr &= ~0x06; | |
459 | ||
460 | #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860) | |
461 | /* | |
462 | * Standard configuration for SCC's is on Part A | |
463 | */ | |
464 | ip->iop_papar |= ((3 << (2 * SCC_INDEX))); | |
465 | ip->iop_padir &= ~((3 << (2 * SCC_INDEX))); | |
466 | ip->iop_paodr &= ~((3 << (2 * SCC_INDEX))); | |
467 | #else | |
468 | /* | |
469 | * The IP860 has SCC3 and SCC4 on Port D | |
470 | */ | |
471 | ip->iop_pdpar |= ((3 << (2 * SCC_INDEX))); | |
472 | #endif | |
473 | ||
474 | /* Allocate space for two buffer descriptors in the DP ram. | |
475 | */ | |
476 | ||
6d0f6bcf | 477 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
4a9cbbe8 WD |
478 | dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ; |
479 | #else | |
281e00a3 | 480 | dpaddr = CPM_SERIAL2_BASE ; |
4a9cbbe8 WD |
481 | #endif |
482 | ||
483 | /* Enable SDMA. | |
484 | */ | |
485 | im->im_siu_conf.sc_sdcr = 0x0001; | |
486 | ||
487 | /* Set the physical address of the host memory buffers in | |
488 | * the buffer descriptors. | |
489 | */ | |
490 | ||
491 | rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; | |
492 | rbdf->cbd_bufaddr = (uint) (rbdf+2); | |
493 | rbdf->cbd_sc = 0; | |
494 | tbdf = rbdf + 1; | |
495 | tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; | |
496 | tbdf->cbd_sc = 0; | |
497 | ||
498 | /* Set up the baud rate generator. | |
499 | */ | |
281e00a3 | 500 | scc_setbrg (); |
4a9cbbe8 WD |
501 | |
502 | /* Set up the uart parameters in the parameter ram. | |
503 | */ | |
504 | up->scc_genscc.scc_rbase = dpaddr; | |
505 | up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); | |
506 | ||
507 | /* Initialize Tx/Rx parameters. | |
508 | */ | |
509 | while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ | |
510 | ; | |
511 | cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG; | |
512 | ||
513 | while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ | |
514 | ; | |
515 | ||
516 | up->scc_genscc.scc_rfcr = SCC_EB | 0x05; | |
517 | up->scc_genscc.scc_tfcr = SCC_EB | 0x05; | |
518 | ||
519 | up->scc_genscc.scc_mrblr = 1; /* Single character receive */ | |
520 | up->scc_maxidl = 0; /* disable max idle */ | |
521 | up->scc_brkcr = 1; /* send one break character on stop TX */ | |
522 | up->scc_parec = 0; | |
523 | up->scc_frmec = 0; | |
524 | up->scc_nosec = 0; | |
525 | up->scc_brkec = 0; | |
526 | up->scc_uaddr1 = 0; | |
527 | up->scc_uaddr2 = 0; | |
528 | up->scc_toseq = 0; | |
529 | up->scc_char1 = 0x8000; | |
530 | up->scc_char2 = 0x8000; | |
531 | up->scc_char3 = 0x8000; | |
532 | up->scc_char4 = 0x8000; | |
533 | up->scc_char5 = 0x8000; | |
534 | up->scc_char6 = 0x8000; | |
535 | up->scc_char7 = 0x8000; | |
536 | up->scc_char8 = 0x8000; | |
537 | up->scc_rccm = 0xc0ff; | |
538 | ||
539 | /* Set low latency / small fifo. | |
540 | */ | |
541 | sp->scc_gsmrh = SCC_GSMRH_RFW; | |
542 | ||
543 | /* Set SCC(x) clock mode to 16x | |
544 | * See 8xx_io/commproc.c for details. | |
545 | * | |
546 | * Wire BRG1 to SCCn | |
547 | */ | |
548 | ||
549 | /* Set UART mode, clock divider 16 on Tx and Rx | |
550 | */ | |
281e00a3 | 551 | sp->scc_gsmrl &= ~0xF; |
4a9cbbe8 WD |
552 | sp->scc_gsmrl |= |
553 | (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); | |
554 | ||
281e00a3 | 555 | sp->scc_psmr = 0; |
4a9cbbe8 WD |
556 | sp->scc_psmr |= SCU_PSMR_CL; |
557 | ||
558 | /* Mask all interrupts and remove anything pending. | |
559 | */ | |
560 | sp->scc_sccm = 0; | |
561 | sp->scc_scce = 0xffff; | |
562 | sp->scc_dsr = 0x7e7e; | |
563 | sp->scc_psmr = 0x3000; | |
564 | ||
565 | /* Make the first buffer the only buffer. | |
566 | */ | |
567 | tbdf->cbd_sc |= BD_SC_WRAP; | |
568 | rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; | |
569 | ||
570 | /* Enable transmitter/receiver. | |
571 | */ | |
572 | sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
573 | ||
574 | return (0); | |
575 | } | |
576 | ||
281e00a3 WD |
577 | static void |
578 | scc_putc(const char c) | |
4a9cbbe8 WD |
579 | { |
580 | volatile cbd_t *tbdf; | |
581 | volatile char *buf; | |
582 | volatile scc_uart_t *up; | |
6d0f6bcf | 583 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 WD |
584 | volatile cpm8xx_t *cpmp = &(im->im_cpm); |
585 | ||
281e00a3 | 586 | #ifdef CONFIG_MODEM_SUPPORT |
281e00a3 WD |
587 | if (gd->be_quiet) |
588 | return; | |
589 | #endif | |
590 | ||
4a9cbbe8 | 591 | if (c == '\n') |
281e00a3 | 592 | scc_putc ('\r'); |
4a9cbbe8 WD |
593 | |
594 | up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; | |
595 | ||
596 | tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase]; | |
597 | ||
598 | /* Wait for last character to go. | |
599 | */ | |
600 | ||
601 | buf = (char *)tbdf->cbd_bufaddr; | |
4a9cbbe8 WD |
602 | |
603 | *buf = c; | |
604 | tbdf->cbd_datlen = 1; | |
605 | tbdf->cbd_sc |= BD_SC_READY; | |
606 | __asm__("eieio"); | |
d0fb80c3 WD |
607 | |
608 | while (tbdf->cbd_sc & BD_SC_READY) { | |
4a9cbbe8 | 609 | __asm__("eieio"); |
d0fb80c3 WD |
610 | WATCHDOG_RESET (); |
611 | } | |
4a9cbbe8 WD |
612 | } |
613 | ||
281e00a3 WD |
614 | static void |
615 | scc_puts (const char *s) | |
616 | { | |
617 | while (*s) { | |
618 | scc_putc (*s++); | |
619 | } | |
620 | } | |
621 | ||
622 | static int | |
623 | scc_getc(void) | |
4a9cbbe8 WD |
624 | { |
625 | volatile cbd_t *rbdf; | |
626 | volatile unsigned char *buf; | |
627 | volatile scc_uart_t *up; | |
6d0f6bcf | 628 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 WD |
629 | volatile cpm8xx_t *cpmp = &(im->im_cpm); |
630 | unsigned char c; | |
631 | ||
632 | up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; | |
633 | ||
634 | rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase]; | |
635 | ||
636 | /* Wait for character to show up. | |
637 | */ | |
638 | buf = (unsigned char *)rbdf->cbd_bufaddr; | |
d0fb80c3 | 639 | |
4a9cbbe8 | 640 | while (rbdf->cbd_sc & BD_SC_EMPTY) |
d0fb80c3 WD |
641 | WATCHDOG_RESET (); |
642 | ||
4a9cbbe8 WD |
643 | c = *buf; |
644 | rbdf->cbd_sc |= BD_SC_EMPTY; | |
645 | ||
646 | return(c); | |
647 | } | |
648 | ||
281e00a3 WD |
649 | static int |
650 | scc_tstc(void) | |
4a9cbbe8 WD |
651 | { |
652 | volatile cbd_t *rbdf; | |
653 | volatile scc_uart_t *up; | |
6d0f6bcf | 654 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 WD |
655 | volatile cpm8xx_t *cpmp = &(im->im_cpm); |
656 | ||
657 | up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; | |
658 | ||
659 | rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase]; | |
660 | ||
661 | return(!(rbdf->cbd_sc & BD_SC_EMPTY)); | |
662 | } | |
663 | ||
281e00a3 WD |
664 | struct serial_device serial_scc_device = |
665 | { | |
666 | "serial_scc", | |
667 | "SCC", | |
668 | scc_init, | |
669 | scc_setbrg, | |
670 | scc_getc, | |
671 | scc_tstc, | |
672 | scc_putc, | |
673 | scc_puts, | |
674 | }; | |
675 | ||
676 | #endif /* CONFIG_8xx_CONS_SCCx */ | |
4a9cbbe8 | 677 | |
281e00a3 WD |
678 | #ifdef CONFIG_MODEM_SUPPORT |
679 | void disable_putc(void) | |
4a9cbbe8 | 680 | { |
281e00a3 | 681 | gd->be_quiet = 1; |
4a9cbbe8 WD |
682 | } |
683 | ||
281e00a3 WD |
684 | void enable_putc(void) |
685 | { | |
281e00a3 WD |
686 | gd->be_quiet = 0; |
687 | } | |
688 | #endif | |
4a9cbbe8 | 689 | |
4431283c | 690 | #if defined(CONFIG_CMD_KGDB) |
4a9cbbe8 WD |
691 | |
692 | void | |
693 | kgdb_serial_init(void) | |
694 | { | |
281e00a3 WD |
695 | int i = -1; |
696 | ||
697 | if (strcmp(default_serial_console()->ctlr, "SMC") == 0) | |
698 | { | |
4a9cbbe8 | 699 | #if defined(CONFIG_8xx_CONS_SMC1) |
281e00a3 | 700 | i = 1; |
4a9cbbe8 | 701 | #elif defined(CONFIG_8xx_CONS_SMC2) |
281e00a3 WD |
702 | i = 2; |
703 | #endif | |
704 | } | |
705 | else if (strcmp(default_serial_console()->ctlr, "SMC") == 0) | |
706 | { | |
707 | #if defined(CONFIG_8xx_CONS_SCC1) | |
708 | i = 1; | |
4a9cbbe8 | 709 | #elif defined(CONFIG_8xx_CONS_SCC2) |
281e00a3 | 710 | i = 2; |
4a9cbbe8 | 711 | #elif defined(CONFIG_8xx_CONS_SCC3) |
281e00a3 | 712 | i = 3; |
4a9cbbe8 | 713 | #elif defined(CONFIG_8xx_CONS_SCC4) |
281e00a3 | 714 | i = 4; |
4a9cbbe8 | 715 | #endif |
281e00a3 WD |
716 | } |
717 | ||
718 | if (i >= 0) | |
719 | { | |
720 | serial_printf("[on %s%d] ", default_serial_console()->ctlr, i); | |
721 | } | |
4a9cbbe8 WD |
722 | } |
723 | ||
724 | void | |
725 | putDebugChar (int c) | |
726 | { | |
727 | serial_putc (c); | |
728 | } | |
729 | ||
730 | void | |
731 | putDebugStr (const char *str) | |
732 | { | |
733 | serial_puts (str); | |
734 | } | |
735 | ||
736 | int | |
737 | getDebugChar (void) | |
738 | { | |
739 | return serial_getc(); | |
740 | } | |
741 | ||
742 | void | |
743 | kgdb_interruptible (int yes) | |
744 | { | |
745 | return; | |
746 | } | |
068b60a0 | 747 | #endif |
4a9cbbe8 WD |
748 | |
749 | #endif /* CONFIG_8xx_CONS_NONE */ |