[people/ms/u-boot.git] / cpu / mpc8xx / speed.c

/*
 * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc8xx.h>
#include <asm/processor.h>

DECLARE_GLOBAL_DATA_PTR;

#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CONFIG_SYS_MEASURE_CPUCLK) || defined(DEBUG)

#define PITC_SHIFT 16
#define PITR_SHIFT 16
/* pitc values to time for 58/8192 seconds (about 70.8 milliseconds) */
#define SPEED_PIT_COUNTS 58
#define SPEED_PITC	 ((SPEED_PIT_COUNTS - 1) << PITC_SHIFT)
#define SPEED_PITC_INIT	 ((SPEED_PIT_COUNTS + 1) << PITC_SHIFT)

/* Access functions for the Machine State Register */
static __inline__ unsigned long get_msr(void)
{
	unsigned long msr;

	asm volatile("mfmsr %0" : "=r" (msr) :);
	return msr;
}

static __inline__ void set_msr(unsigned long msr)
{
	asm volatile("mtmsr %0" : : "r" (msr));
}

/* ------------------------------------------------------------------------- */

/*
 * Measure CPU clock speed (core clock GCLK1, GCLK2),
 * also determine bus clock speed (checking bus divider factor)
 *
 * (Approx. GCLK frequency in Hz)
 *
 * Initializes timer 2 and PIT, but disables them before return.
 * [Use timer 2, because MPC823 CPUs mask 0.x do not have timers 3 and 4]
 *
 * When measuring the CPU clock against the PIT, we count cpu clocks
 * for 58/8192 seconds with a prescale divide by 177 for the cpu clock.
 * These strange values for the timing interval and prescaling are used
 * because the formula for the CPU clock is:
 *
 *    CPU clock = count * (177 * (8192 / 58))
 *
 *		= count * 24999.7241
 *
 *    which is very close to
 *
 *		= count * 25000
 *
 * Since the count gives the CPU clock divided by 25000, we can get
 * the CPU clock rounded to the nearest 0.1 MHz by
 *
 *    CPU clock = ((count + 2) / 4) * 100000;
 *
 * The rounding is important since the measurement is sometimes going
 * to be high or low by 0.025 MHz, depending on exactly how the clocks
 * and counters interact. By rounding we get the exact answer for any
 * CPU clock that is an even multiple of 0.1 MHz.
 */

unsigned long measure_gclk(void)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer;
	ulong timer2_val;
	ulong msr_val;

#ifdef CONFIG_SYS_8XX_XIN
	/* dont use OSCM, only use EXTCLK/512 */
	immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
#else
	immr->im_clkrst.car_sccr &= ~(SCCR_RTSEL | SCCR_RTDIV);
#endif

	/* Reset + Stop Timer 2, no cascading
	 */
	timerp->cpmt_tgcr &= ~(TGCR_CAS2 | TGCR_RST2);

	/* Keep stopped, halt in debug mode
	 */
	timerp->cpmt_tgcr |= (TGCR_FRZ2 | TGCR_STP2);

	/* Timer 2 setup:
	 * Output ref. interrupt disable, int. clock
	 * Prescale by 177. Note that prescaler divides by value + 1
	 * so we must subtract 1 here.
	 */
	timerp->cpmt_tmr2 = ((177 - 1) << TMR_PS_SHIFT) | TMR_ICLK_IN_GEN;

	timerp->cpmt_tcn2 = 0;		/* reset state		*/
	timerp->cpmt_tgcr |= TGCR_RST2;	/* enable timer 2	*/

	/*
	 * PIT setup:
	 *
	 * We want to time for SPEED_PITC_COUNTS counts (of 8192 Hz),
	 * so the count value would be SPEED_PITC_COUNTS - 1.
	 * But there would be an uncertainty in the start time of 1/4
	 * count since when we enable the PIT the count is not
	 * synchronized to the 32768 Hz oscillator. The trick here is
	 * to start the count higher and wait until the PIT count
	 * changes to the required value before starting timer 2.
	 *
	 * One count high should be enough, but occasionally the start
	 * is off by 1 or 2 counts of 32768 Hz. With the start value
	 * set two counts high it seems very reliable.
	 */

	immr->im_sitk.sitk_pitck = KAPWR_KEY;	/* PIT initialization */
	immr->im_sit.sit_pitc = SPEED_PITC_INIT;

	immr->im_sitk.sitk_piscrk = KAPWR_KEY;
	immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;

	/*
	 * Start measurement - disable interrupts, just in case
	 */
	msr_val = get_msr ();
	set_msr (msr_val & ~MSR_EE);

	immr->im_sit.sit_piscr |= PISCR_PTE;

	/* spin until get exact count when we want to start */
	while (immr->im_sit.sit_pitr > SPEED_PITC);

	timerp->cpmt_tgcr &= ~TGCR_STP2;	/* Start Timer 2	*/
	while ((immr->im_sit.sit_piscr & PISCR_PS) == 0);
	timerp->cpmt_tgcr |= TGCR_STP2;		/* Stop  Timer 2	*/

	/* re-enable external interrupts if they were on */
	set_msr (msr_val);

	/* Disable timer and PIT
	 */
	timer2_val = timerp->cpmt_tcn2;		/* save before reset timer */

	timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2);
	immr->im_sit.sit_piscr &= ~PISCR_PTE;

#if defined(CONFIG_SYS_8XX_XIN)
	/* not using OSCM, using XIN, so scale appropriately */
	return (((timer2_val + 2) / 4) * (CONFIG_SYS_8XX_XIN/512))/8192 * 100000L;
#else
	return ((timer2_val + 2) / 4) * 100000L;	/* convert to Hz	*/
#endif
}

#endif

void get_brgclk(uint sccr)
{
	uint divider = 0;

	switch((sccr&SCCR_DFBRG11)>>11){
		case 0:
			divider = 1;
			break;
		case 1:
			divider = 4;
			break;
		case 2:
			divider = 16;
			break;
		case 3:
			divider = 64;
			break;
	}
	gd->brg_clk = gd->cpu_clk/divider;
}

#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)

/*
 * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
 * or (if it is not defined) measure_gclk() (which uses the ref clock)
 * from above.
 */
int get_clocks (void)
{
	uint immr = get_immr (0);	/* Return full IMMR contents */
	volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
	uint sccr = immap->im_clkrst.car_sccr;
	/*
	 * If for some reason measuring the gclk frequency won't
	 * work, we return the hardwired value.
	 * (For example, the cogent CMA286-60 CPU module has no
	 * separate oscillator for PITRTCLK)
	 */
#if defined(CONFIG_8xx_GCLK_FREQ)
	gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
#elif defined(CONFIG_8xx_OSCLK)
#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
	uint pll = immap->im_clkrst.car_plprcr;
	uint clk;

	if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
		clk = ((CONFIG_8xx_OSCLK / (PLPRCR_val(PDF)+1)) *
		       (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD)+1))) /
			(1<<PLPRCR_val(S));
	} else {
		clk = CONFIG_8xx_OSCLK * (PLPRCR_val(MF)+1);
	}
	if (pll & PLPRCR_CSRC) {	/* Low frequency division factor is used  */
		gd->cpu_clk = clk / (2 << ((sccr >> 8) & 7));
	} else {			/* High frequency division factor is used */
		gd->cpu_clk = clk / (1 << ((sccr >> 5) & 7));
	}
#else
	gd->cpu_clk = measure_gclk();
#endif /* CONFIG_8xx_GCLK_FREQ */

	if ((sccr & SCCR_EBDF11) == 0) {
		/* No Bus Divider active */
		gd->bus_clk = gd->cpu_clk;
	} else {
		/* The MPC8xx has only one BDF: half clock speed */
		gd->bus_clk = gd->cpu_clk / 2;
	}

	get_brgclk(sccr);

	return (0);
}

#else /* CONFIG_8xx_CPUCLK_DEFAULT defined, use dynamic clock setting */

static long init_pll_866 (long clk);

/* This function sets up PLL (init_pll_866() is called) and
 * fills gd->cpu_clk and gd->bus_clk according to the environment
 * variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk'
 * contains invalid value).
 * This functions requires an MPC866 or newer series CPU.
 */
int get_clocks_866 (void)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	char		  tmp[64];
	long		  cpuclk = 0;
	long		  sccr_reg;

	if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0)
		cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;

	if ((CONFIG_SYS_8xx_CPUCLK_MIN > cpuclk) || (CONFIG_SYS_8xx_CPUCLK_MAX < cpuclk))
		cpuclk = CONFIG_8xx_CPUCLK_DEFAULT;

	gd->cpu_clk = init_pll_866 (cpuclk);
#if defined(CONFIG_SYS_MEASURE_CPUCLK)
	gd->cpu_clk = measure_gclk ();
#endif

	get_brgclk(immr->im_clkrst.car_sccr);

	/* if cpu clock <= 66 MHz then set bus division factor to 1,
	 * otherwise set it to 2
	 */
	sccr_reg = immr->im_clkrst.car_sccr;
	sccr_reg &= ~SCCR_EBDF11;

	if (gd->cpu_clk <= 66000000) {
		sccr_reg |= SCCR_EBDF00;	/* bus division factor = 1 */
		gd->bus_clk = gd->cpu_clk;
	} else {
		sccr_reg |= SCCR_EBDF01;	/* bus division factor = 2 */
		gd->bus_clk = gd->cpu_clk / 2;
	}
	immr->im_clkrst.car_sccr = sccr_reg;

	return (0);
}

/* Adjust sdram refresh rate to actual CPU clock.
 */
int sdram_adjust_866 (void)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	long		  mamr;

	mamr = immr->im_memctl.memc_mamr;
	mamr &= ~MAMR_PTA_MSK;
	mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
	immr->im_memctl.memc_mamr = mamr;

	return (0);
}

/* Configure PLL for MPC866/859/885 CPU series
 * PLL multiplication factor is set to the value nearest to the desired clk,
 * assuming a oscclk of 10 MHz.
 */
static long init_pll_866 (long clk)
{
	extern void plprcr_write_866 (long);

	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	long		  n, plprcr;
	char		  mfi, mfn, mfd, s, pdf;
	long		  step_mfi, step_mfn;

	if (clk < 20000000) {
		clk *= 2;
		pdf = 1;
	} else {
		pdf = 0;
	}

	if (clk < 40000000) {
		s = 2;
		step_mfi = CONFIG_8xx_OSCLK / 4;
		mfd = 7;
		step_mfn = CONFIG_8xx_OSCLK / 30;
	} else if (clk < 80000000) {
		s = 1;
		step_mfi = CONFIG_8xx_OSCLK / 2;
		mfd = 14;
		step_mfn = CONFIG_8xx_OSCLK / 30;
	} else {
		s = 0;
		step_mfi = CONFIG_8xx_OSCLK;
		mfd = 29;
		step_mfn = CONFIG_8xx_OSCLK / 30;
	}

	/* Calculate integer part of multiplication factor
	 */
	n = clk / step_mfi;
	mfi = (char)n;

	/* Calculate numerator of fractional part of multiplication factor
	 */
	n = clk - (n * step_mfi);
	mfn = (char)(n / step_mfn);

	/* Calculate effective clk
	 */
	n = ((mfi * step_mfi) + (mfn * step_mfn)) / (pdf + 1);

	immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;

	plprcr = (immr->im_clkrst.car_plprcr & ~(PLPRCR_MFN_MSK
			| PLPRCR_MFD_MSK | PLPRCR_S_MSK
			| PLPRCR_MFI_MSK | PLPRCR_DBRMO
			| PLPRCR_PDF_MSK))
			| (mfn << PLPRCR_MFN_SHIFT)
			| (mfd << PLPRCR_MFD_SHIFT)
			| (s << PLPRCR_S_SHIFT)
			| (mfi << PLPRCR_MFI_SHIFT)
			| (pdf << PLPRCR_PDF_SHIFT);

	if( (mfn > 0) && ((mfd / mfn) > 10) )
		plprcr |= PLPRCR_DBRMO;

	plprcr_write_866 (plprcr);		/* set value using SIU4/9 workaround */
	immr->im_clkrstk.cark_plprcrk = 0x00000000;

	return (n);
}

#endif /* CONFIG_8xx_CPUCLK_DEFAULT */

#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
    && !defined(CONFIG_TQM885D)
/*
 * Adjust sdram refresh rate to actual CPU clock
 * and set timebase source according to actual CPU clock
 */
int adjust_sdram_tbs_8xx (void)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	long		  mamr;
	long              sccr;

	mamr = immr->im_memctl.memc_mamr;
	mamr &= ~MAMR_PTA_MSK;
	mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
	immr->im_memctl.memc_mamr = mamr;

	if (gd->cpu_clk < 67000000) {
		sccr = immr->im_clkrst.car_sccr;
		sccr |= SCCR_TBS;
		immr->im_clkrst.car_sccr = sccr;
	}

	return (0);
}
#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */

/* ------------------------------------------------------------------------- */
Commit	Line	Data
4a9cbbe8	1	/*
d4ca31c4	2	* (C) Copyright 2000-2004
4a9cbbe8 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <mpc8xx.h>
	26	#include <asm/processor.h>
	27
d87080b7 WD	28	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	29
6d0f6bcf	30	#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) \|\| defined(CONFIG_SYS_MEASURE_CPUCLK) \|\| defined(DEBUG)
c178d3da	31
4a9cbbe8 WD	32	#define PITC_SHIFT 16
	33	#define PITR_SHIFT 16
	34	/* pitc values to time for 58/8192 seconds (about 70.8 milliseconds) */
	35	#define SPEED_PIT_COUNTS 58
	36	#define SPEED_PITC ((SPEED_PIT_COUNTS - 1) << PITC_SHIFT)
	37	#define SPEED_PITC_INIT ((SPEED_PIT_COUNTS + 1) << PITC_SHIFT)
	38
4a9cbbe8 WD	39	/* Access functions for the Machine State Register */
	40	static __inline__ unsigned long get_msr(void)
	41	{
	42	unsigned long msr;
	43
	44	asm volatile("mfmsr %0" : "=r" (msr) :);
	45	return msr;
	46	}
	47
	48	static __inline__ void set_msr(unsigned long msr)
	49	{
	50	asm volatile("mtmsr %0" : : "r" (msr));
	51	}
4a9cbbe8 WD	52
	53	/* ------------------------------------------------------------------------- */
	54
	55	/*
	56	* Measure CPU clock speed (core clock GCLK1, GCLK2),
	57	* also determine bus clock speed (checking bus divider factor)
	58	*
	59	* (Approx. GCLK frequency in Hz)
	60	*
	61	* Initializes timer 2 and PIT, but disables them before return.
	62	* [Use timer 2, because MPC823 CPUs mask 0.x do not have timers 3 and 4]
	63	*
	64	* When measuring the CPU clock against the PIT, we count cpu clocks
	65	* for 58/8192 seconds with a prescale divide by 177 for the cpu clock.
	66	* These strange values for the timing interval and prescaling are used
	67	* because the formula for the CPU clock is:
	68	*
a2d18bb7	69	* CPU clock = count * (177 * (8192 / 58))
4a9cbbe8	70	*
a2d18bb7	71	* = count * 24999.7241
4a9cbbe8	72	*
a2d18bb7	73	* which is very close to
4a9cbbe8	74	*
a2d18bb7	75	* = count * 25000
4a9cbbe8 WD	76	*
	77	* Since the count gives the CPU clock divided by 25000, we can get
	78	* the CPU clock rounded to the nearest 0.1 MHz by
	79	*
a2d18bb7	80	* CPU clock = ((count + 2) / 4) * 100000;
4a9cbbe8 WD	81	*
	82	* The rounding is important since the measurement is sometimes going
	83	* to be high or low by 0.025 MHz, depending on exactly how the clocks
	84	* and counters interact. By rounding we get the exact answer for any
	85	* CPU clock that is an even multiple of 0.1 MHz.
	86	*/
	87
2535d602	88	unsigned long measure_gclk(void)
4a9cbbe8	89	{
6d0f6bcf	90	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
4a9cbbe8 WD	91	volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer;
	92	ulong timer2_val;
	93	ulong msr_val;
	94
6d0f6bcf	95	#ifdef CONFIG_SYS_8XX_XIN
42d1f039 WD	96	/* dont use OSCM, only use EXTCLK/512 */
42d1f039 WD	97	immr->im_clkrst.car_sccr \|= SCCR_RTSEL \| SCCR_RTDIV;
2535d602	98	#else
42d1f039	99	immr->im_clkrst.car_sccr &= ~(SCCR_RTSEL \| SCCR_RTDIV);
2535d602 WD	100	#endif
2535d602 WD	101
4a9cbbe8 WD	102	/* Reset + Stop Timer 2, no cascading
	103	*/
	104	timerp->cpmt_tgcr &= ~(TGCR_CAS2 \| TGCR_RST2);
	105
	106	/* Keep stopped, halt in debug mode
	107	*/
	108	timerp->cpmt_tgcr \|= (TGCR_FRZ2 \| TGCR_STP2);
	109
	110	/* Timer 2 setup:
	111	* Output ref. interrupt disable, int. clock
	112	* Prescale by 177. Note that prescaler divides by value + 1
	113	* so we must subtract 1 here.
	114	*/
	115	timerp->cpmt_tmr2 = ((177 - 1) << TMR_PS_SHIFT) \| TMR_ICLK_IN_GEN;
	116
a2d18bb7 WD	117	timerp->cpmt_tcn2 = 0; /* reset state */
a2d18bb7 WD	118	timerp->cpmt_tgcr \|= TGCR_RST2; /* enable timer 2 */
4a9cbbe8 WD	119
	120	/*
	121	* PIT setup:
	122	*
8bde7f77 WD	123	* We want to time for SPEED_PITC_COUNTS counts (of 8192 Hz),
	124	* so the count value would be SPEED_PITC_COUNTS - 1.
	125	* But there would be an uncertainty in the start time of 1/4
	126	* count since when we enable the PIT the count is not
	127	* synchronized to the 32768 Hz oscillator. The trick here is
	128	* to start the count higher and wait until the PIT count
	129	* changes to the required value before starting timer 2.
4a9cbbe8	130	*
8bde7f77 WD	131	* One count high should be enough, but occasionally the start
	132	* is off by 1 or 2 counts of 32768 Hz. With the start value
	133	* set two counts high it seems very reliable.
	134	*/
4a9cbbe8 WD	135
	136	immr->im_sitk.sitk_pitck = KAPWR_KEY; /* PIT initialization */
	137	immr->im_sit.sit_pitc = SPEED_PITC_INIT;
	138
	139	immr->im_sitk.sitk_piscrk = KAPWR_KEY;
6d0f6bcf	140	immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
4a9cbbe8 WD	141
	142	/*
	143	* Start measurement - disable interrupts, just in case
	144	*/
	145	msr_val = get_msr ();
	146	set_msr (msr_val & ~MSR_EE);
	147
	148	immr->im_sit.sit_piscr \|= PISCR_PTE;
	149
	150	/* spin until get exact count when we want to start */
	151	while (immr->im_sit.sit_pitr > SPEED_PITC);
	152
a2d18bb7	153	timerp->cpmt_tgcr &= ~TGCR_STP2; /* Start Timer 2 */
4a9cbbe8	154	while ((immr->im_sit.sit_piscr & PISCR_PS) == 0);
a2d18bb7	155	timerp->cpmt_tgcr \|= TGCR_STP2; /* Stop Timer 2 */
4a9cbbe8 WD	156
	157	/* re-enable external interrupts if they were on */
	158	set_msr (msr_val);
	159
	160	/* Disable timer and PIT
	161	*/
	162	timer2_val = timerp->cpmt_tcn2; /* save before reset timer */
	163
	164	timerp->cpmt_tgcr &= ~(TGCR_RST2 \| TGCR_FRZ2 \| TGCR_STP2);
	165	immr->im_sit.sit_piscr &= ~PISCR_PTE;
	166
6d0f6bcf	167	#if defined(CONFIG_SYS_8XX_XIN)
42d1f039	168	/* not using OSCM, using XIN, so scale appropriately */
6d0f6bcf	169	return (((timer2_val + 2) / 4) * (CONFIG_SYS_8XX_XIN/512))/8192 * 100000L;
2535d602	170	#else
a2d18bb7	171	return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */
2535d602 WD	172	#endif
	173	}
	174
75d1ea7f WD	175	#endif
75d1ea7f WD	176
77ff7b74 BD	177	void get_brgclk(uint sccr)
	178	{
	179	uint divider = 0;
	180
	181	switch((sccr&SCCR_DFBRG11)>>11){
	182	case 0:
	183	divider = 1;
	184	break;
	185	case 1:
	186	divider = 4;
	187	break;
	188	case 2:
	189	divider = 16;
	190	break;
	191	case 3:
	192	divider = 64;
	193	break;
	194	}
	195	gd->brg_clk = gd->cpu_clk/divider;
	196	}
	197
66ca92a5	198	#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
75d1ea7f	199
2535d602 WD	200	/*
	201	* get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
	202	* or (if it is not defined) measure_gclk() (which uses the ref clock)
	203	* from above.
	204	*/
	205	int get_clocks (void)
	206	{
1114257c WD	207	uint immr = get_immr (0); /* Return full IMMR contents */
	208	volatile immap_t immap = (immap_t ) (immr & 0xFFFF0000);
	209	uint sccr = immap->im_clkrst.car_sccr;
4a9cbbe8	210	/*
8bde7f77 WD	211	* If for some reason measuring the gclk frequency won't
	212	* work, we return the hardwired value.
	213	* (For example, the cogent CMA286-60 CPU module has no
	214	* separate oscillator for PITRTCLK)
4a9cbbe8	215	*/
1114257c	216	#if defined(CONFIG_8xx_GCLK_FREQ)
4a9cbbe8	217	gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
1114257c WD	218	#elif defined(CONFIG_8xx_OSCLK)
	219	#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
	220	uint pll = immap->im_clkrst.car_plprcr;
	221	uint clk;
	222
	223	if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
	224	clk = ((CONFIG_8xx_OSCLK / (PLPRCR_val(PDF)+1)) *
	225	(PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD)+1))) /
	226	(1<<PLPRCR_val(S));
	227	} else {
	228	clk = CONFIG_8xx_OSCLK * (PLPRCR_val(MF)+1);
	229	}
	230	if (pll & PLPRCR_CSRC) { /* Low frequency division factor is used */
	231	gd->cpu_clk = clk / (2 << ((sccr >> 8) & 7));
	232	} else { /* High frequency division factor is used */
	233	gd->cpu_clk = clk / (1 << ((sccr >> 5) & 7));
	234	}
	235	#else
	236	gd->cpu_clk = measure_gclk();
4a9cbbe8 WD	237	#endif /* CONFIG_8xx_GCLK_FREQ */
4a9cbbe8 WD	238
1114257c	239	if ((sccr & SCCR_EBDF11) == 0) {
4a9cbbe8 WD	240	/* No Bus Divider active */
	241	gd->bus_clk = gd->cpu_clk;
	242	} else {
	243	/* The MPC8xx has only one BDF: half clock speed */
	244	gd->bus_clk = gd->cpu_clk / 2;
	245	}
	246
77ff7b74 BD	247	get_brgclk(sccr);
77ff7b74 BD	248
4a9cbbe8 WD	249	return (0);
	250	}
	251
66ca92a5	252	#else /* CONFIG_8xx_CPUCLK_DEFAULT defined, use dynamic clock setting */
c178d3da WD	253
	254	static long init_pll_866 (long clk);
	255
	256	/* This function sets up PLL (init_pll_866() is called) and
	257	* fills gd->cpu_clk and gd->bus_clk according to the environment
66ca92a5	258	* variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk'
c178d3da	259	* contains invalid value).
66ca92a5	260	* This functions requires an MPC866 or newer series CPU.
c178d3da WD	261	*/
	262	int get_clocks_866 (void)
	263	{
6d0f6bcf	264	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
a2d18bb7 WD	265	char tmp[64];
	266	long cpuclk = 0;
	267	long sccr_reg;
c178d3da WD	268
	269	if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0)
	270	cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
	271
6d0f6bcf	272	if ((CONFIG_SYS_8xx_CPUCLK_MIN > cpuclk) \|\| (CONFIG_SYS_8xx_CPUCLK_MAX < cpuclk))
66ca92a5	273	cpuclk = CONFIG_8xx_CPUCLK_DEFAULT;
c178d3da WD	274
c178d3da WD	275	gd->cpu_clk = init_pll_866 (cpuclk);
6d0f6bcf	276	#if defined(CONFIG_SYS_MEASURE_CPUCLK)
75d1ea7f WD	277	gd->cpu_clk = measure_gclk ();
75d1ea7f WD	278	#endif
c178d3da	279
77ff7b74 BD	280	get_brgclk(immr->im_clkrst.car_sccr);
77ff7b74 BD	281
a2d18bb7 WD	282	/* if cpu clock <= 66 MHz then set bus division factor to 1,
	283	* otherwise set it to 2
	284	*/
	285	sccr_reg = immr->im_clkrst.car_sccr;
	286	sccr_reg &= ~SCCR_EBDF11;
22d1a56c	287
a2d18bb7 WD	288	if (gd->cpu_clk <= 66000000) {
a2d18bb7 WD	289	sccr_reg \|= SCCR_EBDF00; /* bus division factor = 1 */
c178d3da	290	gd->bus_clk = gd->cpu_clk;
a2d18bb7 WD	291	} else {
a2d18bb7 WD	292	sccr_reg \|= SCCR_EBDF01; /* bus division factor = 2 */
c178d3da	293	gd->bus_clk = gd->cpu_clk / 2;
a2d18bb7 WD	294	}
a2d18bb7 WD	295	immr->im_clkrst.car_sccr = sccr_reg;
c178d3da WD	296
	297	return (0);
	298	}
	299
	300	/* Adjust sdram refresh rate to actual CPU clock.
	301	*/
	302	int sdram_adjust_866 (void)
	303	{
6d0f6bcf	304	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
a2d18bb7	305	long mamr;
c178d3da WD	306
	307	mamr = immr->im_memctl.memc_mamr;
	308	mamr &= ~MAMR_PTA_MSK;
6d0f6bcf	309	mamr \|= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
c178d3da WD	310	immr->im_memctl.memc_mamr = mamr;
	311
	312	return (0);
	313	}
	314
66ca92a5	315	/* Configure PLL for MPC866/859/885 CPU series
c178d3da WD	316	* PLL multiplication factor is set to the value nearest to the desired clk,
	317	* assuming a oscclk of 10 MHz.
	318	*/
	319	static long init_pll_866 (long clk)
	320	{
	321	extern void plprcr_write_866 (long);
	322
6d0f6bcf	323	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
a2d18bb7 WD	324	long n, plprcr;
	325	char mfi, mfn, mfd, s, pdf;
	326	long step_mfi, step_mfn;
c178d3da	327
75d1ea7f WD	328	if (clk < 20000000) {
	329	clk *= 2;
	330	pdf = 1;
	331	} else {
	332	pdf = 0;
	333	}
	334
	335	if (clk < 40000000) {
	336	s = 2;
66ca92a5	337	step_mfi = CONFIG_8xx_OSCLK / 4;
75d1ea7f	338	mfd = 7;
66ca92a5	339	step_mfn = CONFIG_8xx_OSCLK / 30;
75d1ea7f	340	} else if (clk < 80000000) {
c178d3da	341	s = 1;
66ca92a5	342	step_mfi = CONFIG_8xx_OSCLK / 2;
c178d3da	343	mfd = 14;
66ca92a5	344	step_mfn = CONFIG_8xx_OSCLK / 30;
c178d3da WD	345	} else {
c178d3da WD	346	s = 0;
66ca92a5	347	step_mfi = CONFIG_8xx_OSCLK;
c178d3da	348	mfd = 29;
66ca92a5	349	step_mfn = CONFIG_8xx_OSCLK / 30;
c178d3da WD	350	}
	351
	352	/* Calculate integer part of multiplication factor
	353	*/
	354	n = clk / step_mfi;
	355	mfi = (char)n;
	356
	357	/* Calculate numerator of fractional part of multiplication factor
	358	*/
	359	n = clk - (n * step_mfi);
	360	mfn = (char)(n / step_mfn);
	361
	362	/* Calculate effective clk
	363	*/
75d1ea7f	364	n = ((mfi * step_mfi) + (mfn * step_mfn)) / (pdf + 1);
c178d3da WD	365
	366	immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
	367
	368	plprcr = (immr->im_clkrst.car_plprcr & ~(PLPRCR_MFN_MSK
	369	\| PLPRCR_MFD_MSK \| PLPRCR_S_MSK
75d1ea7f WD	370	\| PLPRCR_MFI_MSK \| PLPRCR_DBRMO
75d1ea7f WD	371	\| PLPRCR_PDF_MSK))
c178d3da WD	372	\| (mfn << PLPRCR_MFN_SHIFT)
	373	\| (mfd << PLPRCR_MFD_SHIFT)
	374	\| (s << PLPRCR_S_SHIFT)
	375	\| (mfi << PLPRCR_MFI_SHIFT)
	376	\| (pdf << PLPRCR_PDF_SHIFT);
	377
	378	if( (mfn > 0) && ((mfd / mfn) > 10) )
	379	plprcr \|= PLPRCR_DBRMO;
	380
	381	plprcr_write_866 (plprcr); /* set value using SIU4/9 workaround */
	382	immr->im_clkrstk.cark_plprcrk = 0x00000000;
	383
	384	return (n);
	385	}
	386
66ca92a5	387	#endif /* CONFIG_8xx_CPUCLK_DEFAULT */
c178d3da	388
090eb735 MK	389	#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
090eb735 MK	390	&& !defined(CONFIG_TQM885D)
e9132ea9 WD	391	/*
	392	* Adjust sdram refresh rate to actual CPU clock
	393	* and set timebase source according to actual CPU clock
	394	*/
	395	int adjust_sdram_tbs_8xx (void)
	396	{
6d0f6bcf	397	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
e9132ea9 WD	398	long mamr;
	399	long sccr;
	400
	401	mamr = immr->im_memctl.memc_mamr;
	402	mamr &= ~MAMR_PTA_MSK;
6d0f6bcf	403	mamr \|= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
e9132ea9 WD	404	immr->im_memctl.memc_mamr = mamr;
	405
	406	if (gd->cpu_clk < 67000000) {
	407	sccr = immr->im_clkrst.car_sccr;
	408	sccr \|= SCCR_TBS;
	409	immr->im_clkrst.car_sccr = sccr;
	410	}
	411
	412	return (0);
	413	}
090eb735	414	#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
e9132ea9	415
4a9cbbe8	416	/* ------------------------------------------------------------------------- */