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5c952cf0 WD |
1 | /* |
2 | * (C) Copyright 2004, Psyent Corporation <www.psyent.com> | |
3 | * Scott McNutt <smcnutt@psyent.com> | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | ||
25 | #include <config.h> | |
26 | #include <version.h> | |
27 | ||
28 | /************************************************************************* | |
29 | * RESTART | |
30 | ************************************************************************/ | |
31 | ||
32 | .text | |
33 | .global _start | |
34 | ||
35 | _start: | |
36 | /* ICACHE INIT -- only the icache line at the reset address | |
37 | * is invalidated at reset. So the init must stay within | |
38 | * the cache line size (8 words). If GERMS is used, we'll | |
39 | * just be invalidating the cache a second time. If cache | |
40 | * is not implemented initi behaves as nop. | |
41 | */ | |
6d0f6bcf JCPV |
42 | ori r4, r0, %lo(CONFIG_SYS_ICACHELINE_SIZE) |
43 | movhi r5, %hi(CONFIG_SYS_ICACHE_SIZE) | |
44 | ori r5, r5, %lo(CONFIG_SYS_ICACHE_SIZE) | |
5c952cf0 WD |
45 | mov r6, r0 |
46 | 0: initi r6 | |
47 | add r6, r6, r4 | |
48 | bltu r6, r5, 0b | |
0c1c117c WD |
49 | br _except_end /* Skip the tramp */ |
50 | ||
51 | /* EXCEPTION TRAMPOLINE -- the following gets copied | |
52 | * to the exception address (below), but is otherwise at the | |
53 | * default exception vector offset (0x0020). | |
54 | */ | |
55 | _except_start: | |
56 | movhi et, %hi(_exception) | |
57 | ori et, et, %lo(_exception) | |
58 | jmp et | |
59 | _except_end: | |
5c952cf0 WD |
60 | |
61 | /* INTERRUPTS -- for now, all interrupts masked and globally | |
62 | * disabled. | |
63 | */ | |
64 | wrctl status, r0 /* Disable interrupts */ | |
65 | wrctl ienable, r0 /* All disabled */ | |
66 | ||
67 | /* DCACHE INIT -- if dcache not implemented, initd behaves as | |
68 | * nop. | |
69 | */ | |
6d0f6bcf JCPV |
70 | movhi r4, %hi(CONFIG_SYS_DCACHELINE_SIZE) |
71 | ori r4, r4, %lo(CONFIG_SYS_DCACHELINE_SIZE) | |
72 | movhi r5, %hi(CONFIG_SYS_DCACHE_SIZE) | |
73 | ori r5, r5, %lo(CONFIG_SYS_DCACHE_SIZE) | |
5c952cf0 WD |
74 | mov r6, r0 |
75 | 1: initd 0(r6) | |
76 | add r6, r6, r4 | |
77 | bltu r6, r5, 1b | |
78 | ||
79 | /* RELOCATE CODE, DATA & COMMAND TABLE -- the following code | |
80 | * assumes code, data and the command table are all | |
81 | * contiguous. This lets us relocate everything as a single | |
82 | * block. Make sure the linker script matches this ;-) | |
83 | */ | |
84 | nextpc r4 | |
85 | _cur: movhi r5, %hi(_cur - _start) | |
86 | ori r5, r5, %lo(_cur - _start) | |
87 | sub r4, r4, r5 /* r4 <- cur _start */ | |
88 | mov r8, r4 | |
89 | movhi r5, %hi(_start) | |
90 | ori r5, r5, %lo(_start) /* r5 <- linked _start */ | |
91 | beq r4, r5, 3f | |
92 | ||
93 | movhi r6, %hi(_edata) | |
94 | ori r6, r6, %lo(_edata) | |
95 | 2: ldwio r7, 0(r4) | |
96 | addi r4, r4, 4 | |
97 | stwio r7, 0(r5) | |
98 | addi r5, r5, 4 | |
99 | bne r5, r6, 2b | |
100 | 3: | |
101 | ||
102 | /* ZERO BSS/SBSS -- bss and sbss are assumed to be adjacent | |
103 | * and between __bss_start and _end. | |
104 | */ | |
105 | movhi r5, %hi(__bss_start) | |
106 | ori r5, r5, %lo(__bss_start) | |
107 | movhi r6, %hi(_end) | |
108 | ori r6, r6, %lo(_end) | |
109 | beq r5, r6, 5f | |
110 | ||
111 | 4: stwio r0, 0(r5) | |
112 | addi r5, r5, 4 | |
113 | bne r5, r6, 4b | |
114 | 5: | |
115 | ||
116 | /* GLOBAL POINTER -- the global pointer is used to reference | |
117 | * "small data" (see -G switch). The linker script must | |
118 | * provide the gp address. | |
119 | */ | |
120 | movhi gp, %hi(_gp) | |
121 | ori gp, gp, %lo(_gp) | |
122 | ||
123 | /* JUMP TO RELOC ADDR */ | |
124 | movhi r4, %hi(_reloc) | |
125 | ori r4, r4, %lo(_reloc) | |
126 | jmp r4 | |
127 | _reloc: | |
128 | ||
129 | /* COPY EXCEPTION TRAMPOLINE -- copy the tramp to the | |
0c1c117c WD |
130 | * exception address. Define CONFIG_ROM_STUBS to prevent |
131 | * the copy (e.g. exception in flash or in other | |
132 | * softare/firmware component). | |
5c952cf0 WD |
133 | */ |
134 | #if !defined(CONFIG_ROM_STUBS) | |
135 | movhi r4, %hi(_except_start) | |
136 | ori r4, r4, %lo(_except_start) | |
137 | movhi r5, %hi(_except_end) | |
138 | ori r5, r5, %lo(_except_end) | |
6d0f6bcf JCPV |
139 | movhi r6, %hi(CONFIG_SYS_EXCEPTION_ADDR) |
140 | ori r6, r6, %lo(CONFIG_SYS_EXCEPTION_ADDR) | |
0c1c117c | 141 | beq r4, r6, 7f /* Skip if at proper addr */ |
5c952cf0 WD |
142 | |
143 | 6: ldwio r7, 0(r4) | |
144 | stwio r7, 0(r6) | |
145 | addi r4, r4, 4 | |
146 | addi r6, r6, 4 | |
147 | bne r4, r5, 6b | |
0c1c117c | 148 | 7: |
5c952cf0 WD |
149 | #endif |
150 | ||
151 | /* STACK INIT -- zero top two words for call back chain. | |
152 | */ | |
6d0f6bcf JCPV |
153 | movhi sp, %hi(CONFIG_SYS_INIT_SP) |
154 | ori sp, sp, %lo(CONFIG_SYS_INIT_SP) | |
5c952cf0 WD |
155 | addi sp, sp, -8 |
156 | stw r0, 0(sp) | |
157 | stw r0, 4(sp) | |
158 | mov fp, sp | |
159 | ||
160 | /* | |
161 | * Call board_init -- never returns | |
162 | */ | |
163 | movhi r4, %hi(board_init@h) | |
164 | ori r4, r4, %lo(board_init@h) | |
165 | callr r4 | |
166 | ||
167 | /* NEVER RETURNS -- but branch to the _start just | |
168 | * in case ;-) | |
169 | */ | |
170 | br _start | |
171 | ||
5c952cf0 WD |
172 | |
173 | /* | |
174 | * dly_clks -- Nios2 (like Nios1) doesn't have a timebase in | |
175 | * the core. For simple delay loops, we do our best by counting | |
176 | * instruction cycles. | |
177 | * | |
178 | * Instruction performance varies based on the core. For cores | |
179 | * with icache and static/dynamic branch prediction (II/f, II/s): | |
180 | * | |
53677ef1 WD |
181 | * Normal ALU (e.g. add, cmp, etc): 1 cycle |
182 | * Branch (correctly predicted, taken): 2 cycles | |
5c952cf0 WD |
183 | * Negative offset is predicted (II/s). |
184 | * | |
185 | * For cores without icache and no branch prediction (II/e): | |
186 | * | |
53677ef1 WD |
187 | * Normal ALU (e.g. add, cmp, etc): 6 cycles |
188 | * Branch (no prediction): 6 cycles | |
5c952cf0 WD |
189 | * |
190 | * For simplicity, if an instruction cache is implemented we | |
191 | * assume II/f or II/s. Otherwise, we use the II/e. | |
192 | * | |
193 | */ | |
53677ef1 | 194 | .globl dly_clks |
5c952cf0 WD |
195 | |
196 | dly_clks: | |
197 | ||
6d0f6bcf | 198 | #if (CONFIG_SYS_ICACHE_SIZE > 0) |
5c952cf0 WD |
199 | subi r4, r4, 3 /* 3 clocks/loop */ |
200 | #else | |
201 | subi r4, r4, 12 /* 12 clocks/loop */ | |
202 | #endif | |
203 | bge r4, r0, dly_clks | |
204 | ret | |
205 | ||
206 | ||
207 | #if !defined(CONFIG_IDENT_STRING) | |
208 | #define CONFIG_IDENT_STRING "" | |
209 | #endif | |
210 | .data | |
211 | .globl version_string | |
212 | ||
213 | version_string: | |
214 | .ascii U_BOOT_VERSION | |
215 | .ascii " (", __DATE__, " - ", __TIME__, ")" | |
216 | .ascii CONFIG_IDENT_STRING, "\0" |