]> git.ipfire.org Git - people/ms/u-boot.git/blame - cpu/ppc4xx/405gp_enet.c
projects / people / ms / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* Fix flash parameters passed to Linux for PPChameleon board
[people/ms/u-boot.git] / cpu / ppc4xx / 405gp_enet.c
CommitLineData
c609719b
WD		 1/*-----------------------------------------------------------------------------+
2 *
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
9 *
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
13 *
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
17 *
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21/*-----------------------------------------------------------------------------+
22 *
23 * File Name: enetemac.c
24 *
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
26 *
27 * Author: Mark Wisner
28 *
29 * Change Activity-
30 *
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
48 * include/net.h
49 * - Receive buffer descriptor ring is used to send buffers
50 * to the user
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
66 * used anymore)
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
b4676a25
WD		 70 * 21-Nov-03 pavel.bartusek@sysgo.com
71 * - set ZMII bridge speed on 440
72 *
c609719b
WD		 73 *-----------------------------------------------------------------------------*/
74
75#include <common.h>
76#include <asm/processor.h>
77#include <ppc4xx.h>
78#include <commproc.h>
79#include <405gp_enet.h>
80#include <405_mal.h>
81#include <miiphy.h>
82#include <net.h>
83#include <malloc.h>
84#include "vecnum.h"
85
ba56f625
WD		 86#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
87 ( defined(CONFIG_440) && !defined(CONFIG_NET_MULTI))
c609719b 88
cea655a2
WD		 89#if !defined(CONFIG_NET_MULTI) || !defined(CONFIG_405EP)
90/* 405GP, 440 with !CONFIG_NET_MULTI. For 440 only EMAC0 is supported */
91#define EMAC_NUM_DEV 1
92#else
93/* 440EP && CONFIG_NET_MULTI */
94#define EMAC_NUM_DEV 2
95#endif
96
c609719b 97#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
149dded2 98#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
c609719b 99
c609719b
WD		 100/* Ethernet Transmit and Receive Buffers */
101/* AS.HARNOIS
102 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
103 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
104 */
105#define ENET_MAX_MTU PKTSIZE
106#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
107
c609719b 108/* define the number of channels implemented */
cea655a2
WD		 109#define EMAC_RXCHL EMAC_NUM_DEV
110#define EMAC_TXCHL EMAC_NUM_DEV
c609719b
WD		 111
112/*-----------------------------------------------------------------------------+
113 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
114 * Interrupt Controller).
115 *-----------------------------------------------------------------------------*/
116#define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
117#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
118#define EMAC_UIC_DEF UIC_ENET
cea655a2
WD		 119#define EMAC_UIC_DEF1 UIC_ENET1
120#define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
121
c609719b
WD		 122
123/*-----------------------------------------------------------------------------+
124 * Global variables. TX and RX descriptors and buffers.
125 *-----------------------------------------------------------------------------*/
c609719b 126/* IER globals */
cea655a2 127static uint32_t mal_ier;
c609719b 128
cea655a2
WD		 129#if !defined(CONFIG_NET_MULTI)
130struct eth_device *emac0_dev;
131#endif
c609719b 132
c609719b
WD		 133/*-----------------------------------------------------------------------------+
134 * Prototypes and externals.
135 *-----------------------------------------------------------------------------*/
cea655a2
WD		 136static void enet_rcv (struct eth_device *dev, unsigned long malisr);
137
138int enetInt (struct eth_device *dev);
139static void mal_err (struct eth_device *dev, unsigned long isr,
140 unsigned long uic, unsigned long maldef,
141 unsigned long mal_errr);
142static void emac_err (struct eth_device *dev, unsigned long isr);
c609719b 143
cea655a2
WD		 144/*-----------------------------------------------------------------------------+
145| ppc_405x_eth_halt
146| Disable MAL channel, and EMACn
147|
148|
149+-----------------------------------------------------------------------------*/
a3ed3996 150static void ppc_4xx_eth_halt (struct eth_device *dev)
c609719b 151{
cea655a2
WD		 152 EMAC_405_HW_PST hw_p = dev->priv;
153 uint32_t failsafe = 10000;
c609719b 154
cea655a2
WD		 155 mtdcr (malier, 0x00000000); /* disable mal interrupts */
156 out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
157
158 /* 1st reset MAL channel */
159 /* Note: writing a 0 to a channel has no effect */
160 mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
161 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
c609719b
WD		 162
163 /* wait for reset */
cea655a2
WD		 164 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
165 udelay (1000); /* Delay 1 MS so as not to hammer the register */
166 failsafe--;
167 if (failsafe == 0)
168 break;
169
170 }
c609719b
WD		 171
172 /* EMAC RESET */
cea655a2 173 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
c609719b 174
cea655a2 175 hw_p->print_speed = 1; /* print speed message again next time */
c609719b 176
cea655a2
WD		 177 return;
178}
c609719b 179
a3ed3996 180static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
c609719b
WD		 181{
182 int i;
183 unsigned long reg;
184 unsigned long msr;
185 unsigned long speed;
186 unsigned long duplex;
cea655a2 187 unsigned long failsafe;
c609719b 188 unsigned mode_reg;
cea655a2 189 unsigned short devnum;
c609719b
WD		 190 unsigned short reg_short;
191
cea655a2
WD		 192 EMAC_405_HW_PST hw_p = dev->priv;
193 /* before doing anything, figure out if we have a MAC address */
194 /* if not, bail */
195 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0)
196 return -1;
197
c609719b
WD		 198 msr = mfmsr ();
199 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
200
cea655a2
WD		 201 devnum = hw_p->devnum;
202
c609719b
WD		 203#ifdef INFO_405_ENET
204 /* AS.HARNOIS
205 * We should have :
cea655a2
WD		 206 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
207 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
8bde7f77
WD		 208 * is possible that new packets (without relationship with
209 * current transfer) have got the time to arrived before
210 * netloop calls eth_halt
c609719b 211 */
cea655a2 212 printf ("About preceeding transfer (eth%d):\n"
c609719b
WD		 213 "- Sent packet number %d\n"
214 "- Received packet number %d\n"
215 "- Handled packet number %d\n",
cea655a2
WD		 216 hw_p->devnum,
217 hw_p->stats.pkts_tx,
218 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
219
220 hw_p->stats.pkts_tx = 0;
221 hw_p->stats.pkts_rx = 0;
222 hw_p->stats.pkts_handled = 0;
c609719b
WD		 223#endif
224
225 /* MAL RESET */
cea655a2
WD		 226 mtdcr (malmcr, MAL_CR_MMSR);
227 /* wait for reset */
228 while (mfdcr (malmcr) & MAL_CR_MMSR) {
229 };
230#if defined(CONFIG_440)
231 /* set RMII mode */
232 out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
233#endif /* CONFIG_440 */
234
235 /* MAL Channel RESET */
236 /* 1st reset MAL channel */
237 /* Note: writing a 0 to a channel has no effect */
238 mtdcr (maltxcarr, (MAL_TXRX_CASR >> (hw_p->devnum * 2)));
239 mtdcr (malrxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
240
241 /* wait for reset */
242 /* TBS: should have udelay and failsafe here */
243 failsafe = 10000;
c609719b 244 /* wait for reset */
cea655a2
WD		 245 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
246 udelay (1000); /* Delay 1 MS so as not to hammer the register */
247 failsafe--;
248 if (failsafe == 0)
249 break;
c609719b 250
cea655a2 251 }
c609719b 252
cea655a2
WD		 253 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
254 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
c609719b 255
cea655a2
WD		 256 hw_p->rx_slot = 0; /* MAL Receive Slot */
257 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
258 hw_p->rx_u_index = 0; /* Receive User Queue Index */
c609719b 259
cea655a2
WD		 260 hw_p->tx_slot = 0; /* MAL Transmit Slot */
261 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
262 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
c609719b 263
cea655a2 264 __asm__ volatile ("eieio");
c609719b 265
cea655a2
WD		 266 /* reset emac so we have access to the phy */
267
268 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
269 __asm__ volatile ("eieio");
270
271 failsafe = 1000;
272 while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
273 udelay (1000);
274 failsafe--;
275 }
276
277#if defined(CONFIG_NET_MULTI)
278 reg = hw_p->devnum ? CONFIG_PHY1_ADDR : CONFIG_PHY_ADDR;
279#else
280 reg = CONFIG_PHY_ADDR;
281#endif
c609719b
WD		 282 /* wait for PHY to complete auto negotiation */
283 reg_short = 0;
284#ifndef CONFIG_CS8952_PHY
cea655a2 285 miiphy_read (reg, PHY_BMSR, &reg_short);
c609719b
WD		 286
287 /*
cea655a2 288 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
c609719b
WD		 289 */
290 if ((reg_short & PHY_BMSR_AUTN_ABLE)
291 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
292 puts ("Waiting for PHY auto negotiation to complete");
293 i = 0;
294 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
c609719b
WD		 295 /*
296 * Timeout reached ?
297 */
149dded2 298 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
c609719b
WD		 299 puts (" TIMEOUT !\n");
300 break;
301 }
149dded2 302
cea655a2 303 if ((i++ % 1000) == 0) {
149dded2 304 putc ('.');
cea655a2 305 }
149dded2 306 udelay (1000); /* 1 ms */
cea655a2 307 miiphy_read (reg, PHY_BMSR, &reg_short);
c609719b
WD		 308 }
309 puts (" done\n");
310 udelay (500000); /* another 500 ms (results in faster booting) */
311 }
312#endif
cea655a2
WD		 313 speed = miiphy_speed (reg);
314 duplex = miiphy_duplex (reg);
315
316 if (hw_p->print_speed) {
317 hw_p->print_speed = 0;
c609719b
WD		 318 printf ("ENET Speed is %d Mbps - %s duplex connection\n",
319 (int) speed, (duplex == HALF) ? "HALF" : "FULL");
320 }
321
c609719b
WD		 322#if defined(CONFIG_440)
323 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
cea655a2
WD		 324 if( get_pvr() == PVR_440GP_RB)
325 mtdcr (malmcr, MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
c609719b
WD		 326 else
327#else
328 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
329#endif
330
331 /* Free "old" buffers */
cea655a2
WD		 332 if (hw_p->alloc_tx_buf)
333 free (hw_p->alloc_tx_buf);
334 if (hw_p->alloc_rx_buf)
335 free (hw_p->alloc_rx_buf);
c609719b
WD		 336
337 /*
338 * Malloc MAL buffer desciptors, make sure they are
339 * aligned on cache line boundary size
340 * (401/403/IOP480 = 16, 405 = 32)
341 * and doesn't cross cache block boundaries.
342 */
cea655a2
WD		 343 hw_p->alloc_tx_buf =
344 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
345 ((2 * CFG_CACHELINE_SIZE) - 2));
346 if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
347 hw_p->tx =
348 (mal_desc_t *) ((int) hw_p->alloc_tx_buf +
349 CFG_CACHELINE_SIZE -
350 ((int) hw_p->
351 alloc_tx_buf & CACHELINE_MASK));
c609719b 352 } else {
cea655a2 353 hw_p->tx = hw_p->alloc_tx_buf;
c609719b
WD		 354 }
355
cea655a2
WD		 356 hw_p->alloc_rx_buf =
357 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
358 ((2 * CFG_CACHELINE_SIZE) - 2));
359 if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
360 hw_p->rx =
361 (mal_desc_t *) ((int) hw_p->alloc_rx_buf +
362 CFG_CACHELINE_SIZE -
363 ((int) hw_p->
364 alloc_rx_buf & CACHELINE_MASK));
c609719b 365 } else {
cea655a2 366 hw_p->rx = hw_p->alloc_rx_buf;
c609719b
WD		 367 }
368
369 for (i = 0; i < NUM_TX_BUFF; i++) {
cea655a2
WD		 370 hw_p->tx[i].ctrl = 0;
371 hw_p->tx[i].data_len = 0;
372 if (hw_p->first_init == 0)
373 hw_p->txbuf_ptr =
374 (char *) malloc (ENET_MAX_MTU_ALIGNED);
375 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
c609719b 376 if ((NUM_TX_BUFF - 1) == i)
cea655a2
WD		 377 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
378 hw_p->tx_run[i] = -1;
c609719b 379#if 0
cea655a2
WD		 380 printf ("TX_BUFF %d @ 0x%08lx\n", i,
381 (ulong) hw_p->tx[i].data_ptr);
c609719b
WD		 382#endif
383 }
384
385 for (i = 0; i < NUM_RX_BUFF; i++) {
cea655a2
WD		 386 hw_p->rx[i].ctrl = 0;
387 hw_p->rx[i].data_len = 0;
c609719b 388 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
cea655a2 389 hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
c609719b 390 if ((NUM_RX_BUFF - 1) == i)
cea655a2
WD		 391 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
392 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
393 hw_p->rx_ready[i] = -1;
c609719b
WD		 394#if 0
395 printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
396#endif
397 }
398
c609719b 399 reg = 0x00000000;
cea655a2 400 reg |= dev->enetaddr[0]; /* set high address */
c609719b 401 reg = reg << 8;
cea655a2 402 reg |= dev->enetaddr[1];
c609719b 403
cea655a2 404 out32 (EMAC_IAH + hw_p->hw_addr, reg);
c609719b
WD		 405
406 reg = 0x00000000;
cea655a2 407 reg |= dev->enetaddr[2]; /* set low address */
c609719b 408 reg = reg << 8;
cea655a2 409 reg |= dev->enetaddr[3];
c609719b 410 reg = reg << 8;
cea655a2 411 reg |= dev->enetaddr[4];
c609719b 412 reg = reg << 8;
cea655a2
WD		 413 reg |= dev->enetaddr[5];
414
415 out32 (EMAC_IAL + hw_p->hw_addr, reg);
416 switch (devnum) {
46a414dc 417#if defined(CONFIG_NET_MULTI)
cea655a2
WD		 418 case 1:
419 /* setup MAL tx & rx channel pointers */
420 /* For 405EP, the EMAC1 tx channel 0 is MAL tx channel 2 */
421 mtdcr (maltxctp2r, hw_p->tx);
422 mtdcr (malrxctp1r, hw_p->rx);
423 /* set RX buffer size */
424 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
425 break;
46a414dc 426#endif
cea655a2
WD		 427 case 0:
428 default:
429 /* setup MAL tx & rx channel pointers */
430 mtdcr (maltxctp0r, hw_p->tx);
431 mtdcr (malrxctp0r, hw_p->rx);
432 /* set RX buffer size */
433 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
434 break;
435 }
c609719b
WD		 436
437 /* Enable MAL transmit and receive channels */
cea655a2
WD		 438 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum * 2)));
439 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
c609719b
WD		 440
441 /* set transmit enable & receive enable */
cea655a2 442 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
c609719b
WD		 443
444 /* set receive fifo to 4k and tx fifo to 2k */
cea655a2
WD		 445 mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
446 mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
c609719b
WD		 447
448 /* set speed */
449 if (speed == _100BASET)
450 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
451 else
452 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
453 if (duplex == FULL)
454 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
455
cea655a2 456 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
c609719b 457
b4676a25
WD		 458#if defined(CONFIG_440)
459 /* set speed in the ZMII bridge */
460 if (speed == _100BASET)
461 out32(ZMII_SSR, in32(ZMII_SSR) | 0x10000000);
462 else
463 out32(ZMII_SSR, in32(ZMII_SSR) & ~0x10000000);
464#endif
465
c609719b 466 /* Enable broadcast and indvidual address */
cea655a2
WD		 467 /* TBS: enabling runts as some misbehaved nics will send runts */
468 out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
c609719b
WD		 469
470 /* we probably need to set the tx mode1 reg? maybe at tx time */
471
472 /* set transmit request threshold register */
cea655a2 473 out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
c609719b 474
c609719b
WD		 475#if defined(CONFIG_440)
476 /* 440GP has a 64 byte burst length */
cea655a2
WD		 477 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
478 out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
479#else
c609719b 480 /* 405s have a 16 byte burst length */
cea655a2
WD		 481 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
482#endif
483
c609719b
WD		 484
485 /* Frame gap set */
cea655a2
WD		 486 out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
487
488 /* Set EMAC IER */
489 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
490 EMAC_ISR_ORE | EMAC_ISR_IRE;
491 if (speed == _100BASET)
492 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
493
494 out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
495 out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
c609719b 496
cea655a2 497 if (hw_p->first_init == 0) {
c609719b
WD		 498 /*
499 * Connect interrupt service routines
500 */
cea655a2
WD		 501#if !defined(CONFIG_405EP)
502 /* 405EP has one EWU interrupt */
503 irq_install_handler (VECNUM_EWU0 + (hw_p->devnum * 2),
504 (interrupt_handler_t *) enetInt, dev);
505#endif
506 irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
507 (interrupt_handler_t *) enetInt, dev);
c609719b
WD		 508 }
509
cea655a2 510 mtmsr (msr); /* enable interrupts again */
c609719b 511
cea655a2
WD		 512 hw_p->bis = bis;
513 hw_p->first_init = 1;
c609719b 514
a3ed3996 515 return (1);
c609719b
WD		 516}
517
518
a3ed3996 519static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, int len)
c609719b
WD		 520{
521 struct enet_frame *ef_ptr;
522 ulong time_start, time_now;
523 unsigned long temp_txm0;
cea655a2 524 EMAC_405_HW_PST hw_p = dev->priv;
c609719b
WD		 525
526 ef_ptr = (struct enet_frame *) ptr;
527
528 /*-----------------------------------------------------------------------+
529 * Copy in our address into the frame.
530 *-----------------------------------------------------------------------*/
cea655a2 531 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
c609719b
WD		 532
533 /*-----------------------------------------------------------------------+
534 * If frame is too long or too short, modify length.
535 *-----------------------------------------------------------------------*/
cea655a2 536 /* TBS: where does the fragment go???? */
c609719b
WD		 537 if (len > ENET_MAX_MTU)
538 len = ENET_MAX_MTU;
539
540 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
cea655a2 541 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
c609719b
WD		 542
543 /*-----------------------------------------------------------------------+
544 * set TX Buffer busy, and send it
545 *-----------------------------------------------------------------------*/
cea655a2
WD		 546 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
547 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
c609719b 548 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
cea655a2
WD		 549 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
550 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
551
552 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
553 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
c609719b 554
cea655a2 555 __asm__ volatile ("eieio");
c609719b 556
cea655a2
WD		 557 out32 (EMAC_TXM0 + hw_p->hw_addr,
558 in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
c609719b 559#ifdef INFO_405_ENET
cea655a2 560 hw_p->stats.pkts_tx++;
c609719b
WD		 561#endif
562
563 /*-----------------------------------------------------------------------+
564 * poll unitl the packet is sent and then make sure it is OK
565 *-----------------------------------------------------------------------*/
566 time_start = get_timer (0);
567 while (1) {
cea655a2 568 temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
c609719b
WD		 569 /* loop until either TINT turns on or 3 seconds elapse */
570 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
571 /* transmit is done, so now check for errors
8bde7f77
WD		 572 * If there is an error, an interrupt should
573 * happen when we return
c609719b
WD		 574 */
575 time_now = get_timer (0);
576 if ((time_now - time_start) > 3000) {
577 return (-1);
578 }
579 } else {
a3ed3996 580 return (len);
c609719b
WD		 581 }
582 }
583}
584
c609719b 585#if defined(CONFIG_440)
cea655a2 586int enetInt (struct eth_device *dev)
c609719b
WD		 587{
588 int serviced;
589 int rc = -1; /* default to not us */
590 unsigned long mal_isr;
591 unsigned long emac_isr = 0;
592 unsigned long mal_rx_eob;
593 unsigned long my_uic0msr, my_uic1msr;
cea655a2
WD		 594 EMAC_405_HW_PST hw_p;
595
596 /*
597 * Because the mal is generic, we need to get the current
598 * eth device
599 */
600#if defined(CONFIG_NET_MULTI)
601 dev = eth_get_dev();
602#else
603 dev = emac0_dev;
604#endif
605 hw_p = dev->priv;
c609719b
WD		 606
607 /* enter loop that stays in interrupt code until nothing to service */
608 do {
609 serviced = 0;
610
611 my_uic0msr = mfdcr (uic0msr);
612 my_uic1msr = mfdcr (uic1msr);
613
614 if (!(my_uic0msr & UIC_MRE)
8bde7f77
WD		 615 && !(my_uic1msr & (UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
616 /* not for us */
c609719b
WD		 617 return (rc);
618 }
619
620 /* get and clear controller status interrupts */
621 /* look at Mal and EMAC interrupts */
622 if ((my_uic0msr & UIC_MRE)
8bde7f77
WD		 623 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
624 /* we have a MAL interrupt */
c609719b
WD		 625 mal_isr = mfdcr (malesr);
626 /* look for mal error */
627 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
cea655a2 628 mal_err (dev, mal_isr, my_uic0msr, MAL_UIC_DEF, MAL_UIC_ERR);
c609719b
WD		 629 serviced = 1;
630 rc = 0;
631 }
632 }
633 if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
cea655a2
WD		 634 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
635 if ((hw_p->emac_ier & emac_isr) != 0) {
636 emac_err (dev, emac_isr);
c609719b
WD		 637 serviced = 1;
638 rc = 0;
639 }
640 }
cea655a2 641 if ((hw_p->emac_ier & emac_isr)
8bde7f77 642 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
c609719b
WD		 643 mtdcr (uic0sr, UIC_MRE); /* Clear */
644 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
645 return (rc); /* we had errors so get out */
646 }
647
648 /* handle MAL RX EOB interupt from a receive */
649 /* check for EOB on valid channels */
650 if (my_uic0msr & UIC_MRE) {
651 mal_rx_eob = mfdcr (malrxeobisr);
cea655a2 652 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel 0 */
c609719b
WD		 653 /* clear EOB
654 mtdcr(malrxeobisr, mal_rx_eob); */
cea655a2 655 enet_rcv (dev, emac_isr);
c609719b
WD		 656 /* indicate that we serviced an interrupt */
657 serviced = 1;
658 rc = 0;
659 }
660 }
8bde7f77
WD		 661 mtdcr (uic0sr, UIC_MRE); /* Clear */
662 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
c609719b
WD		 663 } while (serviced);
664
665 return (rc);
666}
cea655a2 667
c609719b 668#else /* CONFIG_440 */
cea655a2
WD		 669
670int enetInt (struct eth_device *dev)
c609719b
WD		 671{
672 int serviced;
cea655a2 673 int rc = -1; /* default to not us */
c609719b
WD		 674 unsigned long mal_isr;
675 unsigned long emac_isr = 0;
676 unsigned long mal_rx_eob;
677 unsigned long my_uicmsr;
678
cea655a2
WD		 679 EMAC_405_HW_PST hw_p;
680
681 /*
682 * Because the mal is generic, we need to get the current
683 * eth device
684 */
685#if defined(CONFIG_NET_MULTI)
686 dev = eth_get_dev();
687#else
688 dev = emac0_dev;
689#endif
690
691 hw_p = dev->priv;
692
c609719b
WD		 693 /* enter loop that stays in interrupt code until nothing to service */
694 do {
695 serviced = 0;
696
697 my_uicmsr = mfdcr (uicmsr);
cea655a2 698
c609719b
WD		 699 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
700 return (rc);
701 }
c609719b
WD		 702 /* get and clear controller status interrupts */
703 /* look at Mal and EMAC interrupts */
704 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
705 mal_isr = mfdcr (malesr);
706 /* look for mal error */
707 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
cea655a2 708 mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
c609719b
WD		 709 serviced = 1;
710 rc = 0;
711 }
712 }
cea655a2
WD		 713
714 /* port by port dispatch of emac interrupts */
715
716 if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
717 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
718 if ((hw_p->emac_ier & emac_isr) != 0) {
719 emac_err (dev, emac_isr);
c609719b
WD		 720 serviced = 1;
721 rc = 0;
722 }
723 }
cea655a2
WD		 724 if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
725 mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
c609719b
WD		 726 return (rc); /* we had errors so get out */
727 }
728
cea655a2
WD		 729 /* handle MAX TX EOB interrupt from a tx */
730 if (my_uicmsr & UIC_MAL_TXEOB) {
731 mal_rx_eob = mfdcr (maltxeobisr);
732 mtdcr (maltxeobisr, mal_rx_eob);
733 mtdcr (uicsr, UIC_MAL_TXEOB);
734 }
c609719b 735 /* handle MAL RX EOB interupt from a receive */
cea655a2
WD		 736 /* check for EOB on valid channels */
737 if (my_uicmsr & UIC_MAL_RXEOB)
738 {
c609719b 739 mal_rx_eob = mfdcr (malrxeobisr);
cea655a2 740 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
c609719b 741 /* clear EOB
cea655a2
WD		 742 mtdcr(malrxeobisr, mal_rx_eob); */
743 enet_rcv (dev, emac_isr);
c609719b
WD		 744 /* indicate that we serviced an interrupt */
745 serviced = 1;
746 rc = 0;
747 }
748 }
cea655a2 749 mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
c609719b
WD		 750 }
751 while (serviced);
752
753 return (rc);
754}
cea655a2 755#endif
c609719b
WD		 756/*-----------------------------------------------------------------------------+
757 * MAL Error Routine
758 *-----------------------------------------------------------------------------*/
cea655a2
WD		 759static void mal_err (struct eth_device *dev, unsigned long isr,
760 unsigned long uic, unsigned long maldef,
761 unsigned long mal_errr)
c609719b 762{
cea655a2
WD		 763 EMAC_405_HW_PST hw_p = dev->priv;
764
765 mtdcr (malesr, isr); /* clear interrupt */
c609719b
WD		 766
767 /* clear DE interrupt */
768 mtdcr (maltxdeir, 0xC0000000);
769 mtdcr (malrxdeir, 0x80000000);
770
b867d705 771#ifdef INFO_405_ENET
cea655a2 772 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
b867d705 773#endif
c609719b 774
cea655a2 775 eth_init (hw_p->bis); /* start again... */
c609719b
WD		 776}
777
778/*-----------------------------------------------------------------------------+
779 * EMAC Error Routine
780 *-----------------------------------------------------------------------------*/
cea655a2 781static void emac_err (struct eth_device *dev, unsigned long isr)
c609719b 782{
cea655a2
WD		 783 EMAC_405_HW_PST hw_p = dev->priv;
784
785 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
786 out32 (EMAC_ISR + hw_p->hw_addr, isr);
c609719b
WD		 787}
788
789/*-----------------------------------------------------------------------------+
790 * enet_rcv() handles the ethernet receive data
791 *-----------------------------------------------------------------------------*/
cea655a2 792static void enet_rcv (struct eth_device *dev, unsigned long malisr)
c609719b
WD		 793{
794 struct enet_frame *ef_ptr;
795 unsigned long data_len;
796 unsigned long rx_eob_isr;
cea655a2 797 EMAC_405_HW_PST hw_p = dev->priv;
c609719b
WD		 798
799 int handled = 0;
800 int i;
801 int loop_count = 0;
802
803 rx_eob_isr = mfdcr (malrxeobisr);
cea655a2 804 if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
c609719b
WD		 805 /* clear EOB */
806 mtdcr (malrxeobisr, rx_eob_isr);
807
808 /* EMAC RX done */
cea655a2
WD		 809 while (1) { /* do all */
810 i = hw_p->rx_slot;
c609719b 811
cea655a2 812 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
c609719b
WD		 813 || (loop_count >= NUM_RX_BUFF))
814 break;
815 loop_count++;
cea655a2
WD		 816 hw_p->rx_slot++;
817 if (NUM_RX_BUFF == hw_p->rx_slot)
818 hw_p->rx_slot = 0;
c609719b 819 handled++;
cea655a2 820 data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
c609719b
WD		 821 if (data_len) {
822 if (data_len > ENET_MAX_MTU) /* Check len */
823 data_len = 0;
824 else {
cea655a2 825 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
c609719b 826 data_len = 0;
cea655a2
WD		 827 hw_p->stats.rx_err_log[hw_p->
828 rx_err_index]
829 = hw_p->rx[i].ctrl;
830 hw_p->rx_err_index++;
831 if (hw_p->rx_err_index ==
832 MAX_ERR_LOG)
833 hw_p->rx_err_index =
834 0;
835 } /* emac_erros */
836 } /* data_len < max mtu */
837 } /* if data_len */
c609719b 838 if (!data_len) { /* no data */
cea655a2 839 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
c609719b 840
cea655a2 841 hw_p->stats.data_len_err++; /* Error at Rx */
c609719b
WD		 842 }
843
844 /* !data_len */
845 /* AS.HARNOIS */
846 /* Check if user has already eaten buffer */
847 /* if not => ERROR */
cea655a2
WD		 848 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
849 if (hw_p->is_receiving)
c609719b
WD		 850 printf ("ERROR : Receive buffers are full!\n");
851 break;
852 } else {
cea655a2
WD		 853 hw_p->stats.rx_frames++;
854 hw_p->stats.rx += data_len;
855 ef_ptr = (struct enet_frame *) hw_p->rx[i].
856 data_ptr;
c609719b 857#ifdef INFO_405_ENET
cea655a2 858 hw_p->stats.pkts_rx++;
c609719b
WD		 859#endif
860 /* AS.HARNOIS
861 * use ring buffer
862 */
cea655a2
WD		 863 hw_p->rx_ready[hw_p->rx_i_index] = i;
864 hw_p->rx_i_index++;
865 if (NUM_RX_BUFF == hw_p->rx_i_index)
866 hw_p->rx_i_index = 0;
c609719b
WD		 867
868 /* printf("X"); /|* test-only *|/ */
869
870 /* AS.HARNOIS
871 * free receive buffer only when
872 * buffer has been handled (eth_rx)
873 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
cea655a2
WD		 874 */
875 } /* if data_len */
876 } /* while */
877 } /* if EMACK_RXCHL */
c609719b
WD		 878}
879
880
a3ed3996 881static int ppc_4xx_eth_rx (struct eth_device *dev)
c609719b
WD		 882{
883 int length;
884 int user_index;
885 unsigned long msr;
cea655a2 886 EMAC_405_HW_PST hw_p = dev->priv;
c609719b 887
cea655a2 888 hw_p->is_receiving = 1; /* tell driver */
c609719b
WD		 889
890 for (;;) {
891 /* AS.HARNOIS
892 * use ring buffer and
893 * get index from rx buffer desciptor queue
894 */
cea655a2 895 user_index = hw_p->rx_ready[hw_p->rx_u_index];
c609719b
WD		 896 if (user_index == -1) {
897 length = -1;
898 break; /* nothing received - leave for() loop */
899 }
900
901 msr = mfmsr ();
902 mtmsr (msr & ~(MSR_EE));
903
cea655a2 904 length = hw_p->rx[user_index].data_len;
c609719b
WD		 905
906 /* Pass the packet up to the protocol layers. */
907 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
908 /* NetReceive(NetRxPackets[i], length); */
909 NetReceive (NetRxPackets[user_index], length - 4);
910 /* Free Recv Buffer */
cea655a2 911 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
c609719b 912 /* Free rx buffer descriptor queue */
cea655a2
WD		 913 hw_p->rx_ready[hw_p->rx_u_index] = -1;
914 hw_p->rx_u_index++;
915 if (NUM_RX_BUFF == hw_p->rx_u_index)
916 hw_p->rx_u_index = 0;
c609719b
WD		 917
918#ifdef INFO_405_ENET
cea655a2 919 hw_p->stats.pkts_handled++;
c609719b
WD		 920#endif
921
cea655a2 922 mtmsr (msr); /* Enable IRQ's */
c609719b
WD		 923 }
924
cea655a2 925 hw_p->is_receiving = 0; /* tell driver */
c609719b
WD		 926
927 return length;
928}
929
cea655a2
WD		 930static int virgin = 0;
931int ppc_4xx_eth_initialize (bd_t * bis)
a3ed3996 932{
8bde7f77 933 struct eth_device *dev;
cea655a2 934 int eth_num = 0;
8bde7f77 935
cea655a2 936 EMAC_405_HW_PST hw = NULL;
8bde7f77 937
cea655a2
WD		 938 for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
939
940 /* Allocate device structure */
941 dev = (struct eth_device *) malloc (sizeof (*dev));
942 if (dev == NULL) {
943 printf ("ppc_405x_eth_initialize: "
944 "Cannot allocate eth_device %d\n", eth_num);
945 return (-1);
946 }
947 /* Allocate our private use data */
948 hw = (EMAC_405_HW_PST) malloc (sizeof (*hw));
949 if (hw == NULL) {
950 printf ("ppc_405x_eth_initialize: "
951 "Cannot allocate private hw data for eth_device %d",
952 eth_num);
953 free (dev);
954 return (-1);
955 }
8bde7f77 956
cea655a2
WD		 957 switch (eth_num) {
958 case 0:
959 hw->hw_addr = 0;
960 memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
961 break;
962#if defined(CONFIG_NET_MULTI)
963 case 1:
964 hw->hw_addr = 0x100;
965 memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
966 break;
967#endif
968 default:
969 hw->hw_addr = 0;
970 memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
971 break;
972 }
973
974 hw->devnum = eth_num;
975 hw->print_speed = 1;
976
977 sprintf (dev->name, "ppc_405x_eth%d", eth_num);
978 dev->priv = (void *) hw;
979 dev->init = ppc_4xx_eth_init;
980 dev->halt = ppc_4xx_eth_halt;
981 dev->send = ppc_4xx_eth_send;
982 dev->recv = ppc_4xx_eth_rx;
983
984 if (0 == virgin) {
985 /* set the MAL IER ??? names may change with new spec ??? */
986 mal_ier =
987 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
988 MAL_IER_OPBE | MAL_IER_PLBE;
989 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
990 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
991 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
992 mtdcr (malier, mal_ier);
993
994#if defined(CONFIG_405EP)
995 /* 405EP has one EWU interrupt */
996 irq_install_handler (VECNUM_EWU0,
997 (interrupt_handler_t *) enetInt,
998 dev);
999#endif
1000 /* install MAL interrupt handler */
1001 irq_install_handler (VECNUM_MS,
1002 (interrupt_handler_t *) enetInt,
1003 dev);
1004 irq_install_handler (VECNUM_MTE,
1005 (interrupt_handler_t *) enetInt,
1006 dev);
1007 irq_install_handler (VECNUM_MRE,
1008 (interrupt_handler_t *) enetInt,
1009 dev);
1010 irq_install_handler (VECNUM_TXDE,
1011 (interrupt_handler_t *) enetInt,
1012 dev);
1013 irq_install_handler (VECNUM_RXDE,
1014 (interrupt_handler_t *) enetInt,
1015 dev);
1016 virgin = 1;
1017 }
1018
1019#if defined(CONFIG_NET_MULTI)
1020 eth_register (dev);
1021#else
1022 emac0_dev = dev;
1023#endif
1024
1025 } /* end for each supported device */
1026
1027 return (1);
a3ed3996 1028}
cea655a2
WD		 1029
1030#if !defined(CONFIG_NET_MULTI)
1031void eth_halt (void) {
1032 if (emac0_dev) {
1033 ppc_4xx_eth_halt(emac0_dev);
1034 free(emac0_dev);
1035 emac0_dev = NULL;
1036 }
a3ed3996
WD		 1037}
1038
1039int eth_init (bd_t *bis)
1040{
cea655a2
WD		 1041 ppc_4xx_eth_initialize(bis);
1042 return(ppc_4xx_eth_init(emac0_dev, bis));
a3ed3996 1043}
cea655a2 1044
a3ed3996
WD		 1045int eth_send(volatile void *packet, int length)
1046{
cea655a2
WD		 1047
1048 return (ppc_4xx_eth_send(emac0_dev, packet, length));
a3ed3996
WD		 1049}
1050
1051int eth_rx(void)
1052{
cea655a2 1053 return (ppc_4xx_eth_rx(emac0_dev));
a3ed3996 1054}
cea655a2 1055#endif
a3ed3996 1056
cea655a2 1057#endif /* CONFIG_405 */
"Das U-Boot" Source Tree