]>
Commit | Line | Data |
---|---|---|
ba56f625 WD |
1 | /*-----------------------------------------------------------------------------+ |
2 | * | |
265817c7 WD |
3 | * This source code has been made available to you by IBM on an AS-IS |
4 | * basis. Anyone receiving this source is licensed under IBM | |
5 | * copyrights to use it in any way he or she deems fit, including | |
6 | * copying it, modifying it, compiling it, and redistributing it either | |
7 | * with or without modifications. No license under IBM patents or | |
8 | * patent applications is to be implied by the copyright license. | |
ba56f625 | 9 | * |
265817c7 WD |
10 | * Any user of this software should understand that IBM cannot provide |
11 | * technical support for this software and will not be responsible for | |
12 | * any consequences resulting from the use of this software. | |
ba56f625 | 13 | * |
265817c7 WD |
14 | * Any person who transfers this source code or any derivative work |
15 | * must include the IBM copyright notice, this paragraph, and the | |
16 | * preceding two paragraphs in the transferred software. | |
ba56f625 | 17 | * |
265817c7 WD |
18 | * COPYRIGHT I B M CORPORATION 1995 |
19 | * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
ba56f625 WD |
20 | *-----------------------------------------------------------------------------*/ |
21 | /*-----------------------------------------------------------------------------+ | |
22 | * | |
265817c7 | 23 | * File Name: enetemac.c |
ba56f625 | 24 | * |
265817c7 | 25 | * Function: Device driver for the ethernet EMAC3 macro on the 405GP. |
ba56f625 | 26 | * |
265817c7 | 27 | * Author: Mark Wisner |
ba56f625 WD |
28 | * |
29 | * Change Activity- | |
30 | * | |
265817c7 WD |
31 | * Date Description of Change BY |
32 | * --------- --------------------- --- | |
33 | * 05-May-99 Created MKW | |
34 | * 27-Jun-99 Clean up JWB | |
35 | * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW | |
36 | * 29-Jul-99 Added Full duplex support MKW | |
37 | * 06-Aug-99 Changed names for Mal CR reg MKW | |
38 | * 23-Aug-99 Turned off SYE when running at 10Mbs MKW | |
39 | * 24-Aug-99 Marked descriptor empty after call_xlc MKW | |
40 | * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG | |
41 | * to avoid chaining maximum sized packets. Push starting | |
42 | * RX descriptor address up to the next cache line boundary. | |
43 | * 16-Jan-00 Added support for booting with IP of 0x0 MKW | |
44 | * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the | |
45 | * EMAC_RXM register. JWB | |
46 | * 12-Mar-01 anne-sophie.harnois@nextream.fr | |
47 | * - Variables are compatible with those already defined in | |
48 | * include/net.h | |
49 | * - Receive buffer descriptor ring is used to send buffers | |
50 | * to the user | |
51 | * - Info print about send/received/handled packet number if | |
52 | * INFO_405_ENET is set | |
53 | * 17-Apr-01 stefan.roese@esd-electronics.com | |
54 | * - MAL reset in "eth_halt" included | |
55 | * - Enet speed and duplex output now in one line | |
56 | * 08-May-01 stefan.roese@esd-electronics.com | |
57 | * - MAL error handling added (eth_init called again) | |
58 | * 13-Nov-01 stefan.roese@esd-electronics.com | |
59 | * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex | |
60 | * 04-Jan-02 stefan.roese@esd-electronics.com | |
61 | * - Wait for PHY auto negotiation to complete added | |
62 | * 06-Feb-02 stefan.roese@esd-electronics.com | |
63 | * - Bug fixed in waiting for auto negotiation to complete | |
64 | * 26-Feb-02 stefan.roese@esd-electronics.com | |
65 | * - rx and tx buffer descriptors now allocated (no fixed address | |
66 | * used anymore) | |
67 | * 17-Jun-02 stefan.roese@esd-electronics.com | |
68 | * - MAL error debug printf 'M' removed (rx de interrupt may | |
69 | * occur upon many incoming packets with only 4 rx buffers). | |
ba56f625 | 70 | *-----------------------------------------------------------------------------* |
265817c7 WD |
71 | * 17-Nov-03 travis.sawyer@sandburst.com |
72 | * - ported from 405gp_enet.c to utilized upto 4 EMAC ports | |
73 | * in the 440GX. This port should work with the 440GP | |
74 | * (2 EMACs) also | |
75 | * 15-Aug-05 sr@denx.de | |
76 | * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c | |
77 | now handling all 4xx cpu's. | |
ba56f625 WD |
78 | *-----------------------------------------------------------------------------*/ |
79 | ||
80 | #include <config.h> | |
ba56f625 WD |
81 | #include <common.h> |
82 | #include <net.h> | |
83 | #include <asm/processor.h> | |
2d83476a | 84 | #include <asm/io.h> |
ff768cb1 SR |
85 | #include <asm/cache.h> |
86 | #include <asm/mmu.h> | |
ba56f625 | 87 | #include <commproc.h> |
d6c61aab SR |
88 | #include <ppc4xx.h> |
89 | #include <ppc4xx_enet.h> | |
ba56f625 WD |
90 | #include <405_mal.h> |
91 | #include <miiphy.h> | |
92 | #include <malloc.h> | |
ba56f625 | 93 | |
d6c61aab | 94 | /* |
0c8721a4 | 95 | * Only compile for platform with AMCC EMAC ethernet controller and |
d6c61aab SR |
96 | * network support enabled. |
97 | * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller! | |
98 | */ | |
3a1ed1e1 | 99 | #if defined(CONFIG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480) |
d6c61aab | 100 | |
3a1ed1e1 | 101 | #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) |
d6c61aab SR |
102 | #error "CONFIG_MII has to be defined!" |
103 | #endif | |
ba56f625 | 104 | |
1e25f957 SR |
105 | #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI) |
106 | #error "CONFIG_NET_MULTI has to be defined for NetConsole" | |
107 | #endif | |
108 | ||
265817c7 | 109 | #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */ |
1338e6a8 | 110 | #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */ |
ba56f625 | 111 | |
ba56f625 WD |
112 | /* Ethernet Transmit and Receive Buffers */ |
113 | /* AS.HARNOIS | |
114 | * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from | |
115 | * PKTSIZE and PKTSIZE_ALIGN (include/net.h) | |
116 | */ | |
265817c7 | 117 | #define ENET_MAX_MTU PKTSIZE |
ba56f625 WD |
118 | #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN |
119 | ||
ba56f625 WD |
120 | /*-----------------------------------------------------------------------------+ |
121 | * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal | |
122 | * Interrupt Controller). | |
123 | *-----------------------------------------------------------------------------*/ | |
d1631fe1 SR |
124 | #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS)) |
125 | ||
126 | #if defined(CONFIG_HAS_ETH3) | |
127 | #if !defined(CONFIG_440GX) | |
128 | #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \ | |
129 | UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3))) | |
130 | #else | |
131 | /* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */ | |
132 | #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1))) | |
133 | #define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3))) | |
134 | #endif /* !defined(CONFIG_440GX) */ | |
135 | #elif defined(CONFIG_HAS_ETH2) | |
136 | #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \ | |
137 | UIC_MASK(ETH_IRQ_NUM(2))) | |
138 | #elif defined(CONFIG_HAS_ETH1) | |
139 | #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1))) | |
140 | #else | |
141 | #define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0)) | |
142 | #endif | |
143 | ||
144 | /* | |
145 | * Define a default version for UIC_ETHxB for non 440GX so that we can | |
146 | * use common code for all 4xx variants | |
147 | */ | |
148 | #if !defined(UIC_ETHxB) | |
149 | #define UIC_ETHxB 0 | |
150 | #endif | |
151 | ||
152 | #define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR) | |
153 | #define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE) | |
154 | #define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE) | |
155 | #define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB) | |
156 | #define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB) | |
157 | ||
158 | #define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE) | |
159 | #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR) | |
160 | ||
161 | /* | |
162 | * We have 3 different interrupt types: | |
163 | * - MAL interrupts indicating successful transfer | |
164 | * - MAL error interrupts indicating MAL related errors | |
165 | * - EMAC interrupts indicating EMAC related errors | |
166 | * | |
167 | * All those interrupts can be on different UIC's, but since | |
168 | * now at least all interrupts from one type are on the same | |
169 | * UIC. Only exception is 440GX where the EMAC interrupts are | |
170 | * spread over two UIC's! | |
171 | */ | |
5de85140 SR |
172 | #if defined(CONFIG_440GX) |
173 | #define UIC_BASE_MAL UIC1_DCR_BASE | |
174 | #define UIC_BASE_MAL_ERR UIC2_DCR_BASE | |
175 | #define UIC_BASE_EMAC UIC2_DCR_BASE | |
176 | #define UIC_BASE_EMAC_B UIC3_DCR_BASE | |
177 | #else | |
d1631fe1 SR |
178 | #define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10)) |
179 | #define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10)) | |
180 | #define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10)) | |
d1631fe1 SR |
181 | #define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10)) |
182 | #endif | |
ba56f625 | 183 | |
d6c61aab | 184 | #undef INFO_4XX_ENET |
ba56f625 | 185 | |
265817c7 WD |
186 | #define BI_PHYMODE_NONE 0 |
187 | #define BI_PHYMODE_ZMII 1 | |
3c74e32a | 188 | #define BI_PHYMODE_RGMII 2 |
887e2ec9 SR |
189 | #define BI_PHYMODE_GMII 3 |
190 | #define BI_PHYMODE_RTBI 4 | |
191 | #define BI_PHYMODE_TBI 5 | |
dbbd1257 | 192 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
8ac41e3e | 193 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 194 | defined(CONFIG_405EX) |
887e2ec9 SR |
195 | #define BI_PHYMODE_SMII 6 |
196 | #define BI_PHYMODE_MII 7 | |
8ac41e3e SR |
197 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
198 | #define BI_PHYMODE_RMII 8 | |
199 | #endif | |
887e2ec9 | 200 | #endif |
78d78236 | 201 | #define BI_PHYMODE_SGMII 9 |
3c74e32a | 202 | |
1941cce7 | 203 | #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
dbbd1257 | 204 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
8ac41e3e | 205 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 206 | defined(CONFIG_405EX) |
887e2ec9 SR |
207 | #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1)) |
208 | #endif | |
d6c61aab | 209 | |
8ac41e3e SR |
210 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
211 | #define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n)) | |
212 | #endif | |
213 | ||
214 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
215 | #define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */ | |
216 | #else | |
217 | #define MAL_RX_CHAN_MUL 1 | |
218 | #endif | |
219 | ||
78d78236 VG |
220 | /*--------------------------------------------------------------------+ |
221 | * Fixed PHY (PHY-less) support for Ethernet Ports. | |
222 | *--------------------------------------------------------------------*/ | |
223 | ||
224 | /* | |
225 | * Some boards do not have a PHY for each ethernet port. These ports | |
226 | * are known as Fixed PHY (or PHY-less) ports. For such ports, set | |
227 | * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and | |
6d0f6bcf | 228 | * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and |
78d78236 VG |
229 | * duplex should be for these ports in the board configuration |
230 | * file. | |
231 | * | |
232 | * For Example: | |
233 | * #define CONFIG_FIXED_PHY 0xFFFFFFFF | |
234 | * | |
235 | * #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY | |
236 | * #define CONFIG_PHY1_ADDR 1 | |
237 | * #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY | |
238 | * #define CONFIG_PHY3_ADDR 3 | |
239 | * | |
6d0f6bcf | 240 | * #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \ |
78d78236 VG |
241 | * {devnum, speed, duplex}, |
242 | * | |
6d0f6bcf JCPV |
243 | * #define CONFIG_SYS_FIXED_PHY_PORTS \ |
244 | * CONFIG_SYS_FIXED_PHY_PORT(0,1000,FULL) \ | |
245 | * CONFIG_SYS_FIXED_PHY_PORT(2,100,HALF) | |
78d78236 VG |
246 | */ |
247 | ||
248 | #ifndef CONFIG_FIXED_PHY | |
249 | #define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */ | |
250 | #endif | |
251 | ||
6d0f6bcf JCPV |
252 | #ifndef CONFIG_SYS_FIXED_PHY_PORTS |
253 | #define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */ | |
78d78236 VG |
254 | #endif |
255 | ||
256 | struct fixed_phy_port { | |
257 | unsigned int devnum; /* ethernet port */ | |
258 | unsigned int speed; /* specified speed 10,100 or 1000 */ | |
259 | unsigned int duplex; /* specified duplex FULL or HALF */ | |
260 | }; | |
261 | ||
262 | static const struct fixed_phy_port fixed_phy_port[] = { | |
6d0f6bcf | 263 | CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */ |
78d78236 VG |
264 | }; |
265 | ||
ba56f625 WD |
266 | /*-----------------------------------------------------------------------------+ |
267 | * Global variables. TX and RX descriptors and buffers. | |
268 | *-----------------------------------------------------------------------------*/ | |
d6c61aab | 269 | #if !defined(CONFIG_NET_MULTI) |
4f92ac36 | 270 | struct eth_device *emac0_dev = NULL; |
d6c61aab SR |
271 | #endif |
272 | ||
1e25f957 SR |
273 | /* |
274 | * Get count of EMAC devices (doesn't have to be the max. possible number | |
275 | * supported by the cpu) | |
353f2688 SR |
276 | * |
277 | * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the | |
278 | * EMAC count is possible. As it is needed for the Kilauea/Haleakala | |
279 | * 405EX/405EXr eval board, using the same binary. | |
1e25f957 | 280 | */ |
353f2688 SR |
281 | #if defined(CONFIG_BOARD_EMAC_COUNT) |
282 | #define LAST_EMAC_NUM board_emac_count() | |
283 | #else /* CONFIG_BOARD_EMAC_COUNT */ | |
1e25f957 SR |
284 | #if defined(CONFIG_HAS_ETH3) |
285 | #define LAST_EMAC_NUM 4 | |
286 | #elif defined(CONFIG_HAS_ETH2) | |
287 | #define LAST_EMAC_NUM 3 | |
288 | #elif defined(CONFIG_HAS_ETH1) | |
289 | #define LAST_EMAC_NUM 2 | |
290 | #else | |
291 | #define LAST_EMAC_NUM 1 | |
292 | #endif | |
353f2688 | 293 | #endif /* CONFIG_BOARD_EMAC_COUNT */ |
d6c61aab | 294 | |
5fb692ca SR |
295 | /* normal boards start with EMAC0 */ |
296 | #if !defined(CONFIG_EMAC_NR_START) | |
297 | #define CONFIG_EMAC_NR_START 0 | |
298 | #endif | |
299 | ||
ff768cb1 SR |
300 | #define MAL_RX_DESC_SIZE 2048 |
301 | #define MAL_TX_DESC_SIZE 2048 | |
302 | #define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE) | |
303 | ||
ba56f625 WD |
304 | /*-----------------------------------------------------------------------------+ |
305 | * Prototypes and externals. | |
306 | *-----------------------------------------------------------------------------*/ | |
307 | static void enet_rcv (struct eth_device *dev, unsigned long malisr); | |
308 | ||
309 | int enetInt (struct eth_device *dev); | |
310 | static void mal_err (struct eth_device *dev, unsigned long isr, | |
311 | unsigned long uic, unsigned long maldef, | |
312 | unsigned long mal_errr); | |
313 | static void emac_err (struct eth_device *dev, unsigned long isr); | |
314 | ||
63ff004c MB |
315 | extern int phy_setup_aneg (char *devname, unsigned char addr); |
316 | extern int emac4xx_miiphy_read (char *devname, unsigned char addr, | |
317 | unsigned char reg, unsigned short *value); | |
318 | extern int emac4xx_miiphy_write (char *devname, unsigned char addr, | |
319 | unsigned char reg, unsigned short value); | |
d6c61aab | 320 | |
353f2688 SR |
321 | int board_emac_count(void); |
322 | ||
8ac41e3e SR |
323 | static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p) |
324 | { | |
325 | #if defined(CONFIG_440SPE) || \ | |
326 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
327 | defined(CONFIG_405EX) | |
328 | u32 val; | |
329 | ||
330 | mfsdr(sdr_mfr, val); | |
331 | val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); | |
332 | mtsdr(sdr_mfr, val); | |
333 | #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
334 | u32 val; | |
335 | ||
336 | mfsdr(SDR0_ETH_CFG, val); | |
337 | val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum); | |
338 | mtsdr(SDR0_ETH_CFG, val); | |
339 | #endif | |
340 | } | |
341 | ||
342 | static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p) | |
343 | { | |
344 | #if defined(CONFIG_440SPE) || \ | |
345 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
346 | defined(CONFIG_405EX) | |
347 | u32 val; | |
348 | ||
349 | mfsdr(sdr_mfr, val); | |
350 | val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); | |
351 | mtsdr(sdr_mfr, val); | |
352 | #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
353 | u32 val; | |
354 | ||
355 | mfsdr(SDR0_ETH_CFG, val); | |
356 | val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum); | |
357 | mtsdr(SDR0_ETH_CFG, val); | |
358 | #endif | |
359 | } | |
360 | ||
ba56f625 | 361 | /*-----------------------------------------------------------------------------+ |
d6c61aab | 362 | | ppc_4xx_eth_halt |
ba56f625 | 363 | | Disable MAL channel, and EMACn |
ba56f625 | 364 | +-----------------------------------------------------------------------------*/ |
d6c61aab | 365 | static void ppc_4xx_eth_halt (struct eth_device *dev) |
ba56f625 | 366 | { |
d6c61aab | 367 | EMAC_4XX_HW_PST hw_p = dev->priv; |
9ad31989 | 368 | u32 val = 10000; |
ba56f625 | 369 | |
2d83476a | 370 | out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ |
ba56f625 WD |
371 | |
372 | /* 1st reset MAL channel */ | |
373 | /* Note: writing a 0 to a channel has no effect */ | |
d6c61aab SR |
374 | #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) |
375 | mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2))); | |
376 | #else | |
ba56f625 | 377 | mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum)); |
d6c61aab | 378 | #endif |
ba56f625 WD |
379 | mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum)); |
380 | ||
381 | /* wait for reset */ | |
d6c61aab | 382 | while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) { |
ba56f625 | 383 | udelay (1000); /* Delay 1 MS so as not to hammer the register */ |
9ad31989 SR |
384 | val--; |
385 | if (val == 0) | |
ba56f625 | 386 | break; |
ba56f625 WD |
387 | } |
388 | ||
6c5879f3 | 389 | /* provide clocks for EMAC internal loopback */ |
8ac41e3e | 390 | emac_loopback_enable(hw_p); |
6c5879f3 | 391 | |
8ac41e3e | 392 | /* EMAC RESET */ |
2d83476a | 393 | out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); |
ba56f625 | 394 | |
6c5879f3 | 395 | /* remove clocks for EMAC internal loopback */ |
8ac41e3e | 396 | emac_loopback_disable(hw_p); |
6c5879f3 | 397 | |
a93316c5 | 398 | #ifndef CONFIG_NETCONSOLE |
c157d8e2 | 399 | hw_p->print_speed = 1; /* print speed message again next time */ |
a93316c5 | 400 | #endif |
c157d8e2 | 401 | |
4c9e8557 SR |
402 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
403 | /* don't bypass the TAHOE0/TAHOE1 cores for Linux */ | |
9ad31989 SR |
404 | mfsdr(SDR0_ETH_CFG, val); |
405 | val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); | |
406 | mtsdr(SDR0_ETH_CFG, val); | |
4c9e8557 SR |
407 | #endif |
408 | ||
ba56f625 WD |
409 | return; |
410 | } | |
411 | ||
846b0dd2 | 412 | #if defined (CONFIG_440GX) |
d6c61aab | 413 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) |
855a496f WD |
414 | { |
415 | unsigned long pfc1; | |
416 | unsigned long zmiifer; | |
417 | unsigned long rmiifer; | |
418 | ||
419 | mfsdr(sdr_pfc1, pfc1); | |
420 | pfc1 = SDR0_PFC1_EPS_DECODE(pfc1); | |
421 | ||
422 | zmiifer = 0; | |
423 | rmiifer = 0; | |
424 | ||
425 | switch (pfc1) { | |
426 | case 1: | |
427 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
428 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); | |
429 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2); | |
430 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3); | |
431 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
432 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
433 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
434 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
435 | break; | |
436 | case 2: | |
f6e495f5 SR |
437 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); |
438 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); | |
439 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2); | |
440 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3); | |
855a496f WD |
441 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; |
442 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
443 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
444 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
445 | break; | |
446 | case 3: | |
447 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
448 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
449 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
450 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
451 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
452 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
453 | break; | |
454 | case 4: | |
455 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); | |
456 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); | |
457 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2); | |
458 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3); | |
459 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
460 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
461 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
462 | bis->bi_phymode[3] = BI_PHYMODE_RGMII; | |
463 | break; | |
464 | case 5: | |
465 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); | |
466 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); | |
467 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2); | |
468 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); | |
469 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
470 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
471 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
472 | bis->bi_phymode[3] = BI_PHYMODE_RGMII; | |
473 | break; | |
474 | case 6: | |
475 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); | |
476 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); | |
477 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
855a496f WD |
478 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; |
479 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
480 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
855a496f WD |
481 | break; |
482 | case 0: | |
483 | default: | |
484 | zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum); | |
485 | rmiifer = 0x0; | |
486 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
487 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
488 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
489 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
490 | break; | |
491 | } | |
492 | ||
493 | /* Ensure we setup mdio for this devnum and ONLY this devnum */ | |
494 | zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); | |
495 | ||
ff768cb1 SR |
496 | out_be32((void *)ZMII_FER, zmiifer); |
497 | out_be32((void *)RGMII_FER, rmiifer); | |
855a496f WD |
498 | |
499 | return ((int)pfc1); | |
855a496f | 500 | } |
6c5879f3 | 501 | #endif /* CONFIG_440_GX */ |
855a496f | 502 | |
887e2ec9 SR |
503 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
504 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) | |
505 | { | |
506 | unsigned long zmiifer=0x0; | |
37ed6cdd | 507 | unsigned long pfc1; |
887e2ec9 | 508 | |
37ed6cdd MF |
509 | mfsdr(sdr_pfc1, pfc1); |
510 | pfc1 &= SDR0_PFC1_SELECT_MASK; | |
511 | ||
2f15278c | 512 | switch (pfc1) { |
37ed6cdd | 513 | case SDR0_PFC1_SELECT_CONFIG_2: |
887e2ec9 | 514 | /* 1 x GMII port */ |
2d83476a SR |
515 | out_be32((void *)ZMII_FER, 0x00); |
516 | out_be32((void *)RGMII_FER, 0x00000037); | |
887e2ec9 SR |
517 | bis->bi_phymode[0] = BI_PHYMODE_GMII; |
518 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
519 | break; | |
37ed6cdd | 520 | case SDR0_PFC1_SELECT_CONFIG_4: |
887e2ec9 | 521 | /* 2 x RGMII ports */ |
2d83476a SR |
522 | out_be32((void *)ZMII_FER, 0x00); |
523 | out_be32((void *)RGMII_FER, 0x00000055); | |
887e2ec9 SR |
524 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; |
525 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
526 | break; | |
37ed6cdd | 527 | case SDR0_PFC1_SELECT_CONFIG_6: |
887e2ec9 | 528 | /* 2 x SMII ports */ |
2d83476a SR |
529 | out_be32((void *)ZMII_FER, |
530 | ((ZMII_FER_SMII) << ZMII_FER_V(0)) | | |
531 | ((ZMII_FER_SMII) << ZMII_FER_V(1))); | |
532 | out_be32((void *)RGMII_FER, 0x00000000); | |
37ed6cdd MF |
533 | bis->bi_phymode[0] = BI_PHYMODE_SMII; |
534 | bis->bi_phymode[1] = BI_PHYMODE_SMII; | |
535 | break; | |
536 | case SDR0_PFC1_SELECT_CONFIG_1_2: | |
537 | /* only 1 x MII supported */ | |
2d83476a SR |
538 | out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); |
539 | out_be32((void *)RGMII_FER, 0x00000000); | |
37ed6cdd MF |
540 | bis->bi_phymode[0] = BI_PHYMODE_MII; |
541 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
887e2ec9 SR |
542 | break; |
543 | default: | |
544 | break; | |
545 | } | |
546 | ||
547 | /* Ensure we setup mdio for this devnum and ONLY this devnum */ | |
2d83476a | 548 | zmiifer = in_be32((void *)ZMII_FER); |
887e2ec9 | 549 | zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); |
2d83476a | 550 | out_be32((void *)ZMII_FER, zmiifer); |
887e2ec9 SR |
551 | |
552 | return ((int)0x0); | |
553 | } | |
554 | #endif /* CONFIG_440EPX */ | |
555 | ||
dbbd1257 SR |
556 | #if defined(CONFIG_405EX) |
557 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) | |
558 | { | |
1740c1bf | 559 | u32 rgmiifer = 0; |
dbbd1257 SR |
560 | |
561 | /* | |
1740c1bf GE |
562 | * The 405EX(r)'s RGMII bridge can operate in one of several |
563 | * modes, only one of which (2 x RGMII) allows the | |
564 | * simultaneous use of both EMACs on the 405EX. | |
dbbd1257 | 565 | */ |
1740c1bf GE |
566 | |
567 | switch (CONFIG_EMAC_PHY_MODE) { | |
568 | ||
569 | case EMAC_PHY_MODE_NONE: | |
570 | /* No ports */ | |
571 | rgmiifer |= RGMII_FER_DIS << 0; | |
572 | rgmiifer |= RGMII_FER_DIS << 4; | |
573 | out_be32((void *)RGMII_FER, rgmiifer); | |
574 | bis->bi_phymode[0] = BI_PHYMODE_NONE; | |
575 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
576 | break; | |
577 | case EMAC_PHY_MODE_NONE_RGMII: | |
578 | /* 1 x RGMII port on channel 0 */ | |
579 | rgmiifer |= RGMII_FER_RGMII << 0; | |
580 | rgmiifer |= RGMII_FER_DIS << 4; | |
581 | out_be32((void *)RGMII_FER, rgmiifer); | |
582 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; | |
583 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
584 | break; | |
585 | case EMAC_PHY_MODE_RGMII_NONE: | |
586 | /* 1 x RGMII port on channel 1 */ | |
587 | rgmiifer |= RGMII_FER_DIS << 0; | |
588 | rgmiifer |= RGMII_FER_RGMII << 4; | |
589 | out_be32((void *)RGMII_FER, rgmiifer); | |
590 | bis->bi_phymode[0] = BI_PHYMODE_NONE; | |
591 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
592 | break; | |
593 | case EMAC_PHY_MODE_RGMII_RGMII: | |
dbbd1257 | 594 | /* 2 x RGMII ports */ |
1740c1bf GE |
595 | rgmiifer |= RGMII_FER_RGMII << 0; |
596 | rgmiifer |= RGMII_FER_RGMII << 4; | |
597 | out_be32((void *)RGMII_FER, rgmiifer); | |
dbbd1257 SR |
598 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; |
599 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
600 | break; | |
1740c1bf GE |
601 | case EMAC_PHY_MODE_NONE_GMII: |
602 | /* 1 x GMII port on channel 0 */ | |
603 | rgmiifer |= RGMII_FER_GMII << 0; | |
604 | rgmiifer |= RGMII_FER_DIS << 4; | |
605 | out_be32((void *)RGMII_FER, rgmiifer); | |
606 | bis->bi_phymode[0] = BI_PHYMODE_GMII; | |
607 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
608 | break; | |
609 | case EMAC_PHY_MODE_NONE_MII: | |
610 | /* 1 x MII port on channel 0 */ | |
611 | rgmiifer |= RGMII_FER_MII << 0; | |
612 | rgmiifer |= RGMII_FER_DIS << 4; | |
613 | out_be32((void *)RGMII_FER, rgmiifer); | |
614 | bis->bi_phymode[0] = BI_PHYMODE_MII; | |
615 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
616 | break; | |
617 | case EMAC_PHY_MODE_GMII_NONE: | |
618 | /* 1 x GMII port on channel 1 */ | |
619 | rgmiifer |= RGMII_FER_DIS << 0; | |
620 | rgmiifer |= RGMII_FER_GMII << 4; | |
621 | out_be32((void *)RGMII_FER, rgmiifer); | |
622 | bis->bi_phymode[0] = BI_PHYMODE_NONE; | |
623 | bis->bi_phymode[1] = BI_PHYMODE_GMII; | |
624 | break; | |
625 | case EMAC_PHY_MODE_MII_NONE: | |
626 | /* 1 x MII port on channel 1 */ | |
627 | rgmiifer |= RGMII_FER_DIS << 0; | |
628 | rgmiifer |= RGMII_FER_MII << 4; | |
629 | out_be32((void *)RGMII_FER, rgmiifer); | |
630 | bis->bi_phymode[0] = BI_PHYMODE_NONE; | |
631 | bis->bi_phymode[1] = BI_PHYMODE_MII; | |
dbbd1257 SR |
632 | break; |
633 | default: | |
634 | break; | |
635 | } | |
636 | ||
637 | /* Ensure we setup mdio for this devnum and ONLY this devnum */ | |
1740c1bf GE |
638 | rgmiifer = in_be32((void *)RGMII_FER); |
639 | rgmiifer |= (1 << (19-devnum)); | |
640 | out_be32((void *)RGMII_FER, rgmiifer); | |
dbbd1257 SR |
641 | |
642 | return ((int)0x0); | |
643 | } | |
644 | #endif /* CONFIG_405EX */ | |
645 | ||
8ac41e3e SR |
646 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
647 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) | |
648 | { | |
649 | u32 eth_cfg; | |
650 | u32 zmiifer; /* ZMII0_FER reg. */ | |
651 | u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */ | |
652 | u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */ | |
4c9e8557 | 653 | int mode; |
8ac41e3e SR |
654 | |
655 | zmiifer = 0; | |
656 | rmiifer = 0; | |
657 | rmiifer1 = 0; | |
658 | ||
4c9e8557 SR |
659 | #if defined(CONFIG_460EX) |
660 | mode = 9; | |
78d78236 VG |
661 | mfsdr(SDR0_ETH_CFG, eth_cfg); |
662 | if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) && | |
663 | ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0)) | |
664 | mode = 11; /* config SGMII */ | |
4c9e8557 SR |
665 | #else |
666 | mode = 10; | |
78d78236 VG |
667 | mfsdr(SDR0_ETH_CFG, eth_cfg); |
668 | if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) && | |
669 | ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0) && | |
670 | ((eth_cfg & SDR0_ETH_CFG_SGMII2_ENABLE) > 0)) | |
671 | mode = 12; /* config SGMII */ | |
4c9e8557 SR |
672 | #endif |
673 | ||
8ac41e3e SR |
674 | /* TODO: |
675 | * NOTE: 460GT has 2 RGMII bridge cores: | |
676 | * emac0 ------ RGMII0_BASE | |
677 | * | | |
678 | * emac1 -----+ | |
679 | * | |
680 | * emac2 ------ RGMII1_BASE | |
681 | * | | |
682 | * emac3 -----+ | |
683 | * | |
684 | * 460EX has 1 RGMII bridge core: | |
685 | * and RGMII1_BASE is disabled | |
686 | * emac0 ------ RGMII0_BASE | |
687 | * | | |
688 | * emac1 -----+ | |
689 | */ | |
690 | ||
691 | /* | |
692 | * Right now only 2*RGMII is supported. Please extend when needed. | |
693 | * sr - 2008-02-19 | |
78d78236 VG |
694 | * Add SGMII support. |
695 | * vg - 2008-07-28 | |
8ac41e3e | 696 | */ |
4c9e8557 | 697 | switch (mode) { |
8ac41e3e SR |
698 | case 1: |
699 | /* 1 MII - 460EX */ | |
700 | /* GMC0 EMAC4_0, ZMII Bridge */ | |
701 | zmiifer |= ZMII_FER_MII << ZMII_FER_V(0); | |
702 | bis->bi_phymode[0] = BI_PHYMODE_MII; | |
703 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
704 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
705 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
706 | break; | |
707 | case 2: | |
708 | /* 2 MII - 460GT */ | |
709 | /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */ | |
710 | zmiifer |= ZMII_FER_MII << ZMII_FER_V(0); | |
711 | zmiifer |= ZMII_FER_MII << ZMII_FER_V(2); | |
712 | bis->bi_phymode[0] = BI_PHYMODE_MII; | |
713 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
714 | bis->bi_phymode[2] = BI_PHYMODE_MII; | |
715 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
716 | break; | |
717 | case 3: | |
718 | /* 2 RMII - 460EX */ | |
719 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */ | |
720 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
721 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); | |
722 | bis->bi_phymode[0] = BI_PHYMODE_RMII; | |
723 | bis->bi_phymode[1] = BI_PHYMODE_RMII; | |
724 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
725 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
726 | break; | |
727 | case 4: | |
728 | /* 4 RMII - 460GT */ | |
729 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */ | |
730 | /* ZMII Bridge */ | |
731 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
732 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); | |
733 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2); | |
734 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3); | |
735 | bis->bi_phymode[0] = BI_PHYMODE_RMII; | |
736 | bis->bi_phymode[1] = BI_PHYMODE_RMII; | |
737 | bis->bi_phymode[2] = BI_PHYMODE_RMII; | |
738 | bis->bi_phymode[3] = BI_PHYMODE_RMII; | |
739 | break; | |
740 | case 5: | |
741 | /* 2 SMII - 460EX */ | |
742 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */ | |
743 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); | |
744 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); | |
745 | bis->bi_phymode[0] = BI_PHYMODE_SMII; | |
746 | bis->bi_phymode[1] = BI_PHYMODE_SMII; | |
747 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
748 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
749 | break; | |
750 | case 6: | |
751 | /* 4 SMII - 460GT */ | |
752 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */ | |
753 | /* ZMII Bridge */ | |
754 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); | |
755 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); | |
756 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2); | |
757 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3); | |
758 | bis->bi_phymode[0] = BI_PHYMODE_SMII; | |
759 | bis->bi_phymode[1] = BI_PHYMODE_SMII; | |
760 | bis->bi_phymode[2] = BI_PHYMODE_SMII; | |
761 | bis->bi_phymode[3] = BI_PHYMODE_SMII; | |
762 | break; | |
763 | case 7: | |
764 | /* This is the default mode that we want for board bringup - Maple */ | |
765 | /* 1 GMII - 460EX */ | |
766 | /* GMC0 EMAC4_0, RGMII Bridge 0 */ | |
767 | rmiifer |= RGMII_FER_MDIO(0); | |
768 | ||
769 | if (devnum == 0) { | |
770 | rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */ | |
771 | bis->bi_phymode[0] = BI_PHYMODE_GMII; | |
772 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
773 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
774 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
775 | } else { | |
776 | rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */ | |
777 | bis->bi_phymode[0] = BI_PHYMODE_NONE; | |
778 | bis->bi_phymode[1] = BI_PHYMODE_GMII; | |
779 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
780 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
781 | } | |
782 | break; | |
783 | case 8: | |
784 | /* 2 GMII - 460GT */ | |
785 | /* GMC0 EMAC4_0, RGMII Bridge 0 */ | |
786 | /* GMC1 EMAC4_2, RGMII Bridge 1 */ | |
787 | rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */ | |
788 | rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */ | |
789 | rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */ | |
790 | rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */ | |
791 | ||
792 | bis->bi_phymode[0] = BI_PHYMODE_GMII; | |
793 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
794 | bis->bi_phymode[2] = BI_PHYMODE_GMII; | |
795 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
796 | break; | |
797 | case 9: | |
798 | /* 2 RGMII - 460EX */ | |
799 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ | |
800 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
801 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); | |
802 | rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */ | |
803 | ||
804 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; | |
805 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
806 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
807 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
808 | break; | |
809 | case 10: | |
810 | /* 4 RGMII - 460GT */ | |
811 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ | |
812 | /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */ | |
813 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
814 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); | |
815 | rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
816 | rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3); | |
817 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; | |
818 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
819 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
820 | bis->bi_phymode[3] = BI_PHYMODE_RGMII; | |
821 | break; | |
78d78236 VG |
822 | case 11: |
823 | /* 2 SGMII - 460EX */ | |
824 | bis->bi_phymode[0] = BI_PHYMODE_SGMII; | |
825 | bis->bi_phymode[1] = BI_PHYMODE_SGMII; | |
826 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
827 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
828 | break; | |
829 | case 12: | |
830 | /* 3 SGMII - 460GT */ | |
831 | bis->bi_phymode[0] = BI_PHYMODE_SGMII; | |
832 | bis->bi_phymode[1] = BI_PHYMODE_SGMII; | |
833 | bis->bi_phymode[2] = BI_PHYMODE_SGMII; | |
834 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
835 | break; | |
8ac41e3e SR |
836 | default: |
837 | break; | |
838 | } | |
839 | ||
840 | /* Set EMAC for MDIO */ | |
841 | mfsdr(SDR0_ETH_CFG, eth_cfg); | |
842 | eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0; | |
843 | mtsdr(SDR0_ETH_CFG, eth_cfg); | |
844 | ||
845 | out_be32((void *)RGMII_FER, rmiifer); | |
846 | #if defined(CONFIG_460GT) | |
847 | out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1); | |
848 | #endif | |
849 | ||
850 | /* bypass the TAHOE0/TAHOE1 cores for U-Boot */ | |
851 | mfsdr(SDR0_ETH_CFG, eth_cfg); | |
852 | eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); | |
853 | mtsdr(SDR0_ETH_CFG, eth_cfg); | |
854 | ||
855 | return 0; | |
856 | } | |
857 | #endif /* CONFIG_460EX || CONFIG_460GT */ | |
858 | ||
ff768cb1 SR |
859 | static inline void *malloc_aligned(u32 size, u32 align) |
860 | { | |
861 | return (void *)(((u32)malloc(size + align) + align - 1) & | |
862 | ~(align - 1)); | |
863 | } | |
864 | ||
d6c61aab | 865 | static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) |
ba56f625 | 866 | { |
ff768cb1 | 867 | int i; |
d6c61aab | 868 | unsigned long reg = 0; |
ba56f625 WD |
869 | unsigned long msr; |
870 | unsigned long speed; | |
871 | unsigned long duplex; | |
872 | unsigned long failsafe; | |
873 | unsigned mode_reg; | |
874 | unsigned short devnum; | |
875 | unsigned short reg_short; | |
887e2ec9 SR |
876 | #if defined(CONFIG_440GX) || \ |
877 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
dbbd1257 | 878 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
8ac41e3e | 879 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 880 | defined(CONFIG_405EX) |
d6c61aab | 881 | sys_info_t sysinfo; |
887e2ec9 | 882 | #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ |
dbbd1257 | 883 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
8ac41e3e | 884 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 885 | defined(CONFIG_405EX) |
6e7fb6ea SR |
886 | int ethgroup = -1; |
887 | #endif | |
6c5879f3 | 888 | #endif |
ff768cb1 SR |
889 | u32 bd_cached; |
890 | u32 bd_uncached = 0; | |
4fae35a5 AG |
891 | #ifdef CONFIG_4xx_DCACHE |
892 | static u32 last_used_ea = 0; | |
893 | #endif | |
e54ec0f0 SR |
894 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
895 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ | |
896 | defined(CONFIG_405EX) | |
897 | int rgmii_channel; | |
898 | #endif | |
6c5879f3 | 899 | |
d6c61aab | 900 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
901 | |
902 | /* before doing anything, figure out if we have a MAC address */ | |
903 | /* if not, bail */ | |
4f92ac36 SR |
904 | if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) { |
905 | printf("ERROR: ethaddr not set!\n"); | |
ba56f625 | 906 | return -1; |
4f92ac36 | 907 | } |
ba56f625 | 908 | |
887e2ec9 SR |
909 | #if defined(CONFIG_440GX) || \ |
910 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
dbbd1257 | 911 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
8ac41e3e | 912 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 913 | defined(CONFIG_405EX) |
ba56f625 WD |
914 | /* Need to get the OPB frequency so we can access the PHY */ |
915 | get_sys_info (&sysinfo); | |
d6c61aab | 916 | #endif |
ba56f625 | 917 | |
ba56f625 WD |
918 | msr = mfmsr (); |
919 | mtmsr (msr & ~(MSR_EE)); /* disable interrupts */ | |
920 | ||
921 | devnum = hw_p->devnum; | |
922 | ||
d6c61aab | 923 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
924 | /* AS.HARNOIS |
925 | * We should have : | |
265817c7 | 926 | * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX |
ba56f625 WD |
927 | * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it |
928 | * is possible that new packets (without relationship with | |
929 | * current transfer) have got the time to arrived before | |
930 | * netloop calls eth_halt | |
931 | */ | |
932 | printf ("About preceeding transfer (eth%d):\n" | |
933 | "- Sent packet number %d\n" | |
934 | "- Received packet number %d\n" | |
935 | "- Handled packet number %d\n", | |
936 | hw_p->devnum, | |
937 | hw_p->stats.pkts_tx, | |
938 | hw_p->stats.pkts_rx, hw_p->stats.pkts_handled); | |
939 | ||
940 | hw_p->stats.pkts_tx = 0; | |
941 | hw_p->stats.pkts_rx = 0; | |
942 | hw_p->stats.pkts_handled = 0; | |
6c5879f3 | 943 | hw_p->print_speed = 1; /* print speed message again next time */ |
ba56f625 WD |
944 | #endif |
945 | ||
265817c7 WD |
946 | hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */ |
947 | hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */ | |
ba56f625 WD |
948 | |
949 | hw_p->rx_slot = 0; /* MAL Receive Slot */ | |
950 | hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */ | |
951 | hw_p->rx_u_index = 0; /* Receive User Queue Index */ | |
952 | ||
953 | hw_p->tx_slot = 0; /* MAL Transmit Slot */ | |
954 | hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */ | |
955 | hw_p->tx_u_index = 0; /* Transmit User Queue Index */ | |
956 | ||
6c5879f3 | 957 | #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) |
ba56f625 WD |
958 | /* set RMII mode */ |
959 | /* NOTE: 440GX spec states that mode is mutually exclusive */ | |
960 | /* NOTE: Therefore, disable all other EMACS, since we handle */ | |
961 | /* NOTE: only one emac at a time */ | |
962 | reg = 0; | |
2d83476a | 963 | out_be32((void *)ZMII_FER, 0); |
ba56f625 | 964 | udelay (100); |
ba56f625 | 965 | |
8ac41e3e | 966 | #if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) |
2d83476a | 967 | out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); |
8ac41e3e SR |
968 | #elif defined(CONFIG_440GX) || \ |
969 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
970 | defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
d6c61aab | 971 | ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); |
0e6d798c | 972 | #endif |
c57c7980 | 973 | |
2d83476a | 974 | out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); |
6e7fb6ea | 975 | #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ |
dbbd1257 SR |
976 | #if defined(CONFIG_405EX) |
977 | ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); | |
978 | #endif | |
d6c61aab | 979 | |
8ac41e3e | 980 | sync(); |
0e6d798c | 981 | |
6c5879f3 | 982 | /* provide clocks for EMAC internal loopback */ |
8ac41e3e | 983 | emac_loopback_enable(hw_p); |
0e6d798c | 984 | |
8ac41e3e | 985 | /* EMAC RESET */ |
2d83476a | 986 | out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); |
ba56f625 | 987 | |
8ac41e3e SR |
988 | /* remove clocks for EMAC internal loopback */ |
989 | emac_loopback_disable(hw_p); | |
990 | ||
ba56f625 | 991 | failsafe = 1000; |
2d83476a | 992 | while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { |
ba56f625 WD |
993 | udelay (1000); |
994 | failsafe--; | |
995 | } | |
887e2ec9 SR |
996 | if (failsafe <= 0) |
997 | printf("\nProblem resetting EMAC!\n"); | |
ba56f625 | 998 | |
887e2ec9 SR |
999 | #if defined(CONFIG_440GX) || \ |
1000 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
dbbd1257 | 1001 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
8ac41e3e | 1002 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 1003 | defined(CONFIG_405EX) |
ba56f625 WD |
1004 | /* Whack the M1 register */ |
1005 | mode_reg = 0x0; | |
1006 | mode_reg &= ~0x00000038; | |
1007 | if (sysinfo.freqOPB <= 50000000); | |
1008 | else if (sysinfo.freqOPB <= 66666667) | |
1009 | mode_reg |= EMAC_M1_OBCI_66; | |
1010 | else if (sysinfo.freqOPB <= 83333333) | |
1011 | mode_reg |= EMAC_M1_OBCI_83; | |
1012 | else if (sysinfo.freqOPB <= 100000000) | |
1013 | mode_reg |= EMAC_M1_OBCI_100; | |
1014 | else | |
1015 | mode_reg |= EMAC_M1_OBCI_GT100; | |
1016 | ||
2d83476a | 1017 | out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); |
6e7fb6ea | 1018 | #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ |
ba56f625 | 1019 | |
78d78236 VG |
1020 | #if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \ |
1021 | defined(CONFIG_GPCS_PHY2_ADDR) || defined(CONFIG_GPCS_PHY3_ADDR) | |
1022 | if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) { | |
1023 | /* | |
1024 | * In SGMII mode, GPCS access is needed for | |
1025 | * communication with the internal SGMII SerDes. | |
1026 | */ | |
1027 | switch (devnum) { | |
1028 | #if defined(CONFIG_GPCS_PHY_ADDR) | |
1029 | case 0: | |
1030 | reg = CONFIG_GPCS_PHY_ADDR; | |
1031 | break; | |
1032 | #endif | |
1033 | #if defined(CONFIG_GPCS_PHY1_ADDR) | |
1034 | case 1: | |
1035 | reg = CONFIG_GPCS_PHY1_ADDR; | |
1036 | break; | |
1037 | #endif | |
1038 | #if defined(CONFIG_GPCS_PHY2_ADDR) | |
1039 | case 2: | |
1040 | reg = CONFIG_GPCS_PHY2_ADDR; | |
1041 | break; | |
1042 | #endif | |
1043 | #if defined(CONFIG_GPCS_PHY3_ADDR) | |
1044 | case 3: | |
1045 | reg = CONFIG_GPCS_PHY3_ADDR; | |
1046 | break; | |
1047 | #endif | |
1048 | } | |
1049 | ||
1050 | mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); | |
1051 | mode_reg |= EMAC_M1_MF_1000GPCS | EMAC_M1_IPPA_SET(reg); | |
1052 | out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); | |
1053 | ||
1054 | /* Configure GPCS interface to recommended setting for SGMII */ | |
1055 | miiphy_reset(dev->name, reg); | |
1056 | miiphy_write(dev->name, reg, 0x04, 0x8120); /* AsymPause, FDX */ | |
1057 | miiphy_write(dev->name, reg, 0x07, 0x2801); /* msg_pg, toggle */ | |
1058 | miiphy_write(dev->name, reg, 0x00, 0x0140); /* 1Gbps, FDX */ | |
1059 | } | |
1060 | #endif /* defined(CONFIG_GPCS_PHY_ADDR) */ | |
1061 | ||
ba56f625 WD |
1062 | /* wait for PHY to complete auto negotiation */ |
1063 | reg_short = 0; | |
ba56f625 WD |
1064 | switch (devnum) { |
1065 | case 0: | |
1066 | reg = CONFIG_PHY_ADDR; | |
1067 | break; | |
d6c61aab | 1068 | #if defined (CONFIG_PHY1_ADDR) |
ba56f625 WD |
1069 | case 1: |
1070 | reg = CONFIG_PHY1_ADDR; | |
1071 | break; | |
d6c61aab | 1072 | #endif |
4c9e8557 | 1073 | #if defined (CONFIG_PHY2_ADDR) |
ba56f625 WD |
1074 | case 2: |
1075 | reg = CONFIG_PHY2_ADDR; | |
1076 | break; | |
4c9e8557 SR |
1077 | #endif |
1078 | #if defined (CONFIG_PHY3_ADDR) | |
ba56f625 WD |
1079 | case 3: |
1080 | reg = CONFIG_PHY3_ADDR; | |
1081 | break; | |
1082 | #endif | |
1083 | default: | |
1084 | reg = CONFIG_PHY_ADDR; | |
1085 | break; | |
1086 | } | |
1087 | ||
3c74e32a WD |
1088 | bis->bi_phynum[devnum] = reg; |
1089 | ||
78d78236 VG |
1090 | if (reg == CONFIG_FIXED_PHY) |
1091 | goto get_speed; | |
1092 | ||
d6c61aab | 1093 | #if defined(CONFIG_PHY_RESET) |
a06752e3 WD |
1094 | /* |
1095 | * Reset the phy, only if its the first time through | |
1096 | * otherwise, just check the speeds & feeds | |
1097 | */ | |
1098 | if (hw_p->first_init == 0) { | |
ec0c2ec7 | 1099 | #if defined(CONFIG_M88E1111_PHY) |
887e2ec9 SR |
1100 | miiphy_write (dev->name, reg, 0x14, 0x0ce3); |
1101 | miiphy_write (dev->name, reg, 0x18, 0x4101); | |
1102 | miiphy_write (dev->name, reg, 0x09, 0x0e00); | |
1103 | miiphy_write (dev->name, reg, 0x04, 0x01e1); | |
1104 | #endif | |
78d78236 VG |
1105 | #if defined(CONFIG_M88E1112_PHY) |
1106 | if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) { | |
1107 | /* | |
1108 | * Marvell 88E1112 PHY needs to have the SGMII MAC | |
1109 | * interace (page 2) properly configured to | |
1110 | * communicate with the 460EX/GT GPCS interface. | |
1111 | */ | |
1112 | ||
1113 | /* Set access to Page 2 */ | |
1114 | miiphy_write(dev->name, reg, 0x16, 0x0002); | |
1115 | ||
1116 | miiphy_write(dev->name, reg, 0x00, 0x0040); /* 1Gbps */ | |
1117 | miiphy_read(dev->name, reg, 0x1a, ®_short); | |
1118 | reg_short |= 0x8000; /* bypass Auto-Negotiation */ | |
1119 | miiphy_write(dev->name, reg, 0x1a, reg_short); | |
1120 | miiphy_reset(dev->name, reg); /* reset MAC interface */ | |
1121 | ||
1122 | /* Reset access to Page 0 */ | |
1123 | miiphy_write(dev->name, reg, 0x16, 0x0000); | |
1124 | } | |
1125 | #endif /* defined(CONFIG_M88E1112_PHY) */ | |
63ff004c | 1126 | miiphy_reset (dev->name, reg); |
ba56f625 | 1127 | |
887e2ec9 SR |
1128 | #if defined(CONFIG_440GX) || \ |
1129 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
dbbd1257 | 1130 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
8ac41e3e | 1131 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 1132 | defined(CONFIG_405EX) |
887e2ec9 | 1133 | |
0e6d798c | 1134 | #if defined(CONFIG_CIS8201_PHY) |
fc1cfcdb | 1135 | /* |
17f50f22 SR |
1136 | * Cicada 8201 PHY needs to have an extended register whacked |
1137 | * for RGMII mode. | |
fc1cfcdb | 1138 | */ |
887e2ec9 | 1139 | if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) { |
b79316f2 | 1140 | #if defined(CONFIG_CIS8201_SHORT_ETCH) |
63ff004c | 1141 | miiphy_write (dev->name, reg, 23, 0x1300); |
b79316f2 | 1142 | #else |
63ff004c | 1143 | miiphy_write (dev->name, reg, 23, 0x1000); |
b79316f2 | 1144 | #endif |
17f50f22 SR |
1145 | /* |
1146 | * Vitesse VSC8201/Cicada CIS8201 errata: | |
1147 | * Interoperability problem with Intel 82547EI phys | |
1148 | * This work around (provided by Vitesse) changes | |
1149 | * the default timer convergence from 8ms to 12ms | |
1150 | */ | |
63ff004c MB |
1151 | miiphy_write (dev->name, reg, 0x1f, 0x2a30); |
1152 | miiphy_write (dev->name, reg, 0x08, 0x0200); | |
1153 | miiphy_write (dev->name, reg, 0x1f, 0x52b5); | |
1154 | miiphy_write (dev->name, reg, 0x02, 0x0004); | |
1155 | miiphy_write (dev->name, reg, 0x01, 0x0671); | |
1156 | miiphy_write (dev->name, reg, 0x00, 0x8fae); | |
1157 | miiphy_write (dev->name, reg, 0x1f, 0x2a30); | |
1158 | miiphy_write (dev->name, reg, 0x08, 0x0000); | |
1159 | miiphy_write (dev->name, reg, 0x1f, 0x0000); | |
17f50f22 SR |
1160 | /* end Vitesse/Cicada errata */ |
1161 | } | |
6ca8646c | 1162 | #endif /* defined(CONFIG_CIS8201_PHY) */ |
5fb692ca SR |
1163 | |
1164 | #if defined(CONFIG_ET1011C_PHY) | |
1165 | /* | |
1166 | * Agere ET1011c PHY needs to have an extended register whacked | |
1167 | * for RGMII mode. | |
1168 | */ | |
1169 | if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) { | |
1170 | miiphy_read (dev->name, reg, 0x16, ®_short); | |
1171 | reg_short &= ~(0x7); | |
1172 | reg_short |= 0x6; /* RGMII DLL Delay*/ | |
1173 | miiphy_write (dev->name, reg, 0x16, reg_short); | |
1174 | ||
1175 | miiphy_read (dev->name, reg, 0x17, ®_short); | |
1176 | reg_short &= ~(0x40); | |
1177 | miiphy_write (dev->name, reg, 0x17, reg_short); | |
1178 | ||
1179 | miiphy_write(dev->name, reg, 0x1c, 0x74f0); | |
1180 | } | |
6ca8646c | 1181 | #endif /* defined(CONFIG_ET1011C_PHY) */ |
5fb692ca | 1182 | |
6ca8646c | 1183 | #endif /* defined(CONFIG_440GX) ... */ |
a06752e3 | 1184 | /* Start/Restart autonegotiation */ |
63ff004c | 1185 | phy_setup_aneg (dev->name, reg); |
a06752e3 WD |
1186 | udelay (1000); |
1187 | } | |
d6c61aab | 1188 | #endif /* defined(CONFIG_PHY_RESET) */ |
ba56f625 | 1189 | |
63ff004c | 1190 | miiphy_read (dev->name, reg, PHY_BMSR, ®_short); |
ba56f625 WD |
1191 | |
1192 | /* | |
0e6d798c | 1193 | * Wait if PHY is capable of autonegotiation and autonegotiation is not complete |
ba56f625 WD |
1194 | */ |
1195 | if ((reg_short & PHY_BMSR_AUTN_ABLE) | |
1196 | && !(reg_short & PHY_BMSR_AUTN_COMP)) { | |
1197 | puts ("Waiting for PHY auto negotiation to complete"); | |
1198 | i = 0; | |
1199 | while (!(reg_short & PHY_BMSR_AUTN_COMP)) { | |
1200 | /* | |
1201 | * Timeout reached ? | |
1202 | */ | |
1203 | if (i > PHY_AUTONEGOTIATE_TIMEOUT) { | |
1204 | puts (" TIMEOUT !\n"); | |
1205 | break; | |
1206 | } | |
1207 | ||
1208 | if ((i++ % 1000) == 0) { | |
1209 | putc ('.'); | |
1210 | } | |
1211 | udelay (1000); /* 1 ms */ | |
63ff004c | 1212 | miiphy_read (dev->name, reg, PHY_BMSR, ®_short); |
ba56f625 WD |
1213 | } |
1214 | puts (" done\n"); | |
1215 | udelay (500000); /* another 500 ms (results in faster booting) */ | |
1216 | } | |
d6c61aab | 1217 | |
78d78236 VG |
1218 | get_speed: |
1219 | if (reg == CONFIG_FIXED_PHY) { | |
1220 | for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) { | |
1221 | if (devnum == fixed_phy_port[i].devnum) { | |
1222 | speed = fixed_phy_port[i].speed; | |
1223 | duplex = fixed_phy_port[i].duplex; | |
1224 | break; | |
1225 | } | |
1226 | } | |
1227 | ||
1228 | if (i == ARRAY_SIZE(fixed_phy_port)) { | |
1229 | printf("ERROR: PHY (%s) not configured correctly!\n", | |
1230 | dev->name); | |
1231 | return -1; | |
1232 | } | |
1233 | } else { | |
1234 | speed = miiphy_speed(dev->name, reg); | |
1235 | duplex = miiphy_duplex(dev->name, reg); | |
1236 | } | |
ba56f625 WD |
1237 | |
1238 | if (hw_p->print_speed) { | |
1239 | hw_p->print_speed = 0; | |
5fb692ca SR |
1240 | printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n", |
1241 | (int) speed, (duplex == HALF) ? "HALF" : "FULL", | |
1242 | hw_p->devnum); | |
ba56f625 WD |
1243 | } |
1244 | ||
8ac41e3e SR |
1245 | #if defined(CONFIG_440) && \ |
1246 | !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ | |
1247 | !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ | |
1248 | !defined(CONFIG_460EX) && !defined(CONFIG_460GT) | |
846b0dd2 | 1249 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
c157d8e2 SR |
1250 | mfsdr(sdr_mfr, reg); |
1251 | if (speed == 100) { | |
1252 | reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M; | |
1253 | } else { | |
1254 | reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; | |
1255 | } | |
1256 | mtsdr(sdr_mfr, reg); | |
1257 | #endif | |
c57c7980 | 1258 | |
ba56f625 | 1259 | /* Set ZMII/RGMII speed according to the phy link speed */ |
ff768cb1 | 1260 | reg = in_be32((void *)ZMII_SSR); |
855a496f | 1261 | if ( (speed == 100) || (speed == 1000) ) |
ff768cb1 | 1262 | out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); |
ba56f625 | 1263 | else |
ff768cb1 | 1264 | out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); |
ba56f625 WD |
1265 | |
1266 | if ((devnum == 2) || (devnum == 3)) { | |
1267 | if (speed == 1000) | |
1268 | reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); | |
1269 | else if (speed == 100) | |
1270 | reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum)); | |
887e2ec9 | 1271 | else if (speed == 10) |
ba56f625 | 1272 | reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum)); |
887e2ec9 SR |
1273 | else { |
1274 | printf("Error in RGMII Speed\n"); | |
1275 | return -1; | |
1276 | } | |
ff768cb1 | 1277 | out_be32((void *)RGMII_SSR, reg); |
ba56f625 | 1278 | } |
6e7fb6ea | 1279 | #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ |
ba56f625 | 1280 | |
dbbd1257 | 1281 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
8ac41e3e | 1282 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 1283 | defined(CONFIG_405EX) |
e54ec0f0 SR |
1284 | if (devnum >= 2) |
1285 | rgmii_channel = devnum - 2; | |
1286 | else | |
1287 | rgmii_channel = devnum; | |
1288 | ||
887e2ec9 | 1289 | if (speed == 1000) |
e54ec0f0 | 1290 | reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel)); |
887e2ec9 | 1291 | else if (speed == 100) |
e54ec0f0 | 1292 | reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel)); |
887e2ec9 | 1293 | else if (speed == 10) |
e54ec0f0 | 1294 | reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel)); |
887e2ec9 SR |
1295 | else { |
1296 | printf("Error in RGMII Speed\n"); | |
1297 | return -1; | |
1298 | } | |
2d83476a | 1299 | out_be32((void *)RGMII_SSR, reg); |
8ac41e3e SR |
1300 | #if defined(CONFIG_460GT) |
1301 | if ((devnum == 2) || (devnum == 3)) | |
1302 | out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg); | |
1303 | #endif | |
887e2ec9 SR |
1304 | #endif |
1305 | ||
ba56f625 | 1306 | /* set the Mal configuration reg */ |
887e2ec9 SR |
1307 | #if defined(CONFIG_440GX) || \ |
1308 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
dbbd1257 | 1309 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
8ac41e3e | 1310 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 1311 | defined(CONFIG_405EX) |
17f50f22 SR |
1312 | mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | |
1313 | MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); | |
1314 | #else | |
1315 | mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); | |
ba56f625 | 1316 | /* Errata 1.12: MAL_1 -- Disable MAL bursting */ |
17f50f22 SR |
1317 | if (get_pvr() == PVR_440GP_RB) { |
1318 | mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB); | |
1319 | } | |
1320 | #endif | |
ba56f625 | 1321 | |
ba56f625 WD |
1322 | /* |
1323 | * Malloc MAL buffer desciptors, make sure they are | |
1324 | * aligned on cache line boundary size | |
1325 | * (401/403/IOP480 = 16, 405 = 32) | |
1326 | * and doesn't cross cache block boundaries. | |
1327 | */ | |
ff768cb1 SR |
1328 | if (hw_p->first_init == 0) { |
1329 | debug("*** Allocating descriptor memory ***\n"); | |
ba56f625 | 1330 | |
ff768cb1 SR |
1331 | bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096); |
1332 | if (!bd_cached) { | |
b002144e | 1333 | printf("%s: Error allocating MAL descriptor buffers!\n", __func__); |
ff768cb1 SR |
1334 | return -1; |
1335 | } | |
b79316f2 | 1336 | |
ff768cb1 | 1337 | #ifdef CONFIG_4xx_DCACHE |
ba79fde5 | 1338 | flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE); |
4fae35a5 | 1339 | if (!last_used_ea) |
6d0f6bcf JCPV |
1340 | #if defined(CONFIG_SYS_MEM_TOP_HIDE) |
1341 | bd_uncached = bis->bi_memsize + CONFIG_SYS_MEM_TOP_HIDE; | |
5e3dca57 | 1342 | #else |
4fae35a5 | 1343 | bd_uncached = bis->bi_memsize; |
5e3dca57 | 1344 | #endif |
4fae35a5 AG |
1345 | else |
1346 | bd_uncached = last_used_ea + MAL_ALLOC_SIZE; | |
1347 | ||
1348 | last_used_ea = bd_uncached; | |
ff768cb1 SR |
1349 | program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE, |
1350 | TLB_WORD2_I_ENABLE); | |
1351 | #else | |
1352 | bd_uncached = bd_cached; | |
1353 | #endif | |
1354 | hw_p->tx_phys = bd_cached; | |
1355 | hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE; | |
1356 | hw_p->tx = (mal_desc_t *)(bd_uncached); | |
1357 | hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE); | |
1358 | debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx); | |
ba56f625 WD |
1359 | } |
1360 | ||
1361 | for (i = 0; i < NUM_TX_BUFF; i++) { | |
1362 | hw_p->tx[i].ctrl = 0; | |
1363 | hw_p->tx[i].data_len = 0; | |
ff768cb1 SR |
1364 | if (hw_p->first_init == 0) |
1365 | hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE, | |
1366 | L1_CACHE_BYTES); | |
ba56f625 WD |
1367 | hw_p->tx[i].data_ptr = hw_p->txbuf_ptr; |
1368 | if ((NUM_TX_BUFF - 1) == i) | |
1369 | hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP; | |
1370 | hw_p->tx_run[i] = -1; | |
ff768cb1 | 1371 | debug("TX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->tx[i].data_ptr); |
ba56f625 WD |
1372 | } |
1373 | ||
1374 | for (i = 0; i < NUM_RX_BUFF; i++) { | |
1375 | hw_p->rx[i].ctrl = 0; | |
1376 | hw_p->rx[i].data_len = 0; | |
ff768cb1 | 1377 | hw_p->rx[i].data_ptr = (char *)NetRxPackets[i]; |
ba56f625 WD |
1378 | if ((NUM_RX_BUFF - 1) == i) |
1379 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP; | |
1380 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR; | |
1381 | hw_p->rx_ready[i] = -1; | |
ff768cb1 | 1382 | debug("RX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->rx[i].data_ptr); |
ba56f625 WD |
1383 | } |
1384 | ||
1385 | reg = 0x00000000; | |
1386 | ||
1387 | reg |= dev->enetaddr[0]; /* set high address */ | |
1388 | reg = reg << 8; | |
1389 | reg |= dev->enetaddr[1]; | |
1390 | ||
2d83476a | 1391 | out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg); |
ba56f625 WD |
1392 | |
1393 | reg = 0x00000000; | |
1394 | reg |= dev->enetaddr[2]; /* set low address */ | |
1395 | reg = reg << 8; | |
1396 | reg |= dev->enetaddr[3]; | |
1397 | reg = reg << 8; | |
1398 | reg |= dev->enetaddr[4]; | |
1399 | reg = reg << 8; | |
1400 | reg |= dev->enetaddr[5]; | |
1401 | ||
2d83476a | 1402 | out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg); |
ba56f625 WD |
1403 | |
1404 | switch (devnum) { | |
1405 | case 1: | |
1406 | /* setup MAL tx & rx channel pointers */ | |
d6c61aab | 1407 | #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) |
ff768cb1 | 1408 | mtdcr (maltxctp2r, hw_p->tx_phys); |
c157d8e2 | 1409 | #else |
ff768cb1 | 1410 | mtdcr (maltxctp1r, hw_p->tx_phys); |
c157d8e2 | 1411 | #endif |
d6c61aab | 1412 | #if defined(CONFIG_440) |
c157d8e2 | 1413 | mtdcr (maltxbattr, 0x0); |
ba56f625 | 1414 | mtdcr (malrxbattr, 0x0); |
d6c61aab | 1415 | #endif |
8ac41e3e SR |
1416 | |
1417 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
4c9e8557 | 1418 | mtdcr (malrxctp8r, hw_p->rx_phys); |
8ac41e3e SR |
1419 | /* set RX buffer size */ |
1420 | mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16); | |
1421 | #else | |
ff768cb1 | 1422 | mtdcr (malrxctp1r, hw_p->rx_phys); |
ba56f625 WD |
1423 | /* set RX buffer size */ |
1424 | mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16); | |
8ac41e3e | 1425 | #endif |
ba56f625 | 1426 | break; |
846b0dd2 | 1427 | #if defined (CONFIG_440GX) |
ba56f625 WD |
1428 | case 2: |
1429 | /* setup MAL tx & rx channel pointers */ | |
1430 | mtdcr (maltxbattr, 0x0); | |
ba56f625 | 1431 | mtdcr (malrxbattr, 0x0); |
ff768cb1 SR |
1432 | mtdcr (maltxctp2r, hw_p->tx_phys); |
1433 | mtdcr (malrxctp2r, hw_p->rx_phys); | |
ba56f625 WD |
1434 | /* set RX buffer size */ |
1435 | mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16); | |
1436 | break; | |
1437 | case 3: | |
1438 | /* setup MAL tx & rx channel pointers */ | |
1439 | mtdcr (maltxbattr, 0x0); | |
ff768cb1 | 1440 | mtdcr (maltxctp3r, hw_p->tx_phys); |
ba56f625 | 1441 | mtdcr (malrxbattr, 0x0); |
ff768cb1 | 1442 | mtdcr (malrxctp3r, hw_p->rx_phys); |
ba56f625 WD |
1443 | /* set RX buffer size */ |
1444 | mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16); | |
1445 | break; | |
c57c7980 | 1446 | #endif /* CONFIG_440GX */ |
4c9e8557 SR |
1447 | #if defined (CONFIG_460GT) |
1448 | case 2: | |
1449 | /* setup MAL tx & rx channel pointers */ | |
1450 | mtdcr (maltxbattr, 0x0); | |
1451 | mtdcr (malrxbattr, 0x0); | |
1452 | mtdcr (maltxctp2r, hw_p->tx_phys); | |
1453 | mtdcr (malrxctp16r, hw_p->rx_phys); | |
1454 | /* set RX buffer size */ | |
1455 | mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16); | |
1456 | break; | |
1457 | case 3: | |
1458 | /* setup MAL tx & rx channel pointers */ | |
1459 | mtdcr (maltxbattr, 0x0); | |
1460 | mtdcr (malrxbattr, 0x0); | |
1461 | mtdcr (maltxctp3r, hw_p->tx_phys); | |
1462 | mtdcr (malrxctp24r, hw_p->rx_phys); | |
1463 | /* set RX buffer size */ | |
1464 | mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16); | |
1465 | break; | |
1466 | #endif /* CONFIG_460GT */ | |
ba56f625 WD |
1467 | case 0: |
1468 | default: | |
1469 | /* setup MAL tx & rx channel pointers */ | |
d6c61aab | 1470 | #if defined(CONFIG_440) |
ba56f625 | 1471 | mtdcr (maltxbattr, 0x0); |
ba56f625 | 1472 | mtdcr (malrxbattr, 0x0); |
d6c61aab | 1473 | #endif |
ff768cb1 SR |
1474 | mtdcr (maltxctp0r, hw_p->tx_phys); |
1475 | mtdcr (malrxctp0r, hw_p->rx_phys); | |
ba56f625 WD |
1476 | /* set RX buffer size */ |
1477 | mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16); | |
1478 | break; | |
1479 | } | |
1480 | ||
1481 | /* Enable MAL transmit and receive channels */ | |
d6c61aab | 1482 | #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) |
c157d8e2 SR |
1483 | mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2))); |
1484 | #else | |
ba56f625 | 1485 | mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); |
c157d8e2 | 1486 | #endif |
ba56f625 WD |
1487 | mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); |
1488 | ||
1489 | /* set transmit enable & receive enable */ | |
2d83476a | 1490 | out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); |
ba56f625 | 1491 | |
2d83476a | 1492 | mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); |
76957cb3 SR |
1493 | |
1494 | /* set rx-/tx-fifo size */ | |
1495 | mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE; | |
ba56f625 WD |
1496 | |
1497 | /* set speed */ | |
6e7fb6ea | 1498 | if (speed == _1000BASET) { |
738815c0 SR |
1499 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
1500 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) | |
6e7fb6ea | 1501 | unsigned long pfc1; |
887e2ec9 | 1502 | |
6e7fb6ea SR |
1503 | mfsdr (sdr_pfc1, pfc1); |
1504 | pfc1 |= SDR0_PFC1_EM_1000; | |
1505 | mtsdr (sdr_pfc1, pfc1); | |
1506 | #endif | |
855a496f | 1507 | mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST; |
6e7fb6ea | 1508 | } else if (speed == _100BASET) |
ba56f625 WD |
1509 | mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST; |
1510 | else | |
1511 | mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */ | |
1512 | if (duplex == FULL) | |
1513 | mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST; | |
1514 | ||
2d83476a | 1515 | out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); |
ba56f625 WD |
1516 | |
1517 | /* Enable broadcast and indvidual address */ | |
1518 | /* TBS: enabling runts as some misbehaved nics will send runts */ | |
2d83476a | 1519 | out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); |
ba56f625 WD |
1520 | |
1521 | /* we probably need to set the tx mode1 reg? maybe at tx time */ | |
1522 | ||
1523 | /* set transmit request threshold register */ | |
2d83476a | 1524 | out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ |
ba56f625 | 1525 | |
265817c7 | 1526 | /* set receive low/high water mark register */ |
d6c61aab | 1527 | #if defined(CONFIG_440) |
6c5879f3 | 1528 | /* 440s has a 64 byte burst length */ |
2d83476a | 1529 | out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); |
d6c61aab SR |
1530 | #else |
1531 | /* 405s have a 16 byte burst length */ | |
2d83476a | 1532 | out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); |
d6c61aab | 1533 | #endif /* defined(CONFIG_440) */ |
2d83476a | 1534 | out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); |
ba56f625 WD |
1535 | |
1536 | /* Set fifo limit entry in tx mode 0 */ | |
2d83476a | 1537 | out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003); |
ba56f625 | 1538 | /* Frame gap set */ |
2d83476a | 1539 | out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); |
ba56f625 WD |
1540 | |
1541 | /* Set EMAC IER */ | |
d6c61aab | 1542 | hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE; |
ba56f625 WD |
1543 | if (speed == _100BASET) |
1544 | hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE; | |
1545 | ||
2d83476a SR |
1546 | out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ |
1547 | out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); | |
ba56f625 WD |
1548 | |
1549 | if (hw_p->first_init == 0) { | |
1550 | /* | |
1551 | * Connect interrupt service routines | |
1552 | */ | |
dbbd1257 SR |
1553 | irq_install_handler(ETH_IRQ_NUM(hw_p->devnum), |
1554 | (interrupt_handler_t *) enetInt, dev); | |
ba56f625 | 1555 | } |
ba56f625 WD |
1556 | |
1557 | mtmsr (msr); /* enable interrupts again */ | |
1558 | ||
1559 | hw_p->bis = bis; | |
1560 | hw_p->first_init = 1; | |
1561 | ||
802b769b | 1562 | return 0; |
ba56f625 WD |
1563 | } |
1564 | ||
1565 | ||
d6c61aab | 1566 | static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, |
ba56f625 WD |
1567 | int len) |
1568 | { | |
1569 | struct enet_frame *ef_ptr; | |
1570 | ulong time_start, time_now; | |
1571 | unsigned long temp_txm0; | |
d6c61aab | 1572 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1573 | |
1574 | ef_ptr = (struct enet_frame *) ptr; | |
1575 | ||
1576 | /*-----------------------------------------------------------------------+ | |
1577 | * Copy in our address into the frame. | |
1578 | *-----------------------------------------------------------------------*/ | |
1579 | (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH); | |
1580 | ||
1581 | /*-----------------------------------------------------------------------+ | |
1582 | * If frame is too long or too short, modify length. | |
1583 | *-----------------------------------------------------------------------*/ | |
1584 | /* TBS: where does the fragment go???? */ | |
1585 | if (len > ENET_MAX_MTU) | |
1586 | len = ENET_MAX_MTU; | |
1587 | ||
1588 | /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */ | |
1589 | memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len); | |
ba79fde5 | 1590 | flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len); |
ba56f625 WD |
1591 | |
1592 | /*-----------------------------------------------------------------------+ | |
1593 | * set TX Buffer busy, and send it | |
1594 | *-----------------------------------------------------------------------*/ | |
1595 | hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST | | |
1596 | EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) & | |
1597 | ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA); | |
1598 | if ((NUM_TX_BUFF - 1) == hw_p->tx_slot) | |
1599 | hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP; | |
1600 | ||
1601 | hw_p->tx[hw_p->tx_slot].data_len = (short) len; | |
1602 | hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY; | |
1603 | ||
8ac41e3e | 1604 | sync(); |
ba56f625 | 1605 | |
2d83476a SR |
1606 | out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, |
1607 | in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); | |
d6c61aab | 1608 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
1609 | hw_p->stats.pkts_tx++; |
1610 | #endif | |
1611 | ||
1612 | /*-----------------------------------------------------------------------+ | |
1613 | * poll unitl the packet is sent and then make sure it is OK | |
1614 | *-----------------------------------------------------------------------*/ | |
1615 | time_start = get_timer (0); | |
1616 | while (1) { | |
2d83476a | 1617 | temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr); |
ba56f625 WD |
1618 | /* loop until either TINT turns on or 3 seconds elapse */ |
1619 | if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) { | |
1620 | /* transmit is done, so now check for errors | |
1621 | * If there is an error, an interrupt should | |
1622 | * happen when we return | |
1623 | */ | |
1624 | time_now = get_timer (0); | |
1625 | if ((time_now - time_start) > 3000) { | |
1626 | return (-1); | |
1627 | } | |
1628 | } else { | |
1629 | return (len); | |
1630 | } | |
1631 | } | |
1632 | } | |
1633 | ||
ba56f625 WD |
1634 | int enetInt (struct eth_device *dev) |
1635 | { | |
1636 | int serviced; | |
1637 | int rc = -1; /* default to not us */ | |
d1631fe1 SR |
1638 | u32 mal_isr; |
1639 | u32 emac_isr = 0; | |
1640 | u32 mal_eob; | |
1641 | u32 uic_mal; | |
1642 | u32 uic_mal_err; | |
1643 | u32 uic_emac; | |
1644 | u32 uic_emac_b; | |
d6c61aab | 1645 | EMAC_4XX_HW_PST hw_p; |
ba56f625 WD |
1646 | |
1647 | /* | |
1648 | * Because the mal is generic, we need to get the current | |
1649 | * eth device | |
1650 | */ | |
d6c61aab SR |
1651 | #if defined(CONFIG_NET_MULTI) |
1652 | dev = eth_get_dev(); | |
1653 | #else | |
1654 | dev = emac0_dev; | |
1655 | #endif | |
ba56f625 WD |
1656 | |
1657 | hw_p = dev->priv; | |
1658 | ||
ba56f625 WD |
1659 | /* enter loop that stays in interrupt code until nothing to service */ |
1660 | do { | |
1661 | serviced = 0; | |
1662 | ||
d1631fe1 SR |
1663 | uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR); |
1664 | uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR); | |
1665 | uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR); | |
1666 | uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR); | |
887e2ec9 | 1667 | |
d1631fe1 SR |
1668 | if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB)) |
1669 | && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) | |
1670 | && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) { | |
ba56f625 WD |
1671 | /* not for us */ |
1672 | return (rc); | |
1673 | } | |
d1631fe1 | 1674 | |
ba56f625 | 1675 | /* get and clear controller status interrupts */ |
d1631fe1 SR |
1676 | /* look at MAL and EMAC error interrupts */ |
1677 | if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) { | |
1678 | /* we have a MAL error interrupt */ | |
1679 | mal_isr = mfdcr(malesr); | |
1680 | mal_err(dev, mal_isr, uic_mal_err, | |
1681 | MAL_UIC_DEF, MAL_UIC_ERR); | |
ba56f625 | 1682 | |
d1631fe1 SR |
1683 | /* clear MAL error interrupt status bits */ |
1684 | mtdcr(UIC_BASE_MAL_ERR + UIC_SR, | |
1685 | UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE); | |
ba56f625 | 1686 | |
d1631fe1 | 1687 | return -1; |
ba56f625 WD |
1688 | } |
1689 | ||
d1631fe1 SR |
1690 | /* look for EMAC errors */ |
1691 | if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) { | |
1692 | emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); | |
1693 | emac_err(dev, emac_isr); | |
6e7fb6ea | 1694 | |
d1631fe1 SR |
1695 | /* clear EMAC error interrupt status bits */ |
1696 | mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx); | |
1697 | mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB); | |
6e7fb6ea | 1698 | |
d1631fe1 | 1699 | return -1; |
ba56f625 | 1700 | } |
d6c61aab | 1701 | |
d1631fe1 SR |
1702 | /* handle MAX TX EOB interrupt from a tx */ |
1703 | if (uic_mal & UIC_MAL_TXEOB) { | |
1704 | /* clear MAL interrupt status bits */ | |
1705 | mal_eob = mfdcr(maltxeobisr); | |
1706 | mtdcr(maltxeobisr, mal_eob); | |
1707 | mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB); | |
1708 | ||
1709 | /* indicate that we serviced an interrupt */ | |
1710 | serviced = 1; | |
1711 | rc = 0; | |
d6c61aab SR |
1712 | } |
1713 | ||
d1631fe1 SR |
1714 | /* handle MAL RX EOB interupt from a receive */ |
1715 | /* check for EOB on valid channels */ | |
1716 | if (uic_mal & UIC_MAL_RXEOB) { | |
1717 | mal_eob = mfdcr(malrxeobisr); | |
1718 | if (mal_eob & | |
1719 | (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) { | |
1720 | /* push packet to upper layer */ | |
1721 | enet_rcv(dev, emac_isr); | |
d6c61aab | 1722 | |
d1631fe1 SR |
1723 | /* clear MAL interrupt status bits */ |
1724 | mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB); | |
d6c61aab | 1725 | |
d6c61aab SR |
1726 | /* indicate that we serviced an interrupt */ |
1727 | serviced = 1; | |
1728 | rc = 0; | |
1729 | } | |
1730 | } | |
d1631fe1 | 1731 | } while (serviced); |
d6c61aab SR |
1732 | |
1733 | return (rc); | |
1734 | } | |
1735 | ||
ba56f625 WD |
1736 | /*-----------------------------------------------------------------------------+ |
1737 | * MAL Error Routine | |
1738 | *-----------------------------------------------------------------------------*/ | |
1739 | static void mal_err (struct eth_device *dev, unsigned long isr, | |
1740 | unsigned long uic, unsigned long maldef, | |
1741 | unsigned long mal_errr) | |
1742 | { | |
d6c61aab | 1743 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1744 | |
1745 | mtdcr (malesr, isr); /* clear interrupt */ | |
1746 | ||
1747 | /* clear DE interrupt */ | |
1748 | mtdcr (maltxdeir, 0xC0000000); | |
1749 | mtdcr (malrxdeir, 0x80000000); | |
1750 | ||
d6c61aab | 1751 | #ifdef INFO_4XX_ENET |
265817c7 | 1752 | printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr); |
ba56f625 WD |
1753 | #endif |
1754 | ||
1755 | eth_init (hw_p->bis); /* start again... */ | |
1756 | } | |
1757 | ||
1758 | /*-----------------------------------------------------------------------------+ | |
1759 | * EMAC Error Routine | |
1760 | *-----------------------------------------------------------------------------*/ | |
1761 | static void emac_err (struct eth_device *dev, unsigned long isr) | |
1762 | { | |
d6c61aab | 1763 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1764 | |
1765 | printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr); | |
2d83476a | 1766 | out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr); |
ba56f625 WD |
1767 | } |
1768 | ||
1769 | /*-----------------------------------------------------------------------------+ | |
1770 | * enet_rcv() handles the ethernet receive data | |
1771 | *-----------------------------------------------------------------------------*/ | |
1772 | static void enet_rcv (struct eth_device *dev, unsigned long malisr) | |
1773 | { | |
1774 | struct enet_frame *ef_ptr; | |
1775 | unsigned long data_len; | |
1776 | unsigned long rx_eob_isr; | |
d6c61aab | 1777 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1778 | |
1779 | int handled = 0; | |
1780 | int i; | |
1781 | int loop_count = 0; | |
1782 | ||
1783 | rx_eob_isr = mfdcr (malrxeobisr); | |
8ac41e3e | 1784 | if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) { |
ba56f625 WD |
1785 | /* clear EOB */ |
1786 | mtdcr (malrxeobisr, rx_eob_isr); | |
1787 | ||
1788 | /* EMAC RX done */ | |
1789 | while (1) { /* do all */ | |
1790 | i = hw_p->rx_slot; | |
1791 | ||
1792 | if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl) | |
1793 | || (loop_count >= NUM_RX_BUFF)) | |
1794 | break; | |
a2e1c709 | 1795 | |
ba56f625 | 1796 | loop_count++; |
ba56f625 | 1797 | handled++; |
8ac41e3e | 1798 | data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */ |
ba56f625 WD |
1799 | if (data_len) { |
1800 | if (data_len > ENET_MAX_MTU) /* Check len */ | |
1801 | data_len = 0; | |
1802 | else { | |
1803 | if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */ | |
1804 | data_len = 0; | |
1805 | hw_p->stats.rx_err_log[hw_p-> | |
1806 | rx_err_index] | |
1807 | = hw_p->rx[i].ctrl; | |
1808 | hw_p->rx_err_index++; | |
1809 | if (hw_p->rx_err_index == | |
1810 | MAX_ERR_LOG) | |
1811 | hw_p->rx_err_index = | |
1812 | 0; | |
fc1cfcdb | 1813 | } /* emac_erros */ |
ba56f625 | 1814 | } /* data_len < max mtu */ |
fc1cfcdb | 1815 | } /* if data_len */ |
ba56f625 WD |
1816 | if (!data_len) { /* no data */ |
1817 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */ | |
1818 | ||
1819 | hw_p->stats.data_len_err++; /* Error at Rx */ | |
1820 | } | |
1821 | ||
1822 | /* !data_len */ | |
1823 | /* AS.HARNOIS */ | |
1824 | /* Check if user has already eaten buffer */ | |
1825 | /* if not => ERROR */ | |
1826 | else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) { | |
1827 | if (hw_p->is_receiving) | |
1828 | printf ("ERROR : Receive buffers are full!\n"); | |
1829 | break; | |
1830 | } else { | |
1831 | hw_p->stats.rx_frames++; | |
1832 | hw_p->stats.rx += data_len; | |
1833 | ef_ptr = (struct enet_frame *) hw_p->rx[i]. | |
1834 | data_ptr; | |
d6c61aab | 1835 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
1836 | hw_p->stats.pkts_rx++; |
1837 | #endif | |
1838 | /* AS.HARNOIS | |
1839 | * use ring buffer | |
1840 | */ | |
1841 | hw_p->rx_ready[hw_p->rx_i_index] = i; | |
1842 | hw_p->rx_i_index++; | |
1843 | if (NUM_RX_BUFF == hw_p->rx_i_index) | |
1844 | hw_p->rx_i_index = 0; | |
1845 | ||
a2e1c709 SR |
1846 | hw_p->rx_slot++; |
1847 | if (NUM_RX_BUFF == hw_p->rx_slot) | |
1848 | hw_p->rx_slot = 0; | |
1849 | ||
ba56f625 WD |
1850 | /* AS.HARNOIS |
1851 | * free receive buffer only when | |
1852 | * buffer has been handled (eth_rx) | |
1853 | rx[i].ctrl |= MAL_RX_CTRL_EMPTY; | |
1854 | */ | |
1855 | } /* if data_len */ | |
1856 | } /* while */ | |
1857 | } /* if EMACK_RXCHL */ | |
1858 | } | |
1859 | ||
1860 | ||
d6c61aab | 1861 | static int ppc_4xx_eth_rx (struct eth_device *dev) |
ba56f625 WD |
1862 | { |
1863 | int length; | |
1864 | int user_index; | |
1865 | unsigned long msr; | |
d6c61aab | 1866 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 | 1867 | |
265817c7 | 1868 | hw_p->is_receiving = 1; /* tell driver */ |
ba56f625 WD |
1869 | |
1870 | for (;;) { | |
1871 | /* AS.HARNOIS | |
1872 | * use ring buffer and | |
1873 | * get index from rx buffer desciptor queue | |
1874 | */ | |
1875 | user_index = hw_p->rx_ready[hw_p->rx_u_index]; | |
1876 | if (user_index == -1) { | |
1877 | length = -1; | |
1878 | break; /* nothing received - leave for() loop */ | |
1879 | } | |
1880 | ||
1881 | msr = mfmsr (); | |
1882 | mtmsr (msr & ~(MSR_EE)); | |
1883 | ||
8ac41e3e | 1884 | length = hw_p->rx[user_index].data_len & 0x0fff; |
ba56f625 WD |
1885 | |
1886 | /* Pass the packet up to the protocol layers. */ | |
265817c7 WD |
1887 | /* NetReceive(NetRxPackets[rxIdx], length - 4); */ |
1888 | /* NetReceive(NetRxPackets[i], length); */ | |
ff768cb1 SR |
1889 | invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr, |
1890 | (u32)hw_p->rx[user_index].data_ptr + | |
ba79fde5 | 1891 | length - 4); |
ba56f625 WD |
1892 | NetReceive (NetRxPackets[user_index], length - 4); |
1893 | /* Free Recv Buffer */ | |
1894 | hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY; | |
1895 | /* Free rx buffer descriptor queue */ | |
1896 | hw_p->rx_ready[hw_p->rx_u_index] = -1; | |
1897 | hw_p->rx_u_index++; | |
1898 | if (NUM_RX_BUFF == hw_p->rx_u_index) | |
1899 | hw_p->rx_u_index = 0; | |
1900 | ||
d6c61aab | 1901 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
1902 | hw_p->stats.pkts_handled++; |
1903 | #endif | |
1904 | ||
1905 | mtmsr (msr); /* Enable IRQ's */ | |
1906 | } | |
1907 | ||
265817c7 | 1908 | hw_p->is_receiving = 0; /* tell driver */ |
ba56f625 WD |
1909 | |
1910 | return length; | |
1911 | } | |
1912 | ||
d6c61aab | 1913 | int ppc_4xx_eth_initialize (bd_t * bis) |
ba56f625 WD |
1914 | { |
1915 | static int virgin = 0; | |
ba56f625 WD |
1916 | struct eth_device *dev; |
1917 | int eth_num = 0; | |
d6c61aab | 1918 | EMAC_4XX_HW_PST hw = NULL; |
5fb692ca SR |
1919 | u8 ethaddr[4 + CONFIG_EMAC_NR_START][6]; |
1920 | u32 hw_addr[4]; | |
d1631fe1 | 1921 | u32 mal_ier; |
ba56f625 | 1922 | |
846b0dd2 | 1923 | #if defined(CONFIG_440GX) |
c157d8e2 SR |
1924 | unsigned long pfc1; |
1925 | ||
ba56f625 WD |
1926 | mfsdr (sdr_pfc1, pfc1); |
1927 | pfc1 &= ~(0x01e00000); | |
1928 | pfc1 |= 0x01200000; | |
1929 | mtsdr (sdr_pfc1, pfc1); | |
c157d8e2 | 1930 | #endif |
6c5879f3 | 1931 | |
5fb692ca SR |
1932 | /* first clear all mac-addresses */ |
1933 | for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) | |
1934 | memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6); | |
a06752e3 | 1935 | |
1e25f957 | 1936 | for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { |
ba56f625 | 1937 | switch (eth_num) { |
e2ffd59b | 1938 | default: /* fall through */ |
ba56f625 | 1939 | case 0: |
5fb692ca SR |
1940 | memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], |
1941 | bis->bi_enetaddr, 6); | |
1942 | hw_addr[eth_num] = 0x0; | |
ba56f625 | 1943 | break; |
e2ffd59b | 1944 | #ifdef CONFIG_HAS_ETH1 |
ba56f625 | 1945 | case 1: |
5fb692ca SR |
1946 | memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], |
1947 | bis->bi_enet1addr, 6); | |
1948 | hw_addr[eth_num] = 0x100; | |
ba56f625 | 1949 | break; |
e2ffd59b WD |
1950 | #endif |
1951 | #ifdef CONFIG_HAS_ETH2 | |
ba56f625 | 1952 | case 2: |
5fb692ca SR |
1953 | memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], |
1954 | bis->bi_enet2addr, 6); | |
4c9e8557 SR |
1955 | #if defined(CONFIG_460GT) |
1956 | hw_addr[eth_num] = 0x300; | |
1957 | #else | |
5fb692ca | 1958 | hw_addr[eth_num] = 0x400; |
4c9e8557 | 1959 | #endif |
ba56f625 | 1960 | break; |
e2ffd59b WD |
1961 | #endif |
1962 | #ifdef CONFIG_HAS_ETH3 | |
ba56f625 | 1963 | case 3: |
5fb692ca SR |
1964 | memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], |
1965 | bis->bi_enet3addr, 6); | |
4c9e8557 SR |
1966 | #if defined(CONFIG_460GT) |
1967 | hw_addr[eth_num] = 0x400; | |
1968 | #else | |
5fb692ca | 1969 | hw_addr[eth_num] = 0x600; |
4c9e8557 | 1970 | #endif |
ba56f625 | 1971 | break; |
e2ffd59b | 1972 | #endif |
ba56f625 | 1973 | } |
5fb692ca SR |
1974 | } |
1975 | ||
1976 | /* set phy num and mode */ | |
1977 | bis->bi_phynum[0] = CONFIG_PHY_ADDR; | |
1978 | bis->bi_phymode[0] = 0; | |
1979 | ||
1980 | #if defined(CONFIG_PHY1_ADDR) | |
1981 | bis->bi_phynum[1] = CONFIG_PHY1_ADDR; | |
1982 | bis->bi_phymode[1] = 0; | |
1983 | #endif | |
1984 | #if defined(CONFIG_440GX) | |
1985 | bis->bi_phynum[2] = CONFIG_PHY2_ADDR; | |
1986 | bis->bi_phynum[3] = CONFIG_PHY3_ADDR; | |
1987 | bis->bi_phymode[2] = 2; | |
1988 | bis->bi_phymode[3] = 2; | |
dbbd1257 | 1989 | #endif |
5fb692ca | 1990 | |
dbbd1257 SR |
1991 | #if defined(CONFIG_440GX) || \ |
1992 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
1993 | defined(CONFIG_405EX) | |
5fb692ca SR |
1994 | ppc_4xx_eth_setup_bridge(0, bis); |
1995 | #endif | |
1996 | ||
1997 | for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { | |
1998 | /* | |
1999 | * See if we can actually bring up the interface, | |
2000 | * otherwise, skip it | |
2001 | */ | |
2002 | if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) { | |
2003 | bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; | |
2004 | continue; | |
2005 | } | |
ba56f625 WD |
2006 | |
2007 | /* Allocate device structure */ | |
2008 | dev = (struct eth_device *) malloc (sizeof (*dev)); | |
2009 | if (dev == NULL) { | |
d6c61aab | 2010 | printf ("ppc_4xx_eth_initialize: " |
3f85ce27 | 2011 | "Cannot allocate eth_device %d\n", eth_num); |
ba56f625 WD |
2012 | return (-1); |
2013 | } | |
b2532eff | 2014 | memset(dev, 0, sizeof(*dev)); |
ba56f625 WD |
2015 | |
2016 | /* Allocate our private use data */ | |
d6c61aab | 2017 | hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw)); |
ba56f625 | 2018 | if (hw == NULL) { |
d6c61aab | 2019 | printf ("ppc_4xx_eth_initialize: " |
3f85ce27 | 2020 | "Cannot allocate private hw data for eth_device %d", |
ba56f625 WD |
2021 | eth_num); |
2022 | free (dev); | |
2023 | return (-1); | |
2024 | } | |
b2532eff | 2025 | memset(hw, 0, sizeof(*hw)); |
ba56f625 | 2026 | |
5fb692ca SR |
2027 | hw->hw_addr = hw_addr[eth_num]; |
2028 | memcpy (dev->enetaddr, ethaddr[eth_num], 6); | |
ba56f625 | 2029 | hw->devnum = eth_num; |
c157d8e2 | 2030 | hw->print_speed = 1; |
ba56f625 | 2031 | |
5fb692ca | 2032 | sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START); |
ba56f625 | 2033 | dev->priv = (void *) hw; |
d6c61aab SR |
2034 | dev->init = ppc_4xx_eth_init; |
2035 | dev->halt = ppc_4xx_eth_halt; | |
2036 | dev->send = ppc_4xx_eth_send; | |
2037 | dev->recv = ppc_4xx_eth_rx; | |
ba56f625 WD |
2038 | |
2039 | if (0 == virgin) { | |
2040 | /* set the MAL IER ??? names may change with new spec ??? */ | |
dbbd1257 SR |
2041 | #if defined(CONFIG_440SPE) || \ |
2042 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
8ac41e3e | 2043 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 2044 | defined(CONFIG_405EX) |
6c5879f3 MB |
2045 | mal_ier = |
2046 | MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE | | |
2047 | MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ; | |
2048 | #else | |
ba56f625 WD |
2049 | mal_ier = |
2050 | MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | | |
2051 | MAL_IER_OPBE | MAL_IER_PLBE; | |
6c5879f3 | 2052 | #endif |
ba56f625 WD |
2053 | mtdcr (malesr, 0xffffffff); /* clear pending interrupts */ |
2054 | mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */ | |
2055 | mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */ | |
2056 | mtdcr (malier, mal_ier); | |
2057 | ||
2058 | /* install MAL interrupt handler */ | |
d1631fe1 | 2059 | irq_install_handler (VECNUM_MAL_SERR, |
ba56f625 WD |
2060 | (interrupt_handler_t *) enetInt, |
2061 | dev); | |
d1631fe1 | 2062 | irq_install_handler (VECNUM_MAL_TXEOB, |
ba56f625 WD |
2063 | (interrupt_handler_t *) enetInt, |
2064 | dev); | |
d1631fe1 | 2065 | irq_install_handler (VECNUM_MAL_RXEOB, |
ba56f625 WD |
2066 | (interrupt_handler_t *) enetInt, |
2067 | dev); | |
d1631fe1 | 2068 | irq_install_handler (VECNUM_MAL_TXDE, |
ba56f625 WD |
2069 | (interrupt_handler_t *) enetInt, |
2070 | dev); | |
d1631fe1 | 2071 | irq_install_handler (VECNUM_MAL_RXDE, |
ba56f625 WD |
2072 | (interrupt_handler_t *) enetInt, |
2073 | dev); | |
2074 | virgin = 1; | |
2075 | } | |
2076 | ||
d6c61aab | 2077 | #if defined(CONFIG_NET_MULTI) |
ba56f625 | 2078 | eth_register (dev); |
d6c61aab SR |
2079 | #else |
2080 | emac0_dev = dev; | |
2081 | #endif | |
6c5879f3 MB |
2082 | |
2083 | #if defined(CONFIG_NET_MULTI) | |
3a1ed1e1 | 2084 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
63ff004c | 2085 | miiphy_register (dev->name, |
6e7fb6ea | 2086 | emac4xx_miiphy_read, emac4xx_miiphy_write); |
63ff004c | 2087 | #endif |
6c5879f3 | 2088 | #endif |
ba56f625 | 2089 | } /* end for each supported device */ |
802b769b SR |
2090 | |
2091 | return 0; | |
ba56f625 | 2092 | } |
d6c61aab | 2093 | |
d6c61aab SR |
2094 | #if !defined(CONFIG_NET_MULTI) |
2095 | void eth_halt (void) { | |
2096 | if (emac0_dev) { | |
2097 | ppc_4xx_eth_halt(emac0_dev); | |
2098 | free(emac0_dev); | |
2099 | emac0_dev = NULL; | |
2100 | } | |
2101 | } | |
2102 | ||
2103 | int eth_init (bd_t *bis) | |
2104 | { | |
2105 | ppc_4xx_eth_initialize(bis); | |
4f92ac36 SR |
2106 | if (emac0_dev) { |
2107 | return ppc_4xx_eth_init(emac0_dev, bis); | |
2108 | } else { | |
2109 | printf("ERROR: ethaddr not set!\n"); | |
2110 | return -1; | |
2111 | } | |
d6c61aab SR |
2112 | } |
2113 | ||
2114 | int eth_send(volatile void *packet, int length) | |
2115 | { | |
d6c61aab SR |
2116 | return (ppc_4xx_eth_send(emac0_dev, packet, length)); |
2117 | } | |
2118 | ||
2119 | int eth_rx(void) | |
2120 | { | |
2121 | return (ppc_4xx_eth_rx(emac0_dev)); | |
2122 | } | |
63ff004c MB |
2123 | |
2124 | int emac4xx_miiphy_initialize (bd_t * bis) | |
2125 | { | |
3a1ed1e1 | 2126 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
63ff004c | 2127 | miiphy_register ("ppc_4xx_eth0", |
6e7fb6ea | 2128 | emac4xx_miiphy_read, emac4xx_miiphy_write); |
63ff004c MB |
2129 | #endif |
2130 | ||
2131 | return 0; | |
2132 | } | |
d6c61aab SR |
2133 | #endif /* !defined(CONFIG_NET_MULTI) */ |
2134 | ||
3a1ed1e1 | 2135 | #endif |